diff options
| author | Jason Chen <jason.chen@linaro.org> | 2011-11-30 04:34:27 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-12-09 11:00:49 +0100 |
| commit | c0d96aed8c6dd925afe9ea35491a0cd458642a86 (patch) | |
| tree | c1b14f9a60b2ef4a3d8dffabd7327e70b2148cd8 /arch | |
| parent | Linux 3.2-rc4 (diff) | |
| download | linux-c0d96aed8c6dd925afe9ea35491a0cd458642a86.tar.xz linux-c0d96aed8c6dd925afe9ea35491a0cd458642a86.zip | |
MXC PWM: should active during DOZE/WAIT/DBG mode
Signed-off-by: Jason Chen <jason.chen@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: stable@kernel.org
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/plat-mxc/pwm.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 42d74ea59084..845de59f07ed 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -32,6 +32,9 @@ #define MX3_PWMSAR 0x0C /* PWM Sample Register */ #define MX3_PWMPR 0x10 /* PWM Period Register */ #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define MX3_PWMCR_DOZEEN (1 << 24) +#define MX3_PWMCR_WAITEN (1 << 23) +#define MX3_PWMCR_DBGEN (1 << 22) #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) #define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) @@ -77,7 +80,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR); - cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; + cr = MX3_PWMCR_PRESCALER(prescale) | + MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | + MX3_PWMCR_DBGEN | MX3_PWMCR_EN; if (cpu_is_mx25()) cr |= MX3_PWMCR_CLKSRC_IPG; |