Blackfin: unify DMA masks

Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

8 files changed, 50 insertions, 301 deletions

diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index e3c0dfa73d1b..5eb29502bbe4 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -16,36 +16,65 @@
 
 #define MAX_DMA_ADDRESS PAGE_OFFSET
 
-/*****************************************************************************
-*        Generic DMA  Declarations
-*
-****************************************************************************/
+/* DMA_CONFIG Masks */
+#define DMAEN			0x0001	/* DMA Channel Enable */
+#define WNR				0x0002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
+#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
+#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
+#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
+#define RESTART			0x0020	/* DMA Buffer Clear */
+#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
+#define DI_EN			0x0080	/* Data Interrupt Enable */
+#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
+#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
+#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
+#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
+#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
+#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
+#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
+#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
+#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
+#define NDSIZE			0x0f00	/* Next Descriptor Size */
+#define DMAFLOW			0x7000	/* Flow Control */
+#define DMAFLOW_STOP	0x0000	/* Stop Mode */
+#define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */
+#define DMAFLOW_ARRAY	0x4000	/* Descriptor Array Mode */
+#define DMAFLOW_SMALL	0x6000	/* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE	0x7000	/* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
+#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
+#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
+#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
 
 /*-------------------------
  * config reg bits value
  *-------------------------*/
-#define DATA_SIZE_8 		0
-#define DATA_SIZE_16 		1
-#define DATA_SIZE_32 		2
+#define DATA_SIZE_8			0
+#define DATA_SIZE_16		1
+#define DATA_SIZE_32		2
 
-#define DMA_FLOW_STOP 		0
-#define DMA_FLOW_AUTO 		1
-#define DMA_FLOW_ARRAY 		4
-#define DMA_FLOW_SMALL 		6
-#define DMA_FLOW_LARGE 		7
+#define DMA_FLOW_STOP		0
+#define DMA_FLOW_AUTO		1
+#define DMA_FLOW_ARRAY		4
+#define DMA_FLOW_SMALL		6
+#define DMA_FLOW_LARGE		7
 
-#define DIMENSION_LINEAR    0
-#define DIMENSION_2D           1
+#define DIMENSION_LINEAR	0
+#define DIMENSION_2D		1
 
-#define DIR_READ     0
-#define DIR_WRITE    1
+#define DIR_READ			0
+#define DIR_WRITE			1
 
-#define INTR_DISABLE   0
-#define INTR_ON_BUF    2
-#define INTR_ON_ROW    3
+#define INTR_DISABLE		0
+#define INTR_ON_BUF			2
+#define INTR_ON_ROW			3
 
 #define DMA_NOSYNC_KEEP_DMA_BUF	0
-#define DMA_SYNC_RESTART	1
+#define DMA_SYNC_RESTART		1
 
 struct dmasg {
 	void *next_desc_addr;
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index a97a2bbf9f33..9241205fb992 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -1260,33 +1260,6 @@
 
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
-#define DMAEN			0x0001		/* DMA Channel Enable							*/
-#define WNR				0x0002		/* Channel Direction (W/R*)						*/
-#define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
-#define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
-#define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
-#define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
-#define RESTART			0x0020		/* DMA Buffer Clear								*/
-#define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
-#define DI_EN			0x0080		/* Data Interrupt Enable						*/
-#define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
-#define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
-#define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
-#define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
-#define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
-#define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
-#define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
-#define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
-#define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
-#define NDSIZE	        	0x0900	/* Next Descriptor Size */
-#define DMAFLOW	        	0x7000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000		/* Stop Mode									*/
-#define DMAFLOW_AUTO		0x1000		/* Autobuffer Mode								*/
-#define DMAFLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
-#define DMAFLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
-#define DMAFLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
 #define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
@@ -1304,13 +1277,6 @@
 #define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
 #define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
-
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks													*/
 #define PORT_EN			0x0001		/* PPI Port Enable					*/
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index da42e9c2c69c..8b18b5359210 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -1269,33 +1269,6 @@
 
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
-#define DMAEN			0x0001		/* DMA Channel Enable							*/
-#define WNR				0x0002		/* Channel Direction (W/R*)						*/
-#define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
-#define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
-#define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
-#define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
-#define RESTART			0x0020		/* DMA Buffer Clear								*/
-#define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
-#define DI_EN			0x0080		/* Data Interrupt Enable						*/
-#define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
-#define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
-#define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
-#define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
-#define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
-#define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
-#define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
-#define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
-#define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
-#define NDSIZE	        	0x0900	/* Next Descriptor Size */
-#define DMAFLOW	        	0x7000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000		/* Stop Mode									*/
-#define DMAFLOW_AUTO		0x1000		/* Autobuffer Mode								*/
-#define DMAFLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
-#define DMAFLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
-#define DMAFLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
 #define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
@@ -1313,13 +1286,6 @@
 #define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
 #define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
-
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks													*/
 #define PORT_EN			0x0001		/* PPI Port Enable					*/
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 7e61fe762df2..e9ff491c0953 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -637,54 +637,7 @@
 
 /* **********  DMA CONTROLLER MASKS  *********************8 */
 
-/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN	        0x00000001	/* Channel Enable */
-#define WNR	   	0x00000002	/* Channel Direction (W/R*) */
-#define WDSIZE_8	0x00000000	/* Word Size 8 bits */
-#define WDSIZE_16	0x00000004	/* Word Size 16 bits */
-#define WDSIZE_32	0x00000008	/* Word Size 32 bits */
-#define DMA2D	        0x00000010	/* 2D/1D* Mode */
-#define RESTART         0x00000020	/* Restart */
-#define DI_SEL	        0x00000040	/* Data Interrupt Select */
-#define DI_EN	        0x00000080	/* Data Interrupt Enable */
-#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1                                             */
-#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2                                             */
-#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3                                             */
-#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4                                             */
-#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5                                             */
-#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6                                             */
-#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7                                             */
-#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8                                             */
-#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9                                             */
-#define NDSIZE	        0x00000900	/* Next Descriptor Size */
-#define DMAFLOW	        0x00007000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000	/* Stop Mode */
-#define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
-#define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
-#define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
-
-#define DMAEN_P	            	0	/* Channel Enable */
-#define WNR_P	            	1	/* Channel Direction (W/R*) */
-#define DMA2D_P	        	4	/* 2D/1D* Mode */
-#define RESTART_P	      	5	/* Restart */
-#define DI_SEL_P	     	6	/* Data Interrupt Select */
-#define DI_EN_P	            	7	/* Data Interrupt Enable */
-
-/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE		0x00000001	/* DMA Done Indicator */
-#define DMA_ERR	        	0x00000002	/* DMA Error Indicator */
-#define DFETCH	            	0x00000004	/* Descriptor Fetch Indicator */
-#define DMA_RUN	            	0x00000008	/* DMA Running Indicator */
-
-#define DMA_DONE_P	    	0	/* DMA Done Indicator */
-#define DMA_ERR_P     		1	/* DMA Error Indicator */
-#define DFETCH_P     		2	/* Descriptor Fetch Indicator */
-#define DMA_RUN_P     		3	/* DMA Running Indicator */
-
-/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 
 #define CTYPE	            0x00000040	/* DMA Channel Type Indicator */
 #define CTYPE_P             6	/* DMA Channel Type Indicator BIT POSITION */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 868e1a139944..066d5c261f47 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1584,34 +1584,6 @@
 #define BGSTAT			0x0020	/* Bus Grant Status                                             */
 
 /* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
-#define DMAEN			0x0001	/* DMA Channel Enable                                                   */
-#define WNR				0x0002	/* Channel Direction (W/R*)                                             */
-#define WDSIZE_8		0x0000	/* Transfer Word Size = 8                                               */
-#define WDSIZE_16		0x0004	/* Transfer Word Size = 16                                              */
-#define WDSIZE_32		0x0008	/* Transfer Word Size = 32                                              */
-#define DMA2D			0x0010	/* DMA Mode (2D/1D*)                                                    */
-#define RESTART			0x0020	/* DMA Buffer Clear                                                             */
-#define DI_SEL			0x0040	/* Data Interrupt Timing Select                                 */
-#define DI_EN			0x0080	/* Data Interrupt Enable                                                */
-#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1                                             */
-#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2                                             */
-#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3                                             */
-#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4                                             */
-#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5                                             */
-#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6                                             */
-#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7                                             */
-#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8                                             */
-#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9                                             */
-#define NDSIZE	        	0x0900	/* Next Descriptor Size */
-
-#define DMAFLOW	        	0x7000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000	/* Stop Mode */
-#define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
-#define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
-#define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
 #define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)      */
@@ -1629,12 +1601,6 @@
 #define	PMAP_UART1RX	0xA000	/*              UART1 Port Receive DMA                                          */
 #define	PMAP_UART1TX	0xB000	/*              UART1 Port Transmit DMA                                         */
 
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status      */
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status           */
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator        */
-
 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
 /*  PPI_CONTROL Masks													*/
 #define PORT_EN			0x0001	/* PPI Port Enable                                      */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5375819b6147..fac563e6f62f 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1757,52 +1757,6 @@
 
 
 /* **********  DMA CONTROLLER MASKS  ***********************/
-/* DMAx_CONFIG,	MDMA_yy_CONFIG Masks */
-#define	DMAEN		0x0001	/* Channel Enable */
-#define	WNR			0x0002	/* Channel Direction (W/R*) */
-#define	WDSIZE_8	0x0000	/* Word	Size 8 bits */
-#define	WDSIZE_16	0x0004	/* Word	Size 16	bits */
-#define	WDSIZE_32	0x0008	/* Word	Size 32	bits */
-#define	DMA2D		0x0010	/* 2D/1D* Mode */
-#define	RESTART		0x0020	/* Restart */
-#define	DI_SEL		0x0040	/* Data	Interrupt Select */
-#define	DI_EN		0x0080	/* Data	Interrupt Enable */
-#define	NDSIZE		0x0900	/* Next	Descriptor Size */
-#define	NDSIZE_0	0x0000	/* Next	Descriptor Size	= 0 (Stop/Autobuffer) */
-#define	NDSIZE_1	0x0100	/* Next	Descriptor Size	= 1 */
-#define	NDSIZE_2	0x0200	/* Next	Descriptor Size	= 2 */
-#define	NDSIZE_3	0x0300	/* Next	Descriptor Size	= 3 */
-#define	NDSIZE_4	0x0400	/* Next	Descriptor Size	= 4 */
-#define	NDSIZE_5	0x0500	/* Next	Descriptor Size	= 5 */
-#define	NDSIZE_6	0x0600	/* Next	Descriptor Size	= 6 */
-#define	NDSIZE_7	0x0700	/* Next	Descriptor Size	= 7 */
-#define	NDSIZE_8	0x0800	/* Next	Descriptor Size	= 8 */
-#define	NDSIZE_9	0x0900	/* Next	Descriptor Size	= 9 */
-
-#define DMAFLOW			0x7000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000	/* Stop Mode */
-#define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
-#define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
-#define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
-
-#define	DMAEN_P		0x0		/* Channel Enable */
-#define	WNR_P		0x1		/* Channel Direction (W/R*) */
-#define	DMA2D_P		0x4		/* 2D/1D* Mode */
-#define	RESTART_P	0x5		/* Restart */
-#define	DI_SEL_P	0x6		/* Data	Interrupt Select */
-#define	DI_EN_P		0x7		/* Data	Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define	DMA_DONE	0x0001	/* DMA Done Indicator */
-#define	DMA_ERR		0x0002	/* DMA Error Indicator */
-#define	DFETCH		0x0004	/* Descriptor Fetch Indicator */
-#define	DMA_RUN		0x0008	/* DMA Running Indicator */
-
-#define	DMA_DONE_P	0x0		/* DMA Done Indicator */
-#define	DMA_ERR_P	0x1		/* DMA Error Indicator */
-#define	DFETCH_P	0x2		/* Descriptor Fetch Indicator */
-#define	DMA_RUN_P	0x3		/* DMA Running Indicator */
 
 /* DMAx_PERIPHERAL_MAP,	MDMA_yy_PERIPHERAL_MAP Masks */
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 6d97b4e892b4..ab04d137fd8b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1609,44 +1609,6 @@
 #define                 PINT2  0x40000000 /* Pin Interrupt 2 */
 #define                 PINT3  0x80000000 /* Pin Interrupt 3 */
 
-/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
-
-#define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                       WNR  0x2        /* DMA Direction */
-#define                  WDSIZE_8  0x0        /* Transfer Word Size = 8 */
-#define                 WDSIZE_16  0x4        /* Transfer Word Size = 16 */
-#define                 WDSIZE_32  0x8        /* Transfer Word Size = 32 */
-#define                     DMA2D  0x10       /* DMA Mode */
-#define                   RESTART  0x20       /* Work Unit Transitions */
-#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                     DI_EN  0x80       /* Data Interrupt Enable */
-
-#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
-#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */
-#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */
-#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */
-#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */
-#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */
-#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */
-#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */
-#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */
-#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */
-
-#define                   DMAFLOW  0xf000     /* Next Operation */
-#define              DMAFLOW_STOP  0x0000     /* Stop Mode */
-#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */
-#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */
-#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */
-#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */
-
-/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   DMA_RUN  0x8        /* DMA Channel Running */
-
 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
 
 #define                     CTYPE  0x40       /* DMA Channel Type */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index c2f9c8f54eab..4c8e36b7fb33 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1096,53 +1096,6 @@
 
 /* **********  DMA CONTROLLER MASKS  *********************8 */
 
-/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
-#define DMAEN	        0x00000001	/* Channel Enable */
-#define WNR	   	0x00000002	/* Channel Direction (W/R*) */
-#define WDSIZE_8	0x00000000	/* Word Size 8 bits */
-#define WDSIZE_16	0x00000004	/* Word Size 16 bits */
-#define WDSIZE_32	0x00000008	/* Word Size 32 bits */
-#define DMA2D	        0x00000010	/* 2D/1D* Mode */
-#define RESTART         0x00000020	/* Restart */
-#define DI_SEL	        0x00000040	/* Data Interrupt Select */
-#define DI_EN	        0x00000080	/* Data Interrupt Enable */
-#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1                                             */
-#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2                                             */
-#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3                                             */
-#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4                                             */
-#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5                                             */
-#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6                                             */
-#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7                                             */
-#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8                                             */
-#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9                                             */
-#define NDSIZE	        0x00000900	/* Next Descriptor Size */
-#define DMAFLOW	        0x00007000	/* Flow Control */
-#define DMAFLOW_STOP		0x0000	/* Stop Mode */
-#define DMAFLOW_AUTO		0x1000	/* Autobuffer Mode */
-#define DMAFLOW_ARRAY		0x4000	/* Descriptor Array Mode */
-#define DMAFLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
-
-#define DMAEN_P	            	0	/* Channel Enable */
-#define WNR_P	            	1	/* Channel Direction (W/R*) */
-#define DMA2D_P	        	4	/* 2D/1D* Mode */
-#define RESTART_P	      	5	/* Restart */
-#define DI_SEL_P	     	6	/* Data Interrupt Select */
-#define DI_EN_P	            	7	/* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE		0x00000001	/* DMA Done Indicator */
-#define DMA_ERR	        	0x00000002	/* DMA Error Indicator */
-#define DFETCH	            	0x00000004	/* Descriptor Fetch Indicator */
-#define DMA_RUN	            	0x00000008	/* DMA Running Indicator */
-
-#define DMA_DONE_P	    	0	/* DMA Done Indicator */
-#define DMA_ERR_P     		1	/* DMA Error Indicator */
-#define DFETCH_P     		2	/* Descriptor Fetch Indicator */
-#define DMA_RUN_P     		3	/* DMA Running Indicator */
-
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
 
 #define CTYPE	            0x00000040	/* DMA Channel Type Indicator */