diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-04-08 13:47:05 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-30 14:53:05 +0200 |
| commit | f31318fdf324901ce5a17ccc3d71213117fb44af (patch) | |
| tree | 9bad1a2a21aeedb77fc3e23fb3826af396dabd62 /arch | |
| parent | MIPS: uasm: Add sllv uasm instruction (diff) | |
| download | linux-f31318fdf324901ce5a17ccc3d71213117fb44af.tar.xz linux-f31318fdf324901ce5a17ccc3d71213117fb44af.zip | |
MIPS: uasm: Add srlv uasm instruction
It will be used later on by bpf-jit
[ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6726/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/uasm.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm-micromips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm-mips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm.c | 7 |
5 files changed, 8 insertions, 3 deletions
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3001b1868a45..f1315ce7e449 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -143,6 +143,7 @@ Ip_u2u1u3(_sll); Ip_u3u2u1(_sllv); Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); +Ip_u3u2u1(_srlv); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_u1(_sync); diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 217d696bd1d3..abcdebe60e70 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -253,6 +253,7 @@ enum mm_32a_minor_op { mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, mm_sra_op = 0x080, + mm_srlv32_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c index e0a8df070e4b..b2348003b10f 100644 --- a/arch/mips/mm/uasm-micromips.c +++ b/arch/mips/mm/uasm-micromips.c @@ -97,6 +97,7 @@ static struct insn insn_table_MM[] = { { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD }, { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, + { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD }, { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index 086c590c9997..3d68c001fcb3 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -106,6 +106,7 @@ static struct insn insn_table[] = { { insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD }, { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD }, { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE }, diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 9372d8296ced..567003ca5b18 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -52,9 +52,9 @@ enum opcode { insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, - insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_subu, - insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, - insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield, + insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv, + insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, + insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield, }; struct insn { @@ -283,6 +283,7 @@ I_u2u1u3(_sll) I_u3u2u1(_sllv) I_u2u1u3(_sra) I_u2u1u3(_srl) +I_u3u2u1(_srlv) I_u2u1u3(_rotr) I_u3u1u2(_subu) I_u2s3u1(_sw) |