diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2018-07-09 20:47:20 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2018-08-30 15:38:26 +0200 |
| commit | 12b2982a1f72ce453d76da977e1dad422b2f34ad (patch) | |
| tree | 7d0039f6f439f8ad135e9db9bbbe27f4886ff24c /arch | |
| parent | ARM: dts: socfpga: set timer interrupt to edge sensitive (diff) | |
| download | linux-12b2982a1f72ce453d76da977e1dad422b2f34ad.tar.xz linux-12b2982a1f72ce453d76da977e1dad422b2f34ad.zip | |
ARM: dts: arria10: update NAND clocking
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). This
patch adds a nand_clk, which is derived from the nand_x_clk, but has a
fixed divider of 4, and the nand_ecc_clk, which is derived from the
nand_x_clk.
Update the NAND node to use the additional clocks.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index cebbf0b2808e..266c67878a15 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -377,13 +377,28 @@ clk-gate = <0xC8 11>; }; - nand_clk: nand_clk { + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; clocks = <&l4_mp_clk>; clk-gate = <0xC8 10>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xC8 10>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + fixed-divider = <4>; + clk-gate = <0xC8 10>; + }; + spi_m_clk: spi_m_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; @@ -650,7 +665,8 @@ reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; dma-mask = <0xffffffff>; - clocks = <&nand_clk>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; status = "disabled"; }; |