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authorBryan O'Donoghue <bodonoghue@codehermit.ie>2008-02-04 00:21:29 +0100
committerKumar Gala <galak@kernel.crashing.org>2008-02-06 06:33:22 +0100
commit03bbfe8b97eb277f1af27fef5a14224f7878a983 (patch)
treefa9710df6d0b0ee982dce3a0c68c4e2fff1cba43 /arch
parent[POWERPC] 83xx: Add rtc node to mpc8313erdb dts (diff)
downloadlinux-03bbfe8b97eb277f1af27fef5a14224f7878a983.tar.xz
linux-03bbfe8b97eb277f1af27fef5a14224f7878a983.zip
[POWERPC] 8xx: Add clock-frequency to adder875 and mpc885ads dts
cpm_uart_core has a dependency on fsl,cpm-brg/clock-frequency, this means that a .dts that uses the cpm uart driver needs to supply a clock-frequency entry for get_brgfreq to return a meaningful number. Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/adder875-redboot.dts1
-rw-r--r--arch/powerpc/boot/dts/adder875-uboot.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts1
3 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/adder875-redboot.dts b/arch/powerpc/boot/dts/adder875-redboot.dts
index 930bfb3894eb..28e9cd3d7a21 100644
--- a/arch/powerpc/boot/dts/adder875-redboot.dts
+++ b/arch/powerpc/boot/dts/adder875-redboot.dts
@@ -151,6 +151,7 @@
compatible = "fsl,mpc875-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
+ clock-frequency = <50000000>;
reg = <0x9f0 0x10>;
};
diff --git a/arch/powerpc/boot/dts/adder875-uboot.dts b/arch/powerpc/boot/dts/adder875-uboot.dts
index 0197242dacfb..54fb60ec03e5 100644
--- a/arch/powerpc/boot/dts/adder875-uboot.dts
+++ b/arch/powerpc/boot/dts/adder875-uboot.dts
@@ -150,6 +150,7 @@
compatible = "fsl,mpc875-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
+ clock-frequency = <50000000>;
reg = <0x9f0 0x10>;
};
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index 8848e637293e..d84a012c2aaf 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -166,6 +166,7 @@
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
+ clock-frequency = <0>;
reg = <9f0 10>;
};