diff options
| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2020-07-27 12:34:55 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2020-07-27 12:34:55 +0200 |
| commit | 80e30368669e0387d9778b15bd1b985074725a2e (patch) | |
| tree | fb41faa9d4a067cf823bf04a5f13b5dee5fdb67f /arch | |
| parent | cpufreq: intel_pstate: Fix active mode setting from command line (diff) | |
| parent | cpufreq: intel_pstate: Avoid enabling HWP if EPP is not supported (diff) | |
| download | linux-80e30368669e0387d9778b15bd1b985074725a2e.tar.xz linux-80e30368669e0387d9778b15bd1b985074725a2e.zip | |
Merge back cpufreq material for v5.9.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/platforms/cell/cpufreq_spudemand.c | 26 | ||||
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 6 |
2 files changed, 6 insertions, 26 deletions
diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c index 55b31eadb3c8..ca7849e113d7 100644 --- a/arch/powerpc/platforms/cell/cpufreq_spudemand.c +++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c @@ -126,30 +126,8 @@ static struct cpufreq_governor spu_governor = { .stop = spu_gov_stop, .owner = THIS_MODULE, }; - -/* - * module init and destoy - */ - -static int __init spu_gov_init(void) -{ - int ret; - - ret = cpufreq_register_governor(&spu_governor); - if (ret) - printk(KERN_ERR "registration of governor failed\n"); - return ret; -} - -static void __exit spu_gov_exit(void) -{ - cpufreq_unregister_governor(&spu_governor); -} - - -module_init(spu_gov_init); -module_exit(spu_gov_exit); +cpufreq_governor_init(spu_governor); +cpufreq_governor_exit(spu_governor); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>"); - diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e8370e64a155..21b409195b46 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -149,6 +149,10 @@ #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 + +#define MSR_IA32_POWER_CTL 0x000001fc +#define MSR_IA32_POWER_CTL_BIT_EE 19 + #define MSR_LBR_NHM_FROM 0x00000680 #define MSR_LBR_NHM_TO 0x000006c0 #define MSR_LBR_CORE_FROM 0x00000040 @@ -253,8 +257,6 @@ #define MSR_PEBS_FRONTEND 0x000003f7 -#define MSR_IA32_POWER_CTL 0x000001fc - #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 |