diff options
| author | Bo Yan <byan@nvidia.com> | 2015-03-31 22:30:48 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-04-01 12:12:03 +0200 |
| commit | 6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998 (patch) | |
| tree | 3b3614dd3e76d608abb56fa9bf781c437f18b66b /arch | |
| parent | arm64: errata: add workaround for cortex-a53 erratum #845719 (diff) | |
| download | linux-6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998.tar.xz linux-6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998.zip | |
arm64: fix midr range for Cortex-A57 erratum 832075
Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.
Cc: stable@vger.kernel.org # 3.19+
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Bo Yan <byan@nvidia.com>
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 4672860def1f..6ffd91438560 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -70,7 +70,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = { /* Cortex-A57 r0p0 - r1p2 */ .desc = "ARM erratum 832075", .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, - MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12), + MIDR_RANGE(MIDR_CORTEX_A57, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 2), }, #endif #ifdef CONFIG_ARM64_ERRATUM_845719 |