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authorChen-Yu Tsai <wens@csie.org>2015-06-02 12:04:02 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-06-02 23:14:42 +0200
commit63c6509b0d8bb48454b7b16b560a1779dec581c1 (patch)
tree9d21cc56e2a83e91831ba27ca116005970a201a7 /arch
parentARM: dts: sun8i: Add pinmux setting for 8bit mmc2 (diff)
downloadlinux-63c6509b0d8bb48454b7b16b560a1779dec581c1.tar.xz
linux-63c6509b0d8bb48454b7b16b560a1779dec581c1.zip
ARM: dts: sun8i-a33: Add pinmux setting for uart0 on PB pins
The A33 adds an additional pinmux option for uart0 on the PB pins. This was not present on the A23. Nor is it available on the H3, which does not have the PB pingroup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 9b43bc6e7926..85ee08098b7b 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -86,4 +86,12 @@
compatible = "allwinner,sun8i-a33-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
};