diff options
| author | Jayachandran C <jnair@caviumnetworks.com> | 2018-01-19 13:22:47 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-01-23 20:59:20 +0100 |
| commit | f3d795d9b360523beca6d13ba64c2c532f601149 (patch) | |
| tree | c070edac0a5e8fe9bab727073dbeb1f72378493c /arch | |
| parent | arm64: Run enable method for errata work arounds on late CPUs (diff) | |
| download | linux-f3d795d9b360523beca6d13ba64c2c532f601149.tar.xz linux-f3d795d9b360523beca6d13ba64c2c532f601149.zip | |
arm64: Branch predictor hardening for Cavium ThunderX2
Use PSCI based mitigation for speculative execution attacks targeting
the branch predictor. We use the same mechanism as the one used for
Cortex-A CPUs, we expect the PSCI version call to have a side effect
of clearing the BTBs.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 54e41dfe41f6..ed6881882231 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -359,6 +359,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + .enable = enable_psci_bp_hardening, + }, #endif { } |