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authorKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>2018-04-28 22:34:17 +0200
committerThomas Gleixner <tglx@linutronix.de>2018-05-03 13:55:48 +0200
commit0cc5fa00b0a88dad140b4e5c2cead9951ad36822 (patch)
tree05dc39ce2318600ca81e6eff4135fdfae0c6857e /arch
parentx86/bugs: Expose /sys/../spec_store_bypass (diff)
downloadlinux-0cc5fa00b0a88dad140b4e5c2cead9951ad36822.tar.xz
linux-0cc5fa00b0a88dad140b4e5c2cead9951ad36822.zip
x86/cpufeatures: Add X86_FEATURE_RDS
Add the CPU feature bit CPUID.7.0.EDX[31] which indicates whether the CPU supports Reduced Data Speculation. [ tglx: Split it out from a later patch ] Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/cpufeatures.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 3493b58ef2cc..48305a1ddfd6 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -334,6 +334,7 @@
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
+#define X86_FEATURE_RDS (18*32+31) /* Reduced Data Speculation */
/*
* BUG word(s)