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| author | Javi Merino <javi.merino@arm.com> | 2011-11-16 12:36:39 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-15 22:10:49 +0100 |
| commit | 4272f98a1ae81709fc5c804c33c044064e419cd9 (patch) | |
| tree | 0e3af4e730a6f1bbec98f3e4808dd272e8ae8e58 /arch | |
| parent | ARM: 7325/1: fix v7 boot with lockdep enabled (diff) | |
| download | linux-4272f98a1ae81709fc5c804c33c044064e419cd9.tar.xz linux-4272f98a1ae81709fc5c804c33c044064e419cd9.zip | |
ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field
dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit
field in the Channel Control Register (see Table 3-21 of the DMA-330
Technical Reference Manual) and should be programmed as such.
Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com>
Signed-off-by: Javi Merino <javi.merino@arm.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/hardware/pl330.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h index 575fa8186ca0..c1821385abfa 100644 --- a/arch/arm/include/asm/hardware/pl330.h +++ b/arch/arm/include/asm/hardware/pl330.h @@ -41,7 +41,7 @@ enum pl330_dstcachectrl { DCCTRL1, /* Bufferable only */ DCCTRL2, /* Cacheable, but do not allocate */ DCCTRL3, /* Cacheable and bufferable, but do not allocate */ - DINVALID1 = 8, + DINVALID1, /* AWCACHE = 0x1000 */ DINVALID2, DCCTRL6, /* Cacheable write-through, allocate on writes only */ DCCTRL7, /* Cacheable write-back, allocate on writes only */ |