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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-07-11 23:51:58 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-07-15 06:20:39 +0200 |
| commit | 4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e (patch) | |
| tree | bf9472a2ceab27ae04308e0008bf5bc8391ed9ac /arch | |
| parent | ARM: dts: r8a7792: add SMP support (diff) | |
| download | linux-4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e.tar.xz linux-4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e.zip | |
ARM: dts: r8a7792: add PLL1 divided by 2 clock
Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the
latter hasn't been added to the R8A7792 device tree. This patch corrects
that oversight.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 75256ef4a04d..d5fd0762e2d6 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -284,6 +284,13 @@ }; /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |