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| author | Jiri Kosina <jkosina@suse.cz> | 2010-06-16 18:08:13 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2010-06-16 18:08:13 +0200 |
| commit | f1bbbb6912662b9f6070c5bfc4ca9eb1f06a9d5b (patch) | |
| tree | c2c130a74be25b0b2dff992e1a195e2728bdaadd /arch | |
| parent | fix typos concerning "instead" (diff) | |
| parent | Linux 2.6.35-rc3 (diff) | |
| download | linux-f1bbbb6912662b9f6070c5bfc4ca9eb1f06a9d5b.tar.xz linux-f1bbbb6912662b9f6070c5bfc4ca9eb1f06a9d5b.zip | |
Merge branch 'master' into for-next
Diffstat (limited to 'arch')
752 files changed, 28986 insertions, 16560 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index b7193986cbf9..3e2e540a0f2a 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -51,10 +51,6 @@ config GENERIC_TIME bool default y -config ARCH_USES_GETTIMEOFFSET - bool - default y - config GENERIC_CMOS_UPDATE def_bool y @@ -65,6 +61,9 @@ config ZONE_DMA config NEED_DMA_MAP_STATE def_bool y +config NEED_SG_DMA_LENGTH + def_bool y + config GENERIC_ISA_DMA bool default y diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h index 296da1d5ed57..1dce24bc455a 100644 --- a/arch/alpha/include/asm/bitops.h +++ b/arch/alpha/include/asm/bitops.h @@ -438,22 +438,20 @@ static inline unsigned int __arch_hweight8(unsigned int w) /* * Every architecture must define this function. It's the fastest - * way of searching a 140-bit bitmap where the first 100 bits are - * unlikely to be set. It's guaranteed that at least one of the 140 - * bits is set. + * way of searching a 100-bit bitmap. It's guaranteed that at least + * one of the 100 bits is cleared. */ static inline unsigned long -sched_find_first_bit(unsigned long b[3]) +sched_find_first_bit(const unsigned long b[2]) { - unsigned long b0 = b[0], b1 = b[1], b2 = b[2]; - unsigned long ofs; + unsigned long b0, b1, ofs, tmp; - ofs = (b1 ? 64 : 128); - b1 = (b1 ? b1 : b2); - ofs = (b0 ? 0 : ofs); - b0 = (b0 ? b0 : b1); + b0 = b[0]; + b1 = b[1]; + ofs = (b0 ? 0 : 64); + tmp = (b0 ? b0 : b1); - return __ffs(b0) + ofs; + return __ffs(tmp) + ofs; } #include <asm-generic/bitops/ext2-non-atomic.h> diff --git a/arch/alpha/include/asm/scatterlist.h b/arch/alpha/include/asm/scatterlist.h index 440747ca6349..5728c52a7412 100644 --- a/arch/alpha/include/asm/scatterlist.h +++ b/arch/alpha/include/asm/scatterlist.h @@ -1,24 +1,7 @@ #ifndef _ALPHA_SCATTERLIST_H #define _ALPHA_SCATTERLIST_H -#include <asm/page.h> -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - - unsigned int length; - - dma_addr_t dma_address; - __u32 dma_length; -}; - -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->dma_length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (~0UL) diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index 5465e932e568..1efbed82c0fd 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -51,6 +51,7 @@ #include <linux/mc146818rtc.h> #include <linux/time.h> #include <linux/timex.h> +#include <linux/clocksource.h> #include "proto.h" #include "irq_impl.h" @@ -332,6 +333,34 @@ rpcc_after_update_in_progress(void) return rpcc(); } +#ifndef CONFIG_SMP +/* Until and unless we figure out how to get cpu cycle counters + in sync and keep them there, we can't use the rpcc. */ +static cycle_t read_rpcc(struct clocksource *cs) +{ + cycle_t ret = (cycle_t)rpcc(); + return ret; +} + +static struct clocksource clocksource_rpcc = { + .name = "rpcc", + .rating = 300, + .read = read_rpcc, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS +}; + +static inline void register_rpcc_clocksource(long cycle_freq) +{ + clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4); + clocksource_register(&clocksource_rpcc); +} +#else /* !CONFIG_SMP */ +static inline void register_rpcc_clocksource(long cycle_freq) +{ +} +#endif /* !CONFIG_SMP */ + void __init time_init(void) { @@ -385,6 +414,8 @@ time_init(void) __you_loose(); } + register_rpcc_clocksource(cycle_freq); + state.last_time = cc1; state.scaled_ticks_per_cycle = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq; @@ -395,44 +426,6 @@ time_init(void) } /* - * Use the cycle counter to estimate an displacement from the last time - * tick. Unfortunately the Alpha designers made only the low 32-bits of - * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz - * part. So we can't do the "find absolute time in terms of cycles" thing - * that the other ports do. - */ -u32 arch_gettimeoffset(void) -{ -#ifdef CONFIG_SMP - /* Until and unless we figure out how to get cpu cycle counters - in sync and keep them there, we can't use the rpcc tricks. */ - return 0; -#else - unsigned long delta_cycles, delta_usec, partial_tick; - - delta_cycles = rpcc() - state.last_time; - partial_tick = state.partial_tick; - /* - * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks) - * = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks) - * = cycles * (s_t_p_c) * 15625 / (2**42 * ticks) - * - * which, given a 600MHz cycle and a 1024Hz tick, has a - * dynamic range of about 1.7e17, which is less than the - * 1.8e19 in an unsigned long, so we are safe from overflow. - * - * Round, but with .5 up always, since .5 to even is harder - * with no clear gain. - */ - - delta_usec = (delta_cycles * state.scaled_ticks_per_cycle - + partial_tick) * 15625; - delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2; - return delta_usec * 1000; -#endif -} - -/* * In order to set the CMOS clock precisely, set_rtc_mmss has to be * called 500 ms after the second nowtime has started, because when * nowtime is written into the registers of the CMOS clock, it will diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c index 00a31deaa96e..fadd5f882ff9 100644 --- a/arch/alpha/mm/fault.c +++ b/arch/alpha/mm/fault.c @@ -142,7 +142,6 @@ do_page_fault(unsigned long address, unsigned long mmcsr, goto bad_area; } - survive: /* If for any reason at all we couldn't handle the fault, make sure we exit gracefully rather than endlessly redo the fault. */ @@ -188,16 +187,10 @@ do_page_fault(unsigned long address, unsigned long mmcsr, /* We ran out of memory, or some other thing happened to us that made us unable to handle the page fault gracefully. */ out_of_memory: - if (is_global_init(current)) { - yield(); - down_read(&mm->mmap_sem); - goto survive; - } - printk(KERN_ALERT "VM: killing process %s(%d)\n", - current->comm, task_pid_nr(current)); if (!user_mode(regs)) goto no_context; - do_group_exit(SIGKILL); + pagefault_out_of_memory(); + return; do_sigbus: /* Send a sigbus, regardless of whether we were in kernel diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d70cece2ea2..1f254bd6c937 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -671,6 +671,7 @@ config ARCH_S5P6440 select CPU_V6 select GENERIC_GPIO select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET help Samsung S5P6440 CPU based systems @@ -679,17 +680,19 @@ config ARCH_S5P6442 select CPU_V6 select GENERIC_GPIO select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET help Samsung S5P6442 CPU based systems -config ARCH_S5PC1XX - bool "Samsung S5PC1XX" +config ARCH_S5PC100 + bool "Samsung S5PC100" select GENERIC_GPIO select HAVE_CLK select CPU_V7 select ARM_L1_CACHE_SHIFT_6 + select ARCH_USES_GETTIMEOFFSET help - Samsung S5PC1XX series based systems + Samsung S5PC100 series based systems config ARCH_S5PV210 bool "Samsung S5PV210/S5PC110" @@ -697,6 +700,7 @@ config ARCH_S5PV210 select GENERIC_GPIO select HAVE_CLK select ARM_L1_CACHE_SHIFT_6 + select ARCH_USES_GETTIMEOFFSET help Samsung S5PV210/S5PC110 series based systems @@ -876,7 +880,7 @@ source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s5p/Kconfig" -source "arch/arm/plat-s5pc1xx/Kconfig" + source "arch/arm/plat-spear/Kconfig" if ARCH_S3C2410 @@ -896,9 +900,7 @@ source "arch/arm/mach-s5p6440/Kconfig" source "arch/arm/mach-s5p6442/Kconfig" -if ARCH_S5PC1XX source "arch/arm/mach-s5pc100/Kconfig" -endif source "arch/arm/mach-s5pv210/Kconfig" @@ -1419,6 +1421,17 @@ config CMDLINE time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs). +config CMDLINE_FORCE + bool "Always use the default kernel command string" + depends on CMDLINE != "" + help + Always use the default kernel command string, even if the boot + loader passes other arguments to the kernel. + This is useful if you cannot or don't want to change the + command-line options your boot loader passes to the kernel. + + If unsure, say N. + config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" depends on !ZBOOT_ROM diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b857fbe4314..64ba313724d2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -168,7 +168,7 @@ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5P6442) := s5p6442 -machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 +machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PV210) := s5pv210 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark @@ -198,7 +198,6 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung -plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung plat-$(CONFIG_PLAT_S5P) := s5p samsung plat-$(CONFIG_PLAT_SPEAR) := spear plat-$(CONFIG_PLAT_VERSATILE) := versatile diff --git a/arch/arm/boot/bootp/bootp.lds b/arch/arm/boot/bootp/bootp.lds index 8e3d81ce695e..fc54394f4340 100644 --- a/arch/arm/boot/bootp/bootp.lds +++ b/arch/arm/boot/bootp/bootp.lds @@ -19,7 +19,7 @@ SECTIONS initrd_size = initrd_end - initrd_start; _etext = .; } - + .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index a52a27c1d9be..6f80665f477e 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -951,8 +951,6 @@ static int sa1111_resume(struct platform_device *dev) if (!save) return 0; - spin_lock_irqsave(&sachip->lock, flags); - /* * Ensure that the SA1111 is still here. * FIXME: shouldn't do this here. @@ -969,6 +967,13 @@ static int sa1111_resume(struct platform_device *dev) * First of all, wake up the chip. */ sa1111_wake(sachip); + + /* + * Only lock for write ops. Also, sa1111_wake must be called with + * released spinlock! + */ + spin_lock_irqsave(&sachip->lock, flags); + sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0); sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1); diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig index 232f8eeb72e3..e4f4fb522bac 100644 --- a/arch/arm/configs/am3517_evm_defconfig +++ b/arch/arm/configs/am3517_evm_defconfig @@ -774,7 +774,57 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=4 +CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y +# CONFIG_OMAP2_DSS_RFBI is not set +CONFIG_OMAP2_DSS_VENC=y +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +CONFIG_PANEL_GENERIC=y +# CONFIG_PANEL_SHARP_LS037V7DW01 is not set +CONFIG_PANEL_SHARP_LQ043T1DG01=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index c88e9527a8ec..a708fd6d6ffe 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -809,7 +809,22 @@ CONFIG_SSB_POSSIBLE=y CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_MXC=y + + CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig index a6dd6d1af806..b02e371b0997 100644 --- a/arch/arm/configs/omap3_evm_defconfig +++ b/arch/arm/configs/omap3_evm_defconfig @@ -911,7 +911,56 @@ CONFIG_DAB=y # # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=4 +# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set +# CONFIG_OMAP2_DSS_RFBI is not set +CONFIG_OMAP2_DSS_VENC=y +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 +CONFIG_FB_OMAP2=y +# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set +# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +CONFIG_PANEL_GENERIC=y +# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set +CONFIG_PANEL_SHARP_LS037V7DW01=y # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig index 473f9e13f08b..56d4928cd4c9 100644 --- a/arch/arm/configs/rx51_defconfig +++ b/arch/arm/configs/rx51_defconfig @@ -784,6 +784,7 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_TWL4030=y # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -809,6 +810,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_INPUT_UINPUT=m # @@ -1110,7 +1112,40 @@ CONFIG_RADIO_ADAPTERS=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y + +# Frame buffer hardware drivers +# +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=0 +# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set +# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set +# CONFIG_OMAP2_DSS_DPI is not set +# CONFIG_OMAP2_DSS_RFBI is not set +# CONFIG_OMAP2_DSS_VENC is not set +CONFIG_OMAP2_DSS_SDI=y +# CONFIG_OMAP2_DSS_DSI is not set +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +# CONFIG_PANEL_GENERIC is not set +# CONFIG_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set +# CONFIG_PANEL_TOPPOLY_TDO35S is not set +# CONFIG_PANEL_TPO_TD043MTEA1 is not set +CONFIG_PANEL_ACX565AKM=y + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1127,6 +1162,8 @@ CONFIG_DISPLAY_SUPPORT=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y CONFIG_SOUND=y # CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 8e94c3caeb8c..44cea2ddd22b 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -1,14 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc2 +# Linux kernel version: 2.6.34 +# Fri May 28 19:15:48 2010 # CONFIG_ARM=y CONFIG_HAVE_PWM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y -# CONFIG_GENERIC_TIME is not set -# CONFIG_GENERIC_CLOCKEVENTS is not set -CONFIG_MMU=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -18,13 +19,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -34,6 +36,13 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -45,15 +54,16 @@ CONFIG_SYSVIPC_SYSCTL=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -69,6 +79,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -78,7 +89,6 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -91,19 +101,30 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_CLK=y -# CONFIG_SLOW_WORK is not set + +# +# GCOV-based kernel profiling +# +CONFIG_SLOW_WORK=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,7 +136,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -123,32 +144,64 @@ CONFIG_BLOCK=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set CONFIG_FREEZER=y # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -156,42 +209,37 @@ CONFIG_FREEZER=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set CONFIG_ARCH_S3C2410=y # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set -CONFIG_PLAT_S3C24XX=y -CONFIG_S3C2410_CLOCK=y -CONFIG_S3C24XX_DCLK=y -CONFIG_CPU_S3C244X=y -CONFIG_S3C24XX_PWM=y -CONFIG_S3C24XX_GPIO_EXTRA=128 -CONFIG_S3C24XX_GPIO_EXTRA64=y -CONFIG_S3C24XX_GPIO_EXTRA128=y -CONFIG_PM_SIMTEC=y -CONFIG_S3C2410_DMA=y -# CONFIG_S3C2410_DMA_DEBUG is not set -CONFIG_S3C_ADC=y -CONFIG_MACH_SMDK=y -CONFIG_PLAT_S3C=y -CONFIG_CPU_LLSERIAL_S3C2410=y -CONFIG_CPU_LLSERIAL_S3C2440=y +# CONFIG_PLAT_SPEAR is not set +CONFIG_PLAT_SAMSUNG=y # # Boot options @@ -199,15 +247,44 @@ CONFIG_CPU_LLSERIAL_S3C2440=y # CONFIG_S3C_BOOT_WATCHDOG is not set CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S3C_GPIO_PULL_UP=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_ADC=y +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_HWMON=y +CONFIG_S3C_DEV_FB=y +CONFIG_S3C_DEV_USB_HOST=y +CONFIG_S3C_DEV_WDT=y +CONFIG_S3C_DEV_NAND=y +CONFIG_S3C_DMA=y # # Power management # # CONFIG_SAMSUNG_PM_DEBUG is not set # CONFIG_SAMSUNG_PM_CHECK is not set -CONFIG_S3C_LOWLEVEL_UART_PORT=0 -CONFIG_S3C_GPIO_SPACE=0 -CONFIG_S3C_DEV_HSMMC=y +CONFIG_PLAT_S3C24XX=y +CONFIG_CPU_LLSERIAL_S3C2410=y +CONFIG_CPU_LLSERIAL_S3C2440=y +CONFIG_S3C2410_CLOCK=y +CONFIG_S3C2443_CLOCK=y +CONFIG_S3C24XX_DCLK=y +CONFIG_S3C24XX_PWM=y +CONFIG_S3C24XX_GPIO_EXTRA=128 +CONFIG_S3C24XX_GPIO_EXTRA64=y +CONFIG_S3C24XX_GPIO_EXTRA128=y +CONFIG_PM_SIMTEC=y +CONFIG_S3C2410_DMA=y +# CONFIG_S3C2410_DMA_DEBUG is not set +CONFIG_MACH_SMDK=y +CONFIG_S3C24XX_SIMTEC_AUDIO=y +CONFIG_S3C2410_SETUP_TS=y # # S3C2400 Machines @@ -224,8 +301,10 @@ CONFIG_MACH_BAST_IDE=y # CONFIG_ARCH_SMDK2410=y CONFIG_ARCH_H1940=y +# CONFIG_H1940BT is not set CONFIG_PM_H1940=y CONFIG_MACH_N30=y +CONFIG_MACH_N35=y CONFIG_ARCH_BAST=y CONFIG_MACH_OTOM=y CONFIG_MACH_AML_M5900=y @@ -246,26 +325,35 @@ CONFIG_MACH_SMDK2413=y CONFIG_MACH_S3C2413=y CONFIG_MACH_SMDK2412=y CONFIG_MACH_VSTMS=y +CONFIG_CPU_S3C2416=y +CONFIG_S3C2416_DMA=y + +# +# S3C2416 Machines +# +CONFIG_MACH_SMDK2416=y CONFIG_CPU_S3C2440=y +CONFIG_CPU_S3C2442=y +CONFIG_CPU_S3C244X=y +CONFIG_S3C2440_XTAL_12000000=y +CONFIG_S3C2440_XTAL_16934400=y CONFIG_S3C2440_DMA=y # -# S3C2440 Machines +# S3C2440 and S3C2442 Machines # CONFIG_MACH_ANUBIS=y +CONFIG_MACH_NEO1973_GTA02=y CONFIG_MACH_OSIRIS=y +CONFIG_MACH_OSIRIS_DVS=m CONFIG_MACH_RX3715=y CONFIG_ARCH_S3C2440=y CONFIG_MACH_NEXCODER_2440=y CONFIG_SMDK2440_CPU2440=y +CONFIG_SMDK2440_CPU2442=y CONFIG_MACH_AT2440EVB=y -CONFIG_CPU_S3C2442=y CONFIG_MACH_MINI2440=y - -# -# S3C2442 Machines -# -CONFIG_SMDK2440_CPU2442=y +CONFIG_MACH_RX1950=y CONFIG_CPU_S3C2443=y CONFIG_S3C2443_DMA=y @@ -283,7 +371,7 @@ CONFIG_CPU_32v4T=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV4T=y CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_V4WT=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y @@ -299,7 +387,7 @@ CONFIG_CPU_CP15_MMU=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set -# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 # # Bus support @@ -316,10 +404,11 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_HZ=200 # CONFIG_AEABI is not set -CONFIG_ARCH_FLATMEM_HAS_HOLES=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -330,14 +419,14 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options @@ -345,12 +434,14 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set # # CPU Power Management # +# CONFIG_CPU_FREQ is not set # CONFIG_CPU_IDLE is not set # @@ -384,6 +475,8 @@ CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_APM_EMULATION=m +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -391,7 +484,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m @@ -442,7 +534,9 @@ CONFIG_TCP_CONG_ILLINOIS=m # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_HYBLA is not set # CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_VENO is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" @@ -463,6 +557,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m # CONFIG_IPV6_MULTIPLE_TABLES is not set @@ -498,8 +593,19 @@ CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m # CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_LED=m @@ -508,9 +614,14 @@ CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set CONFIG_NETFILTER_XT_TARGET_TCPMSS=m # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m @@ -529,6 +640,7 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m @@ -536,7 +648,6 @@ CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -556,6 +667,7 @@ CONFIG_IP_VS_TAB_BITS=12 # CONFIG_IP_VS_PROTO_UDP is not set # CONFIG_IP_VS_PROTO_ESP is not set # CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set # # IPVS scheduler @@ -639,8 +751,10 @@ CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set # CONFIG_BRIDGE is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set @@ -653,6 +767,7 @@ CONFIG_IP6_NF_RAW=m # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y # CONFIG_DCB is not set @@ -666,6 +781,7 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_IRDA is not set CONFIG_BT=m CONFIG_BT_L2CAP=m +# CONFIG_BT_L2CAP_EXT_FEATURES is not set CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -687,19 +803,22 @@ CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set CONFIG_MAC80211=m - -# -# Rate control algorithm selection -# +CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y # CONFIG_MAC80211_RC_DEFAULT_PID is not set CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y @@ -710,6 +829,7 @@ CONFIG_MAC80211_LEDS=y # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set +# CONFIG_CAIF is not set # # Device Drivers @@ -719,6 +839,7 @@ CONFIG_MAC80211_LEDS=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -730,9 +851,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y @@ -752,6 +873,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set # CONFIG_MTD_OOPS is not set # @@ -793,6 +915,7 @@ CONFIG_MTD_ROM=y # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -805,9 +928,12 @@ CONFIG_MTD_ROM=y # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_NAND_ECC=y # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 # CONFIG_MTD_NAND_GPIO is not set CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_S3C2410=y @@ -843,6 +969,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_UB=m CONFIG_BLK_DEV_RAM=y @@ -851,19 +981,26 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set # CONFIG_C2PORT is not set # # EEPROM support # -CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=m CONFIG_EEPROM_LEGACY=m +# CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m +# CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y @@ -890,6 +1027,7 @@ CONFIG_BLK_DEV_PLATFORM=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -907,10 +1045,6 @@ CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set @@ -951,7 +1085,6 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_HAVE_PATA_PLATFORM=y # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -989,16 +1122,30 @@ CONFIG_DM9000_DEBUGLEVEL=4 # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_CS89x0 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set # CONFIG_NET_POCKET is not set CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y # CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_ZD1211RW is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -1012,6 +1159,7 @@ CONFIG_NETDEV_10000=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set # CONFIG_WAN is not set # CONFIG_PLIP is not set # CONFIG_PPP is not set @@ -1020,6 +1168,7 @@ CONFIG_NETDEV_10000=y # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support @@ -1027,6 +1176,7 @@ CONFIG_NETDEV_10000=y CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -1043,13 +1193,20 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -1057,6 +1214,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set CONFIG_MOUSE_APPLETOUCH=m @@ -1066,6 +1224,7 @@ CONFIG_MOUSE_BCM5974=m # CONFIG_MOUSE_PC110PAD is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=m CONFIG_JOYSTICK_A3D=m @@ -1102,10 +1261,15 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set @@ -1126,9 +1290,16 @@ CONFIG_TOUCHSCREEN_USB_IRTOUCH=y CONFIG_TOUCHSCREEN_USB_IDEALTEK=y CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC5UH=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set CONFIG_INPUT_ATI_REMOTE=m CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_KEYSPAN_REMOTE=m @@ -1136,6 +1307,8 @@ CONFIG_INPUT_POWERMATE=m CONFIG_INPUT_YEALINK=m CONFIG_INPUT_CM109=m CONFIG_INPUT_UINPUT=m +# CONFIG_INPUT_PCF50633_PMU is not set +# CONFIG_INPUT_PCF8574 is not set CONFIG_INPUT_GPIO_ROTARY_ENCODER=m # @@ -1146,6 +1319,7 @@ CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PARKBD is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set CONFIG_GAMEPORT=m # CONFIG_GAMEPORT_NS558 is not set # CONFIG_GAMEPORT_L4 is not set @@ -1167,10 +1341,9 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set -# CONFIG_SX is not set -# CONFIG_RIO is not set # CONFIG_STALDRV is not set # @@ -1195,6 +1368,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # Non-8250 serial port support # CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS_4=y CONFIG_SERIAL_SAMSUNG_UARTS=4 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set CONFIG_SERIAL_SAMSUNG_CONSOLE=y @@ -1204,6 +1378,9 @@ CONFIG_SERIAL_S3C2440=y # CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -1221,6 +1398,7 @@ CONFIG_HW_RANDOM=y CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y @@ -1232,10 +1410,12 @@ CONFIG_I2C_ALGOBIT=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set CONFIG_I2C_S3C2410=y CONFIG_I2C_SIMTEC=y +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -1252,20 +1432,9 @@ CONFIG_I2C_SIMTEC=y # CONFIG_I2C_PCA_ISA is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y @@ -1278,13 +1447,21 @@ CONFIG_SPI_BITBANG=m CONFIG_SPI_GPIO=m # CONFIG_SPI_LM70_LLP is not set CONFIG_SPI_S3C24XX=m +# CONFIG_SPI_S3C24XX_FIQ is not set CONFIG_SPI_S3C24XX_GPIO=m +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=m CONFIG_SPI_TLE62X0=m + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -1293,13 +1470,16 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -1310,10 +1490,29 @@ CONFIG_GPIOLIB=y # # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_CHARGER_PCF50633 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADCXX is not set @@ -1323,10 +1522,11 @@ CONFIG_HWMON_VID=m # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -1338,6 +1538,7 @@ CONFIG_HWMON_VID=m # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=m # CONFIG_SENSORS_LM77 is not set CONFIG_SENSORS_LM78=m @@ -1358,12 +1559,17 @@ CONFIG_SENSORS_LM85=m # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_S3C is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set @@ -1374,9 +1580,8 @@ CONFIG_SENSORS_LM85=m # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -1385,6 +1590,7 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_S3C2410_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set # # ISA-based Watchdog Cards @@ -1408,213 +1614,36 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set CONFIG_MFD_SM501=y # CONFIG_MFD_SM501_GPIO is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_UCB1400_CORE is not set -# CONFIG_TPS65010 is not set +CONFIG_TPS65010=m # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_VIVI=m -CONFIG_VIDEO_PMS=m -CONFIG_VIDEO_BWQCAM=m -CONFIG_VIDEO_CQCAM=m -CONFIG_VIDEO_W9966=m -CONFIG_VIDEO_CPIA=m -CONFIG_VIDEO_CPIA_PP=m -CONFIG_VIDEO_CPIA_USB=m -CONFIG_VIDEO_CPIA2=m -CONFIG_VIDEO_SAA5246A=m -CONFIG_VIDEO_SAA5249=m -CONFIG_VIDEO_AU0828=m -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -CONFIG_RADIO_ADAPTERS=y -CONFIG_RADIO_CADET=m -CONFIG_RADIO_RTRACK=m -CONFIG_RADIO_RTRACK2=m -CONFIG_RADIO_AZTECH=m -CONFIG_RADIO_GEMTEK=m -CONFIG_RADIO_SF16FMI=m -CONFIG_RADIO_SF16FMR2=m -CONFIG_RADIO_TERRATEC=m -CONFIG_RADIO_TRUST=m -CONFIG_RADIO_TYPHOON=m -CONFIG_RADIO_TYPHOON_PROC_FS=y -CONFIG_RADIO_ZOLTRIX=m -CONFIG_USB_DSBR=m -CONFIG_USB_SI470X=m -CONFIG_USB_MR800=m -CONFIG_RADIO_TEA5764=m -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -# CONFIG_DVB_USB_A800 is not set -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -# CONFIG_DVB_USB_GL861 is not set -# CONFIG_DVB_USB_AU6610 is not set -# CONFIG_DVB_USB_DIGITV is not set -# CONFIG_DVB_USB_VP7045 is not set -# CONFIG_DVB_USB_VP702X is not set -# CONFIG_DVB_USB_GP8PSK is not set -# CONFIG_DVB_USB_NOVA_T_USB2 is not set -# CONFIG_DVB_USB_TTUSB2 is not set -# CONFIG_DVB_USB_DTT200U is not set -# CONFIG_DVB_USB_OPERA1 is not set -CONFIG_DVB_USB_AF9005=m -# CONFIG_DVB_USB_AF9005_REMOTE is not set -# CONFIG_DVB_USB_DW2102 is not set -# CONFIG_DVB_USB_CINERGY_T2 is not set -# CONFIG_DVB_USB_ANYSEE is not set -# CONFIG_DVB_USB_DTV5100 is not set -# CONFIG_DVB_USB_AF9015 is not set -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_SIANO_SMS1XXX is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -# CONFIG_DVB_B2C2_FLEXCOP is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_AU8522=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m +# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_PCF50633=y +# CONFIG_MFD_MC13783 is not set +# CONFIG_PCF50633_ADC is not set +CONFIG_PCF50633_GPIO=y +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -1653,6 +1682,8 @@ CONFIG_FB_SM501=y # CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set # CONFIG_LCD_LTV350QV is not set # CONFIG_LCD_ILI9320 is not set # CONFIG_LCD_TDO24M is not set @@ -1682,6 +1713,7 @@ CONFIG_FONT_8x16=y # CONFIG_LOGO is not set CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -1701,36 +1733,44 @@ CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y # CONFIG_SND_DEBUG is not set CONFIG_SND_VMASTER=y +CONFIG_SND_RAWMIDI_SEQ=m +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set CONFIG_SND_AC97_CODEC=m # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set CONFIG_SND_USB_CAIAQ=m # CONFIG_SND_USB_CAIAQ_INPUT is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_S3C24XX_SOC=y -CONFIG_SND_S3C24XX_SOC_I2S=m +CONFIG_SND_S3C24XX_SOC_I2S=y CONFIG_SND_S3C_I2SV2_SOC=m CONFIG_SND_S3C2412_SOC_I2S=m -CONFIG_SND_S3C2443_SOC_AC97=m +CONFIG_SND_S3C_SOC_AC97=m +# CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753 is not set CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m -CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=m +CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y +# CONFIG_SND_S3C24XX_SOC_SIMTEC_TLV320AIC23 is not set +# CONFIG_SND_S3C24XX_SOC_SIMTEC_HERMES is not set CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_L3=m -CONFIG_SND_SOC_UDA134X=m +CONFIG_SND_SOC_L3=y +CONFIG_SND_SOC_UDA134X=y CONFIG_SND_SOC_WM8750=m # CONFIG_SOUND_PRIME is not set CONFIG_AC97_BUS=y CONFIG_HID_SUPPORT=y CONFIG_HID=y -# CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # @@ -1743,6 +1783,8 @@ CONFIG_HID=y # Special HID drivers # CONFIG_HID_APPLE=m +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_WACOM is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1757,8 +1799,6 @@ CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set @@ -1770,6 +1810,7 @@ CONFIG_USB_MON=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -1854,6 +1895,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y CONFIG_USB_SERIAL_NAVMAN=m CONFIG_USB_SERIAL_PL2303=y # CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set # CONFIG_USB_SERIAL_QUALCOMM is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set # CONFIG_USB_SERIAL_HP4X is not set @@ -1864,9 +1906,12 @@ CONFIG_USB_SERIAL_PL2303=y # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -1879,7 +1924,6 @@ CONFIG_USB_SEVSEG=m CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m CONFIG_USB_LED=m CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m @@ -1891,13 +1935,13 @@ CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m CONFIG_USB_TEST=m # CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set # CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set @@ -1915,10 +1959,15 @@ CONFIG_MMC_TEST=m # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=m +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_SDHCI_S3C is not set CONFIG_MMC_SPI=m CONFIG_MMC_S3C=y +# CONFIG_MMC_S3C_HW_SDIO_IRQ is not set +CONFIG_MMC_S3C_PIO=y +# CONFIG_MMC_S3C_DMA is not set +# CONFIG_MMC_S3C_PIODMA is not set # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m @@ -1930,26 +1979,28 @@ CONFIG_LEDS_H1940=m CONFIG_LEDS_PCA9532=m CONFIG_LEDS_GPIO=m CONFIG_LEDS_GPIO_PLATFORM=y -CONFIG_LEDS_LP5521=m +# CONFIG_LEDS_LP3944 is not set CONFIG_LEDS_PCA955X=m CONFIG_LEDS_DAC124S085=m CONFIG_LEDS_PWM=m CONFIG_LEDS_BD2802=m +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m # CONFIG_LEDS_TRIGGER_IDE_DISK is not set CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -1978,9 +2029,11 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1992,6 +2045,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set # # Platform RTC drivers @@ -2005,8 +2059,11 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_PCF50633 is not set # # on-CPU RTC drivers @@ -2014,7 +2071,6 @@ CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_S3C=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -2032,20 +2088,23 @@ CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set CONFIG_EXT4_FS=m -# CONFIG_EXT4DEV_COMPAT is not set CONFIG_EXT4_FS_XATTR=y CONFIG_EXT4_FS_POSIX_ACL=y # CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set CONFIG_JBD=y CONFIG_JBD2=m CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -2053,6 +2112,7 @@ CONFIG_INOTIFY_USER=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set CONFIG_GENERIC_ACL=y # @@ -2111,6 +2171,7 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y CONFIG_SQUASHFS=m # CONFIG_SQUASHFS_EMBEDDED is not set @@ -2127,7 +2188,6 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y CONFIG_ROMFS_ON_BLOCK=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -2149,6 +2209,7 @@ CONFIG_SUNRPC_GSS=m CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set @@ -2230,6 +2291,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -2246,6 +2308,7 @@ CONFIG_SCHED_DEBUG=y # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -2264,32 +2327,34 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -2297,7 +2362,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set CONFIG_DEBUG_S3C_UART=0 # @@ -2306,13 +2373,16 @@ CONFIG_DEBUG_S3C_UART=0 # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m CONFIG_CRYPTO_ALGAPI2=m CONFIG_CRYPTO_AEAD=m @@ -2355,11 +2425,13 @@ CONFIG_CRYPTO_ECB=m # CONFIG_CRYPTO_HMAC=m # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=m # CONFIG_CRYPTO_MICHAEL_MIC is not set @@ -2420,9 +2492,11 @@ CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m @@ -2430,3 +2504,4 @@ CONFIG_TEXTSEARCH_FSM=m CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 5e7d4c1b8fc1..2b642386f030 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -1,11 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc4 -# Tue Jan 19 13:12:40 2010 +# Linux kernel version: 2.6.34 +# Fri May 28 19:05:39 2010 # CONFIG_ARM=y +CONFIG_HAVE_PWM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -18,6 +22,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -32,6 +37,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set @@ -53,7 +59,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -89,10 +94,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -164,7 +173,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set # CONFIG_MUTEX_SPIN_ON_OWNER is not set -# CONFIG_FREEZER is not set +CONFIG_FREEZER=y # # System Type @@ -174,8 +183,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -184,7 +196,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -201,70 +212,89 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set CONFIG_ARCH_S3C64XX=y # CONFIG_ARCH_S5P6440 is not set -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_PLAT_SAMSUNG=y + +# +# Boot options +# +CONFIG_S3C_BOOT_ERROR_RESET=y +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_SAMSUNG_CLKSRC=y CONFIG_SAMSUNG_IRQ_VIC_TIMER=y CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIOLIB_4BIT=y CONFIG_S3C_GPIO_CFG_S3C24XX=y CONFIG_S3C_GPIO_CFG_S3C64XX=y CONFIG_S3C_GPIO_PULL_UPDOWN=y CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y # CONFIG_S3C_ADC is not set CONFIG_S3C_DEV_HSMMC=y CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_HSMMC2=y +CONFIG_S3C_DEV_HWMON=y CONFIG_S3C_DEV_I2C1=y CONFIG_S3C_DEV_FB=y CONFIG_S3C_DEV_USB_HOST=y CONFIG_S3C_DEV_USB_HSOTG=y +CONFIG_S3C_DEV_WDT=y CONFIG_S3C_DEV_NAND=y -CONFIG_PLAT_S3C64XX=y -CONFIG_CPU_S3C6400_INIT=y -CONFIG_CPU_S3C6400_CLOCK=y -# CONFIG_S3C64XX_DMA is not set -CONFIG_S3C64XX_SETUP_I2C0=y -CONFIG_S3C64XX_SETUP_I2C1=y -CONFIG_S3C64XX_SETUP_FB_24BPP=y -CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y -CONFIG_PLAT_S3C=y - -# -# Boot options -# -CONFIG_S3C_BOOT_ERROR_RESET=y -CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_DEV_RTC=y +CONFIG_SAMSUNG_DEV_ADC=y +CONFIG_SAMSUNG_DEV_TS=y +CONFIG_S3C_DMA=y # # Power management # -CONFIG_S3C_LOWLEVEL_UART_PORT=0 -CONFIG_S3C_GPIO_SPACE=0 -CONFIG_S3C_GPIO_TRACK=y -# CONFIG_MACH_SMDK6400 is not set +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_S3C_PM_DEBUG_LED_SMDK is not set +# CONFIG_SAMSUNG_PM_CHECK is not set +CONFIG_SAMSUNG_WAKEMASK=y +CONFIG_PLAT_S3C64XX=y +CONFIG_CPU_S3C6400=y CONFIG_CPU_S3C6410=y -CONFIG_S3C6410_SETUP_SDHCI=y -# CONFIG_MACH_ANW6410 is not set +CONFIG_S3C64XX_DMA=y +CONFIG_S3C64XX_SETUP_SDHCI=y +CONFIG_S3C64XX_SETUP_I2C0=y +CONFIG_S3C64XX_SETUP_I2C1=y +CONFIG_S3C64XX_SETUP_FB_24BPP=y +CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y +CONFIG_MACH_SMDK6400=y +CONFIG_MACH_ANW6410=y CONFIG_MACH_SMDK6410=y CONFIG_SMDK6410_SD_CH0=y # CONFIG_SMDK6410_SD_CH1 is not set # CONFIG_SMDK6410_WM1190_EV1 is not set -# CONFIG_MACH_NCP is not set -# CONFIG_MACH_HMT is not set +# CONFIG_SMDK6410_WM1192_EV1 is not set +CONFIG_MACH_NCP=y +CONFIG_MACH_HMT=y +CONFIG_MACH_SMARTQ=y +CONFIG_MACH_SMARTQ5=y +CONFIG_MACH_SMARTQ7=y # # Processor Type @@ -290,6 +320,8 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_411920 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 @@ -339,6 +371,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -371,7 +404,14 @@ CONFIG_HAVE_AOUT=y # # Power management options # -# CONFIG_PM is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_NET is not set @@ -392,7 +432,96 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_S3C2410=y +# CONFIG_MTD_NAND_S3C2410_DEBUG is not set +# CONFIG_MTD_NAND_S3C2410_HWECC is not set +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set @@ -402,6 +531,7 @@ CONFIG_BLK_DEV_LOOP=y # # DRBD disabled because PROC_FS, INET or CONNECTOR not selected # +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 @@ -413,13 +543,16 @@ CONFIG_MISC_DEVICES=y # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set # CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set # CONFIG_C2PORT is not set # # EEPROM support # CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set @@ -430,6 +563,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # CONFIG_SCSI_DMA is not set @@ -466,6 +600,7 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_MATRIX is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set @@ -527,12 +662,17 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # Non-8250 serial port support # CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS_4=y CONFIG_SERIAL_SAMSUNG_UARTS=4 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_S3C6400=y +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -561,28 +701,41 @@ CONFIG_I2C_HELPER_AUTO=y # CONFIG_I2C_OCORES is not set CONFIG_I2C_S3C2410=y # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_S3C64XX=m +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set # # PPS support @@ -596,10 +749,12 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set @@ -612,6 +767,9 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set # # AC97 GPIO expanders: @@ -627,16 +785,18 @@ CONFIG_HWMON=y # # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -647,6 +807,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set @@ -661,6 +822,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set @@ -672,6 +834,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set @@ -685,9 +848,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_HAVE_S3C2410_WATCHDOG=y CONFIG_SSB_POSSIBLE=y # @@ -699,10 +864,13 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_UCB1400_CORE is not set # CONFIG_TPS65010 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set @@ -711,12 +879,16 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set -# CONFIG_MFD_88PM8607 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB4500_CORE is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -725,8 +897,47 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S3C=y +# CONFIG_FB_S3C_DEBUG_REGWRITE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +CONFIG_LCD_LTV350QV=y +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y # # Display device support @@ -738,33 +949,246 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_SOUND is not set +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_S3C24XX_SOC=m +CONFIG_SND_S3C_SOC_AC97=m +# CONFIG_SND_S3C64XX_SOC_WM8580 is not set +CONFIG_SND_SOC_SMDK_WM9713=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM9713=m +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y # CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set # # Special HID drivers # +# CONFIG_HID_3M_PCT is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +# CONFIG_HID_CANDO is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_PRODIKEYS is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MOSART is not set +CONFIG_HID_MONTEREY=y +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set # -# Enable Host or Gadget support to see Inventra options +# USB Device Class drivers # +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y CONFIG_MMC_DEBUG=y CONFIG_MMC_UNSAFE_RESUME=y @@ -784,20 +1208,80 @@ CONFIG_MMC_SDHCI=y # CONFIG_MMC_SDHCI_PLTFM is not set CONFIG_MMC_SDHCI_S3C=y # CONFIG_MMC_SDHCI_S3C_DMA is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_SPI is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# TI VLYNQ +# on-CPU RTC drivers # +CONFIG_RTC_DRV_S3C=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # CONFIG_STAGING is not set # @@ -869,6 +1353,8 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -889,7 +1375,46 @@ CONFIG_ROMFS_ON_BLOCK=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set # # Kernel hacking @@ -952,6 +1477,7 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -962,6 +1488,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig index 279a15e53114..532e987beb4d 100644 --- a/arch/arm/configs/s5p6440_defconfig +++ b/arch/arm/configs/s5p6440_defconfig @@ -1,11 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc2 -# Sat Jan 9 16:33:55 2010 +# Linux kernel version: 2.6.34 +# Wed May 26 19:04:32 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -30,6 +34,13 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set @@ -46,7 +57,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -60,6 +70,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -81,10 +92,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -166,8 +181,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -176,7 +194,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -193,44 +210,56 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set CONFIG_ARCH_S5P6440=y -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_PLAT_SAMSUNG=y -CONFIG_SAMSUNG_CLKSRC=y -CONFIG_SAMSUNG_IRQ_VIC_TIMER=y -CONFIG_SAMSUNG_IRQ_UART=y -CONFIG_SAMSUNG_GPIO_EXTRA=0 -CONFIG_PLAT_S3C=y # # Boot options # CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIOLIB_4BIT=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +# CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_WDT=y +CONFIG_SAMSUNG_DEV_ADC=y +CONFIG_SAMSUNG_DEV_TS=y +CONFIG_S3C_PL330_DMA=y # # Power management # -CONFIG_S3C_LOWLEVEL_UART_PORT=1 -CONFIG_S3C_GPIO_SPACE=0 -CONFIG_S3C_GPIO_TRACK=y CONFIG_PLAT_S5P=y -CONFIG_CPU_S5P6440_INIT=y -CONFIG_CPU_S5P6440_CLOCK=y CONFIG_CPU_S5P6440=y CONFIG_MACH_SMDK6440=y @@ -258,9 +287,12 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_411920 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 +CONFIG_PL330=y # # Bus support @@ -307,6 +339,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -382,6 +415,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -470,7 +504,9 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set @@ -518,12 +554,16 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3 # Non-8250 serial port support # CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS_4=y CONFIG_SERIAL_SAMSUNG_UARTS=4 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_S5P6440=y +CONFIG_SERIAL_S3C6400=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -549,6 +589,7 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: @@ -570,6 +611,7 @@ CONFIG_GPIOLIB=y # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_HAVE_S3C2410_WATCHDOG=y CONFIG_SSB_POSSIBLE=y # @@ -626,10 +668,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -704,6 +742,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -826,6 +865,7 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -836,6 +876,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -962,8 +1003,10 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig index 74e20bfc0487..068219b360f5 100644 --- a/arch/arm/configs/s5p6442_defconfig +++ b/arch/arm/configs/s5p6442_defconfig @@ -1,11 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc4 -# Mon Jan 25 08:50:28 2010 +# Linux kernel version: 2.6.34 +# Wed May 26 19:04:34 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -31,6 +35,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set @@ -52,7 +57,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -88,10 +92,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -173,8 +181,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -183,7 +194,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -200,24 +210,35 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_S5P6440 is not set CONFIG_ARCH_S5P6442=y -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_PLAT_SAMSUNG=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_SAMSUNG_CLKSRC=y CONFIG_SAMSUNG_IRQ_VIC_TIMER=y CONFIG_SAMSUNG_IRQ_UART=y @@ -225,22 +246,16 @@ CONFIG_SAMSUNG_GPIOLIB_4BIT=y CONFIG_S3C_GPIO_CFG_S3C24XX=y CONFIG_S3C_GPIO_CFG_S3C64XX=y CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y # CONFIG_S3C_ADC is not set +CONFIG_S3C_PL330_DMA=y # # Power management # -CONFIG_PLAT_S3C=y - -# -# Boot options -# -# CONFIG_S3C_BOOT_ERROR_RESET is not set -CONFIG_S3C_BOOT_UART_FORCE_FIFO=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 -CONFIG_S3C_GPIO_SPACE=0 -CONFIG_S3C_GPIO_TRACK=y CONFIG_PLAT_S5P=y CONFIG_CPU_S5P6442=y CONFIG_MACH_SMDK6442=y @@ -269,9 +284,12 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_411920 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 +CONFIG_PL330=y # # Bus support @@ -318,6 +336,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -394,6 +413,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -462,6 +482,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set @@ -515,6 +536,9 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_S5PV210=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -540,6 +564,7 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: @@ -613,10 +638,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -685,6 +706,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -824,6 +846,7 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -834,6 +857,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig index dc108afc060c..ebc6245b9fca 100644 --- a/arch/arm/configs/s5pc100_defconfig +++ b/arch/arm/configs/s5pc100_defconfig @@ -1,12 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30 -# Wed Jul 1 15:53:07 2009 +# Linux kernel version: 2.6.34 +# Wed May 26 19:04:35 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y -CONFIG_MMU=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -18,7 +20,9 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y @@ -31,6 +35,13 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set @@ -38,14 +49,15 @@ CONFIG_SWAP=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -59,6 +71,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -80,19 +93,21 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # -# Performance Counters +# Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y @@ -122,25 +137,56 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -156,6 +202,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -164,39 +211,64 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set -CONFIG_ARCH_S5PC1XX=y +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +CONFIG_ARCH_S5PC100=y +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -CONFIG_PLAT_S3C=y +# CONFIG_PLAT_SPEAR is not set +CONFIG_PLAT_SAMSUNG=y # # Boot options # # CONFIG_S3C_BOOT_ERROR_RESET is not set CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIOLIB_4BIT=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +# CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_HSMMC2=y +CONFIG_S3C_DEV_I2C1=y +CONFIG_S3C_DEV_FB=y +CONFIG_S3C_PL330_DMA=y # # Power management # -CONFIG_S3C_LOWLEVEL_UART_PORT=0 -CONFIG_S3C_GPIO_SPACE=0 -CONFIG_S3C_GPIO_TRACK=y -CONFIG_S3C_GPIO_PULL_UPDOWN=y -CONFIG_PLAT_S5PC1XX=y -CONFIG_CPU_S5PC100_INIT=y -CONFIG_CPU_S5PC100_CLOCK=y -CONFIG_S5PC100_SETUP_I2C0=y +CONFIG_PLAT_S5P=y +CONFIG_S5P_EXT_INT=y CONFIG_CPU_S5PC100=y +CONFIG_S5PC100_SETUP_FB_24BPP=y +CONFIG_S5PC100_SETUP_I2C1=y +CONFIG_S5PC100_SETUP_SDHCI=y +CONFIG_S5PC100_SETUP_SDHCI_GPIO=y CONFIG_MACH_SMDKC100=y # @@ -206,7 +278,7 @@ CONFIG_CPU_32v6K=y CONFIG_CPU_V7=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_PABRT_V7=y CONFIG_CPU_CACHE_V7=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y @@ -224,11 +296,15 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 +CONFIG_PL330=y # # Bus support @@ -244,8 +320,11 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set CONFIG_AEABI=y CONFIG_OABI_COMPAT=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set @@ -258,12 +337,11 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set @@ -274,6 +352,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -317,6 +396,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -331,6 +411,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 @@ -338,9 +422,12 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # @@ -350,18 +437,21 @@ CONFIG_EEPROM_AT24=y # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set +# CONFIG_PHONE is not set # # Input device support @@ -369,6 +459,7 @@ CONFIG_HAVE_IDE=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -385,13 +476,19 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -399,6 +496,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set @@ -418,6 +516,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -444,11 +543,16 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # Non-8250 serial port support # CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_UARTS=3 +CONFIG_SERIAL_SAMSUNG_UARTS_4=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 # CONFIG_SERIAL_SAMSUNG_DEBUG is not set CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C6400=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -461,6 +565,7 @@ CONFIG_HW_RANDOM=y # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_HELPER_AUTO=y @@ -471,9 +576,11 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set # # External I2C/SMBus adapter drivers @@ -486,20 +593,15 @@ CONFIG_I2C_HELPER_AUTO=y # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -508,13 +610,16 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -523,10 +628,19 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set @@ -535,10 +649,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -549,6 +664,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -573,8 +689,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set @@ -584,9 +702,8 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -599,10 +716,12 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set # CONFIG_TPS65010 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set @@ -610,10 +729,15 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set +# CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set # @@ -637,7 +761,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -CONFIG_HID_DEBUG=y # CONFIG_HIDRAW is not set # CONFIG_HID_PID is not set @@ -680,13 +803,12 @@ CONFIG_SDIO_UART=y CONFIG_MMC_SDHCI=y # CONFIG_MMC_SDHCI_PLTFM is not set # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -710,6 +832,7 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y @@ -758,6 +881,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -772,7 +896,6 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y CONFIG_ROMFS_ON_BLOCK=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set # # Partition Types @@ -789,6 +912,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -826,11 +950,13 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y @@ -839,6 +965,7 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -849,6 +976,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -857,8 +985,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set -CONFIG_DEBUG_S3C_PORT=y +# CONFIG_OC_ETM is not set CONFIG_DEBUG_S3C_UART=0 # @@ -867,7 +996,11 @@ CONFIG_DEBUG_S3C_UART=0 # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" # CONFIG_CRYPTO is not set # CONFIG_BINARY_PRINTF is not set @@ -884,8 +1017,10 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig index 6ea636131ac8..c4de360b0f69 100644 --- a/arch/arm/configs/s5pc110_defconfig +++ b/arch/arm/configs/s5pc110_defconfig @@ -1,11 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc4 -# Wed Feb 24 15:36:54 2010 +# Linux kernel version: 2.6.34 +# Wed May 26 19:04:37 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_VECTORS_BASE=0xffff0000 @@ -33,6 +37,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set @@ -54,7 +59,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -90,10 +94,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -175,8 +183,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -185,7 +196,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -202,24 +212,27 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_S5P6440 is not set # CONFIG_ARCH_S5P6442 is not set -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PC100 is not set CONFIG_ARCH_S5PV210=y # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_PLAT_SAMSUNG=y # @@ -235,16 +248,22 @@ CONFIG_SAMSUNG_GPIOLIB_4BIT=y CONFIG_S3C_GPIO_CFG_S3C24XX=y CONFIG_S3C_GPIO_CFG_S3C64XX=y CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y CONFIG_SAMSUNG_GPIO_EXTRA=0 CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_GPIO_TRACK=y # CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_WDT=y +CONFIG_S3C_PL330_DMA=y # # Power management # CONFIG_PLAT_S5P=y +CONFIG_S5P_EXT_INT=y CONFIG_CPU_S5PV210=y +# CONFIG_MACH_AQUILA is not set +# CONFIG_MACH_GONI is not set # CONFIG_MACH_SMDKV210 is not set CONFIG_MACH_SMDKC110=y @@ -274,11 +293,14 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 +CONFIG_PL330=y # # Bus support @@ -327,6 +349,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -404,6 +427,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -472,6 +496,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set @@ -526,6 +551,9 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_S5PV210=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -551,6 +579,7 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: @@ -572,6 +601,7 @@ CONFIG_GPIOLIB=y # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_HAVE_S3C2410_WATCHDOG=y CONFIG_SSB_POSSIBLE=y # @@ -624,10 +654,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -696,6 +722,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -835,6 +862,8 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -845,6 +874,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 3f7d47491b54..e2f5bce29828 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -1,11 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.33-rc4 -# Wed Feb 24 15:36:16 2010 +# Linux kernel version: 2.6.34 +# Wed May 26 19:04:39 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y @@ -17,6 +20,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_VECTORS_BASE=0xffff0000 @@ -33,6 +37,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set @@ -54,7 +59,6 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -90,10 +94,14 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y # # Kernel Performance Events And Counters # +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -175,8 +183,11 @@ CONFIG_MMU=y # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set # CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -185,7 +196,6 @@ CONFIG_MMU=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -202,24 +212,27 @@ CONFIG_MMU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_S5P6440 is not set # CONFIG_ARCH_S5P6442 is not set -# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PC100 is not set CONFIG_ARCH_S5PV210=y # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set +# CONFIG_PLAT_SPEAR is not set CONFIG_PLAT_SAMSUNG=y # @@ -235,16 +248,24 @@ CONFIG_SAMSUNG_GPIOLIB_4BIT=y CONFIG_S3C_GPIO_CFG_S3C24XX=y CONFIG_S3C_GPIO_CFG_S3C64XX=y CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y CONFIG_SAMSUNG_GPIO_EXTRA=0 CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_GPIO_TRACK=y # CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_WDT=y +CONFIG_SAMSUNG_DEV_ADC=y +CONFIG_SAMSUNG_DEV_TS=y +CONFIG_S3C_PL330_DMA=y # # Power management # CONFIG_PLAT_S5P=y +CONFIG_S5P_EXT_INT=y CONFIG_CPU_S5PV210=y +# CONFIG_MACH_AQUILA is not set +# CONFIG_MACH_GONI is not set CONFIG_MACH_SMDKV210=y # CONFIG_MACH_SMDKC110 is not set @@ -274,11 +295,14 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 +CONFIG_PL330=y # # Bus support @@ -327,6 +351,7 @@ CONFIG_ALIGNMENT_TRAP=y CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_CMDLINE_FORCE is not set # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -404,6 +429,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -472,7 +498,9 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set @@ -526,6 +554,9 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_S5PV210=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -551,6 +582,7 @@ CONFIG_GPIOLIB=y # # Memory mapped GPIO expanders: # +# CONFIG_GPIO_IT8761E is not set # # I2C GPIO expanders: @@ -572,6 +604,7 @@ CONFIG_GPIOLIB=y # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_HAVE_S3C2410_WATCHDOG=y CONFIG_SSB_POSSIBLE=y # @@ -624,10 +657,6 @@ CONFIG_RTC_LIB=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -696,6 +725,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -835,6 +865,8 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set @@ -845,6 +877,7 @@ CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 182310b99195..6d7485aff955 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -12,7 +12,9 @@ typedef struct { #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ -#if NR_IRQS > 256 +#if NR_IRQS > 512 +#define HARDIRQ_BITS 10 +#elif NR_IRQS > 256 #define HARDIRQ_BITS 9 #else #define HARDIRQ_BITS 8 diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h index bcda59f39941..2f87870d9347 100644 --- a/arch/arm/include/asm/scatterlist.h +++ b/arch/arm/include/asm/scatterlist.h @@ -3,9 +3,6 @@ #include <asm/memory.h> #include <asm/types.h> - #include <asm-generic/scatterlist.h> -#undef ARCH_HAS_SG_CHAIN - #endif /* _ASMARM_SCATTERLIST_H */ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c91c77b54dea..122d999bdc7c 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -593,6 +593,7 @@ static int __init parse_tag_revision(const struct tag *tag) __tagtable(ATAG_REVISION, parse_tag_revision); +#ifndef CONFIG_CMDLINE_FORCE static int __init parse_tag_cmdline(const struct tag *tag) { strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); @@ -600,6 +601,7 @@ static int __init parse_tag_cmdline(const struct tag *tag) } __tagtable(ATAG_CMDLINE, parse_tag_cmdline); +#endif /* CONFIG_CMDLINE_FORCE */ /* * Scan the tag table for this tag, and call its parse function. diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 50292cd9c120..dd81a918c106 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -26,6 +26,7 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html */ +#ifndef __CHECKER__ #if !defined (__ARM_EABI__) #warning Your compiler does not have EABI support. #warning ARM unwind is known to compile only with EABI compilers. @@ -34,6 +35,7 @@ #warning Your compiler is too buggy; it is known to not compile ARM unwind support. #warning Change compiler or disable ARM_UNWIND option. #endif +#endif /* __CHECKER__ */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 98f9f4bc9396..ee800595594d 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -25,7 +25,6 @@ #include <linux/leds.h> #include <linux/clk.h> -#include <mach/hardware.h> #include <video/atmel_lcdc.h> #include <asm/setup.h> diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot index d3d29339e149..a51fcef64fe0 100644 --- a/arch/arm/mach-clps711x/Makefile.boot +++ b/arch/arm/mach-clps711x/Makefile.boot @@ -1,7 +1,6 @@ # The standard locations for stuff on CLPS711x type processors - zreladdr-y := 0xc0028000 + zreladdr-y := 0xc0028000 params_phys-y := 0xc0000100 # Should probably have some agreement on these... initrd_phys-$(CONFIG_ARCH_P720T) := 0xc0400000 initrd_phys-$(CONFIG_ARCH_CDB89712) := 0x00700000 - diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index abd04932917b..2ec3095ffb7b 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -17,6 +17,7 @@ #include <linux/i2c.h> #include <linux/i2c/at24.h> #include <linux/i2c/pca953x.h> +#include <linux/mfd/tps6507x.h> #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> @@ -24,6 +25,8 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/regulator/machine.h> +#include <linux/mfd/tps6507x.h> +#include <linux/input/tps6507x-ts.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -533,10 +536,24 @@ struct regulator_init_data tps65070_regulator_data[] = { }, }; +static struct touchscreen_init_data tps6507x_touchscreen_data = { + .poll_period = 30, /* ms between touch samples */ + .min_pressure = 0x30, /* minimum pressure to trigger touch */ + .vref = 0, /* turn off vref when not using A/D */ + .vendor = 0, /* /sys/class/input/input?/id/vendor */ + .product = 65070, /* /sys/class/input/input?/id/product */ + .version = 0x100, /* /sys/class/input/input?/id/version */ +}; + +static struct tps6507x_board tps_board = { + .tps6507x_pmic_init_data = &tps65070_regulator_data[0], + .tps6507x_ts_init_data = &tps6507x_touchscreen_data, +}; + static struct i2c_board_info __initdata da850evm_tps65070_info[] = { { I2C_BOARD_INFO("tps6507x", 0x48), - .platform_data = &tps65070_regulator_data[0], + .platform_data = &tps_board, }, }; diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h index 5a85e24f3673..d4f1e9675069 100644 --- a/arch/arm/mach-davinci/include/mach/mmc.h +++ b/arch/arm/mach-davinci/include/mach/mmc.h @@ -22,6 +22,9 @@ struct davinci_mmc_config { /* Version of the MMC/SD controller */ u8 version; + + /* Number of sg segments */ + u8 nr_sg; }; void davinci_setup_mmc(int module, struct davinci_mmc_config *config); diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h new file mode 100644 index 000000000000..0a37961b3453 --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h @@ -0,0 +1,27 @@ +#ifndef __ASM_MACH_EP93XX_SPI_H +#define __ASM_MACH_EP93XX_SPI_H + +struct spi_device; + +/** + * struct ep93xx_spi_info - EP93xx specific SPI descriptor + * @num_chipselect: number of chip selects on this board, must be + * at least one + */ +struct ep93xx_spi_info { + int num_chipselect; +}; + +/** + * struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device + * @setup: setup the chip select mechanism + * @cleanup: cleanup the chip select mechanism + * @cs_control: control the device chip select + */ +struct ep93xx_spi_chip_ops { + int (*setup)(struct spi_device *spi); + void (*cleanup)(struct spi_device *spi); + void (*cs_control)(struct spi_device *spi, int value); +}; + +#endif /* __ASM_MACH_EP93XX_SPI_H */ diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c index 720c0bac1702..e5ab5bddbc8c 100644 --- a/arch/arm/mach-footbridge/ebsa285-pci.c +++ b/arch/arm/mach-footbridge/ebsa285-pci.c @@ -20,9 +20,9 @@ static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (dev->vendor == PCI_VENDOR_ID_CONTAQ && dev->device == PCI_DEVICE_ID_CONTAQ_82C693) switch (PCI_FUNC(dev->devfn)) { - case 1: return 14; - case 2: return 15; - case 3: return 12; + case 1: return 14; + case 2: return 15; + case 3: return 12; } return irqmap_ebsa285[(slot + pin) & 3]; diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h index d8798dbc44f8..7dd5fa604efc 100644 --- a/arch/arm/mach-h720x/common.h +++ b/arch/arm/mach-h720x/common.h @@ -14,13 +14,13 @@ */ extern unsigned long h720x_gettimeoffset(void); -extern void __init h720x_init_irq (void); +extern void __init h720x_init_irq(void); extern void __init h720x_map_io(void); #ifdef CONFIG_ARCH_H7202 extern struct sys_timer h7202_timer; extern void __init init_hw_h7202(void); -extern void __init h7202_init_irq (void); +extern void __init h7202_init_irq(void); extern void __init h7202_init_time(void); #endif diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index cccb9f3c9d01..db9381b85bf0 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -20,7 +20,6 @@ #include <linux/input.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/bootmem.h> #include <linux/power_supply.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index bac1f3c38a3b..e32981928c77 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -20,7 +20,6 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/delay.h> -#include <linux/bootmem.h> #include <linux/io.h> #include <linux/smsc911x.h> diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index ec4606643d2c..e3cc80792d6c 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -19,7 +19,6 @@ #include <linux/irq.h> #include <linux/gpio.h> #include <linux/platform_device.h> -#include <linux/bootmem.h> #include <linux/delay.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index 3d725ae518e4..02cae5e2951c 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c @@ -17,6 +17,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/interrupt.h> +#include <linux/completion.h> #include <mach/dma.h> #define MSM_DMOV_CHANNEL_COUNT 16 @@ -69,6 +70,8 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id)); } #endif + if (cmd->execute_func) + cmd->execute_func(cmd); PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status); list_add_tail(&cmd->list, &active_commands[id]); if (!channel_active) @@ -116,6 +119,7 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) cmd.dmov_cmd.cmdptr = cmdptr; cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func; + cmd.dmov_cmd.execute_func = NULL; cmd.id = id; init_completion(&cmd.complete); @@ -221,6 +225,8 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); list_del(&cmd->list); list_add_tail(&cmd->list, &active_commands[id]); + if (cmd->execute_func) + cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); writel(cmd->cmdptr, DMOV_CMD_PTR(id)); } diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h index 04c51cc04f31..00f9bbfadbe6 100644 --- a/arch/arm/mach-msm/include/mach/dma.h +++ b/arch/arm/mach-msm/include/mach/dma.h @@ -28,6 +28,8 @@ struct msm_dmov_cmd { void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result, struct msm_dmov_errdata *err); + void (*execute_func)(struct msm_dmov_cmd *cmd); + void *data; }; void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index b91e412f7b3e..a0aeb8a4adc1 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -109,12 +109,7 @@ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); #endif -/* - * Watchdog: - * - i.MX1 - * - i.MX21 - * - i.MX27 - */ +/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ static struct resource mxc_wdt_resources[] = { { .start = MX2x_WDOG_BASE_ADDR, @@ -124,7 +119,7 @@ static struct resource mxc_wdt_resources[] = { }; struct platform_device mxc_wdt = { - .name = "mxc_wdt", + .name = "imx2-wdt", .id = 0, .num_resources = ARRAY_SIZE(mxc_wdt_resources), .resource = mxc_wdt_resources, @@ -483,8 +478,8 @@ int __init mxc_register_gpios(void) #ifdef CONFIG_MACH_MX21 static struct resource mx21_usbhc_resources[] = { { - .start = MX21_BASE_ADDR, - .end = MX21_BASE_ADDR + 0x1FFF, + .start = MX21_USBOTG_BASE_ADDR, + .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, .flags = IORESOURCE_MEM, }, { diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index 778fff230918..a87422ed4ff5 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -145,6 +145,7 @@ static struct mxc_nand_platform_data pca100_nand_board_info = { static struct platform_device *platform_devices[] __initdata = { &mxc_w1_master_device, &mxc_fec_device, + &mxc_wdt, }; static struct imxi2c_platform_data pca100_i2c_1_data = { diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 035fbe046ec0..36c89431679a 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -182,6 +182,7 @@ static struct platform_device *platform_devices[] __initdata = { &mxc_w1_master_device, &mxc_fec_device, &pcm038_sram_mtd_device, + &mxc_wdt, }; /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3f4b8a0b5fac..3a405fa400eb 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -500,3 +500,18 @@ struct platform_device mx25_fb_device = { .coherent_dma_mask = 0xFFFFFFFF, }, }; + +static struct resource mxc_wdt_resources[] = { + { + .start = MX25_WDOG_BASE_ADDR, + .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_wdt = { + .name = "imx2-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_wdt_resources), + .resource = mxc_wdt_resources, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index 39560e13bc0d..cee12c0a0be6 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -21,3 +21,4 @@ extern struct platform_device mx25_fec_device; extern struct platform_device mxc_nand_device; extern struct platform_device mx25_rtc_device; extern struct platform_device mx25_fb_device; +extern struct platform_device mxc_wdt; diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 170f68e46dd5..344753fdf25e 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -82,6 +82,7 @@ config MACH_MX31MOBOARD config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" select ARCH_MX31 + select MXC_ULPI if USB_ULPI help Include support for mx31 based LILLY1131 modules. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index f8911154a9fa..db7acd6e9101 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -582,12 +582,50 @@ static struct resource imx_wdt_resources[] = { }; struct platform_device imx_wdt_device0 = { - .name = "imx-wdt", + .name = "imx2-wdt", .id = 0, .num_resources = ARRAY_SIZE(imx_wdt_resources), .resource = imx_wdt_resources, }; +static struct resource imx_rtc_resources[] = { + { + .start = MX31_RTC_BASE_ADDR, + .end = MX31_RTC_BASE_ADDR + 0x3fff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX31_INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_rtc_device0 = { + .name = "mxc_rtc", + .id = -1, + .num_resources = ARRAY_SIZE(imx_rtc_resources), + .resource = imx_rtc_resources, +}; + +static struct resource imx_kpp_resources[] = { + { + .start = MX3x_KPP_BASE_ADDR, + .end = MX3x_KPP_BASE_ADDR + 0xf, + .flags = IORESOURCE_MEM + }, { + .start = MX3x_INT_KPP, + .end = MX3x_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_kpp_device = { + .name = "imx-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(imx_kpp_resources), + .resource = imx_kpp_resources, +}; + static int __init mx3_devices_init(void) { if (cpu_is_mx31()) { diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 4f77eb501274..2c3c8646a29e 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -27,3 +27,5 @@ extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device imx_ssi_device1; extern struct platform_device imx_wdt_device0; +extern struct platform_device imx_rtc_device0; +extern struct platform_device imx_kpp_device; diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index f54af1e29ca4..58e57291b79d 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/delay.h> #include <linux/types.h> #include <linux/init.h> #include <linux/clk.h> @@ -26,6 +27,8 @@ #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> #include <linux/regulator/machine.h> +#include <linux/fsl_devices.h> +#include <linux/input/matrix_keypad.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -65,6 +68,50 @@ static int mx31_3ds_pins[] = { MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ /* MC13783 IRQ */ IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), + /* USB OTG reset */ + IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), + /* USB OTG */ + MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, + MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, + MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, + MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, + MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, + MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, + MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, + MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, + MX31_PIN_USBOTG_CLK__USBOTG_CLK, + MX31_PIN_USBOTG_DIR__USBOTG_DIR, + MX31_PIN_USBOTG_NXT__USBOTG_NXT, + MX31_PIN_USBOTG_STP__USBOTG_STP, + /*Keyboard*/ + MX31_PIN_KEY_ROW0_KEY_ROW0, + MX31_PIN_KEY_ROW1_KEY_ROW1, + MX31_PIN_KEY_ROW2_KEY_ROW2, + MX31_PIN_KEY_COL0_KEY_COL0, + MX31_PIN_KEY_COL1_KEY_COL1, + MX31_PIN_KEY_COL2_KEY_COL2, + MX31_PIN_KEY_COL3_KEY_COL3, +}; + +/* + * Matrix keyboard + */ + +static const uint32_t mx31_3ds_keymap[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_DOWN), + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_ENTER), + KEY(2, 0, KEY_F6), + KEY(2, 1, KEY_F8), + KEY(2, 2, KEY_F9), + KEY(2, 3, KEY_F10), +}; + +static struct matrix_keymap_data mx31_3ds_keymap_data = { + .keymap = mx31_3ds_keymap, + .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), }; /* Regulators */ @@ -126,6 +173,41 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { #endif }; +/* + * USB OTG + */ + +#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) + +static void mx31_3ds_usbotg_init(void) +{ + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); + + gpio_request(USBOTG_RST_B, "otgusb-reset"); + gpio_direction_output(USBOTG_RST_B, 0); + mdelay(1); + gpio_set_value(USBOTG_RST_B, 1); +} + +static struct fsl_usb2_platform_data usbotg_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -315,6 +397,11 @@ static void __init mxc_board_init(void) spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); + mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); + + mx31_3ds_usbotg_init(); + mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); + if (!mx31_3ds_init_expio()) platform_device_register(&smsc911x_device); } diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 80847b04c063..d3d5877c750e 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -27,12 +27,15 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/clk.h> +#include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/smsc911x.h> #include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/mfd/mc13783.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -44,6 +47,8 @@ #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> #include <mach/spi.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> #include "devices.h" @@ -108,6 +113,137 @@ static struct platform_device physmap_flash_device = { .num_resources = 1, }; +/* USB */ + +#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +static int usbotg_init(struct platform_device *pdev) +{ + unsigned int pins[] = { + MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, + MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, + MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, + MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, + MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, + MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, + MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, + MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, + MX31_PIN_USBOTG_CLK__USBOTG_CLK, + MX31_PIN_USBOTG_DIR__USBOTG_DIR, + MX31_PIN_USBOTG_NXT__USBOTG_NXT, + MX31_PIN_USBOTG_STP__USBOTG_STP, + }; + + mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG"); + + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); + + mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true); + mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true); + + /* chip select */ + mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO), + "USBOTG_CS"); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS"); + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0); + + return 0; +} + +static int usbh1_init(struct platform_device *pdev) +{ + int pins[] = { + MX31_PIN_CSPI1_MOSI__USBH1_RXDM, + MX31_PIN_CSPI1_MISO__USBH1_RXDP, + MX31_PIN_CSPI1_SS0__USBH1_TXDM, + MX31_PIN_CSPI1_SS1__USBH1_TXDP, + MX31_PIN_CSPI1_SS2__USBH1_RCV, + MX31_PIN_CSPI1_SCLK__USBH1_OEB, + MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, + }; + + mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); + + mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); + + return 0; +} + +static int usbh2_init(struct platform_device *pdev) +{ + int pins[] = { + MX31_PIN_USBH2_DATA0__USBH2_DATA0, + MX31_PIN_USBH2_DATA1__USBH2_DATA1, + MX31_PIN_USBH2_CLK__USBH2_CLK, + MX31_PIN_USBH2_DIR__USBH2_DIR, + MX31_PIN_USBH2_NXT__USBH2_NXT, + MX31_PIN_USBH2_STP__USBH2_STP, + }; + + mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); + + mxc_iomux_set_gpr(MUX_PGP_UH2, true); + + /* chip select */ + mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), + "USBH2_CS"); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); + + return 0; +} + +static struct mxc_usbh_platform_data usbotg_pdata = { + .init = usbotg_init, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static struct mxc_usbh_platform_data usbh1_pdata = { + .init = usbh1_init, + .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, + .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .init = usbh2_init, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + static struct platform_device *devices[] __initdata = { &smsc91x_device, &physmap_flash_device, @@ -183,6 +319,15 @@ static void __init mx31lilly_board_init(void) spi_register_board_info(&mc13783_dev, 1); platform_add_devices(devices, ARRAY_SIZE(devices)); + + /* USB */ + usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh1, &usbh1_pdata); + mxc_register_device(&mxc_usbh2, &usbh2_pdata); } static void __init mx31lilly_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index fccb9207b78d..62b5e40165df 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -18,7 +18,6 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> -#include <linux/fsl_devices.h> #include <linux/gfp.h> #include <linux/gpio.h> #include <linux/init.h> @@ -221,11 +220,54 @@ static struct mc13783_regulator_init_data moboard_regulators[] = { }, }; +static struct mc13783_led_platform_data moboard_led[] = { + { + .id = MC13783_LED_R1, + .name = "coreboard-led-4:red", + .max_current = 2, + }, + { + .id = MC13783_LED_G1, + .name = "coreboard-led-4:green", + .max_current = 2, + }, + { + .id = MC13783_LED_B1, + .name = "coreboard-led-4:blue", + .max_current = 2, + }, + { + .id = MC13783_LED_R2, + .name = "coreboard-led-5:red", + .max_current = 3, + }, + { + .id = MC13783_LED_G2, + .name = "coreboard-led-5:green", + .max_current = 3, + }, + { + .id = MC13783_LED_B2, + .name = "coreboard-led-5:blue", + .max_current = 3, + }, +}; + +static struct mc13783_leds_platform_data moboard_leds = { + .num_leds = ARRAY_SIZE(moboard_led), + .led = moboard_led, + .flags = MC13783_LED_SLEWLIMTC, + .abmode = MC13783_LED_AB_DISABLED, + .tc1_period = MC13783_LED_PERIOD_10MS, + .tc2_period = MC13783_LED_PERIOD_10MS, +}; + static struct mc13783_platform_data moboard_pmic = { .regulators = moboard_regulators, .num_regulators = ARRAY_SIZE(moboard_regulators), + .leds = &moboard_leds, .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC | - MC13783_USE_ADC, + MC13783_USE_ADC | MC13783_USE_LED, }; static struct spi_board_info moboard_spi_board_info[] __initdata = { @@ -306,84 +348,56 @@ static struct imxmmc_platform_data sdhc1_pdata = { * this pin is dedicated for all mx31moboard systems, so we do it here */ #define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) - -static void usb_xcvr_reset(void) -{ - gpio_request(USB_RESET_B, "usb-reset"); - gpio_direction_output(USB_RESET_B, 0); - mdelay(1); - gpio_set_value(USB_RESET_B, 1); -} - #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + PAD_CTL_ODE_CMOS) #define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) - -static void moboard_usbotg_init(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); -} - -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -#if defined(CONFIG_USB_ULPI) - #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) -static int moboard_usbh2_hw_init(struct platform_device *pdev) +static void usb_xcvr_reset(void) { - int ret; + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); mxc_iomux_set_gpr(MUX_PGP_UH2, true); + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - ret = gpio_request(USBH2_EN_B, "usbh2-en"); - if (ret) - return ret; + gpio_request(OTG_EN_B, "usb-udc-en"); + gpio_direction_output(OTG_EN_B, 0); + gpio_request(USBH2_EN_B, "usbh2-en"); gpio_direction_output(USBH2_EN_B, 0); - return 0; + gpio_request(USB_RESET_B, "usb-reset"); + gpio_direction_output(USB_RESET_B, 0); + mdelay(1); + gpio_set_value(USB_RESET_B, 1); + mdelay(1); } -static int moboard_usbh2_hw_exit(struct platform_device *pdev) -{ - gpio_free(USBH2_EN_B); - return 0; -} +#if defined(CONFIG_USB_ULPI) static struct mxc_usbh_platform_data usbh2_pdata = { - .init = moboard_usbh2_hw_init, - .exit = moboard_usbh2_hw_exit, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, }; @@ -508,8 +522,6 @@ static void __init mxc_board_init(void) usb_xcvr_reset(); - moboard_usbotg_init(); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); moboard_usbh2_init(); switch (mx31moboard_baseboard) { @@ -522,7 +534,8 @@ static void __init mxc_board_init(void) mx31moboard_marxbot_init(); break; case MX31SMARTBOT: - mx31moboard_smartbot_init(); + case MX31EYEBOT: + mx31moboard_smartbot_init(mx31moboard_baseboard); break; default: printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 78ecd751549b..cce410662383 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -449,6 +449,7 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size) static struct platform_device *devices[] __initdata = { &pcm037_flash, &pcm037_sram_device, + &imx_wdt_device0, &pcm037_mt9t031, &pcm037_mt9v022, }; diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 1bf1ec2eef5e..78d9185a9d4b 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -150,6 +150,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = { static struct platform_device *devices[] __initdata = { &pcm043_flash, &mxc_fec_device, + &imx_wdt_device0, }; static struct pad_desc pcm043_pads[] = { diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 093c595ca581..5f05bfbec380 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -206,5 +206,6 @@ void __init mx31lite_db_init(void) mxc_register_device(&mxc_spi_device0, &spi0_pdata); platform_device_register(&litekit_led_device); mxc_register_device(&imx_wdt_device0, NULL); + mxc_register_device(&imx_rtc_device0, NULL); } diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 11b906ce7eae..582299cb2c08 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -22,6 +22,7 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/types.h> +#include <linux/fsl_devices.h> #include <linux/usb/otg.h> @@ -213,6 +214,12 @@ static int __init devboard_usbh1_init(void) return mxc_register_device(&mxc_usbh1, &usbh1_pdata); } + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + /* * system init for baseboard usage. Will be called by mx31moboard init. */ @@ -229,5 +236,7 @@ void __init mx31moboard_devboard_init(void) devboard_init_sel_gpios(); + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index ffb105e14d88..4930f8c27e66 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -25,6 +25,7 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/types.h> +#include <linux/fsl_devices.h> #include <linux/usb/otg.h> @@ -329,6 +330,11 @@ static int __init marxbot_usbh1_init(void) return mxc_register_device(&mxc_usbh1, &usbh1_pdata); } +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + /* * system init for baseboard usage. Will be called by mx31moboard init. */ @@ -356,5 +362,7 @@ void __init mx31moboard_marxbot_init(void) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + marxbot_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 52a69fc8b14f..293eea6d9d97 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -23,11 +23,18 @@ #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/types.h> +#include <linux/fsl_devices.h> + +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> +#include <mach/board-mx31moboard.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> #include <media/soc_camera.h> @@ -116,10 +123,33 @@ static int __init smartbot_cam_init(void) return 0; } +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +#if defined(CONFIG_USB_ULPI) + +static struct mxc_usbh_platform_data otg_host_pdata = { + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static int __init smartbot_otg_host_init(void) +{ + otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + return mxc_register_device(&mxc_otg_host, &otg_host_pdata); +} +#else +static inline int smartbot_otg_host_init(void) { return 0; } +#endif + #define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) #define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) #define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) +#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) static void smartbot_resets_init(void) { @@ -138,15 +168,15 @@ static void smartbot_resets_init(void) gpio_export(TRSLAT_RST_B, false); } - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); + if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) { + gpio_direction_output(TRSLAT_SRC_CHOICE, 0); + gpio_export(TRSLAT_SRC_CHOICE, false); } } /* * system init for baseboard usage. Will be called by mx31moboard init. */ -void __init mx31moboard_smartbot_init(void) +void __init mx31moboard_smartbot_init(int board) { printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); @@ -155,6 +185,19 @@ void __init mx31moboard_smartbot_init(void) mxc_register_device(&mxc_uart_device1, &uart_pdata); + + switch (board) { + case MX31SMARTBOT: + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + break; + case MX31EYEBOT: + smartbot_otg_host_init(); + break; + default: + printk(KERN_WARNING "Unknown board %d, USB OTG not initialized", + board); + } + smartbot_resets_init(); smartbot_cam_init(); diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index ee67a71db80d..ed885f9d7b73 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -12,11 +12,16 @@ #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/fsl_devices.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx51.h> +#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> @@ -26,6 +31,18 @@ #include "devices.h" +#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ +#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ +#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ + +/* USB_CTRL_1 */ +#define MX51_USB_CTRL_1_OFFSET 0x10 +#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) + +#define MX51_USB_PLLDIV_12_MHZ 0x00 +#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 +#define MX51_USB_PLL_DIV_24_MHZ 0x02 + static struct platform_device *devices[] __initdata = { &mxc_fec_device, }; @@ -46,6 +63,22 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_EIM_D26__UART3_TXD, MX51_PAD_EIM_D27__UART3_RTS, MX51_PAD_EIM_D24__UART3_CTS, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + /* USB HUB reset line*/ + MX51_PAD_GPIO_1_7__GPIO1_7, }; /* Serial ports */ @@ -66,15 +99,149 @@ static inline void mxc_init_imx_uart(void) } #endif /* SERIAL_IMX */ +static int gpio_usbh1_active(void) +{ + struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; + struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; + int ret; + + /* Set USBH1_STP to GPIO and toggle it */ + mxc_iomux_v3_setup_pad(&usbh1stp_gpio); + ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); + + if (ret) { + pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret); + return ret; + } + gpio_direction_output(BABBAGE_USBH1_STP, 0); + gpio_set_value(BABBAGE_USBH1_STP, 1); + msleep(100); + gpio_free(BABBAGE_USBH1_STP); + + /* De-assert USB PHY RESETB */ + mxc_iomux_v3_setup_pad(&phyreset_gpio); + ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); + + if (ret) { + pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret); + return ret; + } + gpio_direction_output(BABBAGE_PHY_RESET, 1); + return 0; +} + +static inline void babbage_usbhub_reset(void) +{ + int ret; + + /* Bring USB hub out of reset */ + ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); + return; + } + gpio_direction_output(BABBAGE_USB_HUB_RESET, 0); + + /* USB HUB RESET - De-assert USB HUB RESET_N */ + msleep(1); + gpio_set_value(BABBAGE_USB_HUB_RESET, 0); + msleep(1); + gpio_set_value(BABBAGE_USB_HUB_RESET, 1); +} + +/* This function is board specific as the bit mask for the plldiv will also +be different for other Freescale SoCs, thus a common bitmask is not +possible and cannot get place in /plat-mxc/ehci.c.*/ +static int initialize_otg_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + u32 usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* Set the PHY clock to 19.2MHz */ + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; + v |= MX51_USB_PLL_DIV_19_2_MHZ; + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); + iounmap(usb_base); + return 0; +} + +static int initialize_usbh1_port(struct platform_device *pdev) +{ + u32 v; + void __iomem *usb_base; + u32 usbother_base; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + /* The clock for the USBH1 ULPI port will come externally from the PHY. */ + v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); + __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); + iounmap(usb_base); + return 0; +} + +static struct mxc_usbh_platform_data dr_utmi_config = { + .init = initialize_otg_port, + .portsc = MXC_EHCI_UTMI_16BIT, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, +}; + +static struct mxc_usbh_platform_data usbh1_config = { + .init = initialize_usbh1_port, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), +}; + +static int otg_mode_host; + +static int __init babbage_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", babbage_otg_mode); + /* * Board specific initialization. */ static void __init mxc_board_init(void) { + struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); mxc_init_imx_uart(); platform_add_devices(devices, ARRAY_SIZE(devices)); + + if (otg_mode_host) + mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + else { + initialize_otg_port(NULL); + mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + } + + gpio_usbh1_active(); + mxc_register_device(&mxc_usbh1_device, &usbh1_config); + /* setback USBH1_STP to be function */ + mxc_iomux_v3_setup_pad(&usbh1stp); + babbage_usbhub_reset(); } static void __init mx51_babbage_timer_init(void) diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 1ee6ce4087b8..d9f612d3370e 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -37,6 +37,7 @@ static struct clk lp_apm_clk; static struct clk periph_apm_clk; static struct clk ahb_clk; static struct clk ipg_clk; +static struct clk usboh3_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ @@ -570,6 +571,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) return 0; } +static unsigned long clk_usboh3_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; + + return parent_rate / (prediv * podf); +} + +static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + static unsigned long get_high_reference_clock_rate(struct clk *clk) { return external_high_reference; @@ -691,6 +721,12 @@ static struct clk uart_root_clk = { .set_parent = _clk_uart_set_parent, }; +static struct clk usboh3_clk = { + .parent = &pll2_sw_clk, + .get_rate = clk_usboh3_get_rate, + .set_parent = _clk_usboh3_set_parent, +}; + static struct clk ahb_max_clk = { .parent = &ahb_clk, .enable_reg = MXC_CCM_CCGR0, @@ -779,6 +815,12 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) + _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) + _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) }; static void clk_tree_init(void) @@ -819,6 +861,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + /* set the usboh3_clk parent to pll2_sw_clk */ + clk_set_parent(&usboh3_clk, &pll2_sw_clk); + /* System timer */ mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_MXC_INT_GPT); diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index d6fd3961ade9..7130449aacdc 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -1,5 +1,6 @@ /* * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -10,8 +11,11 @@ */ #include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/hardware.h> #include <mach/imx-uart.h> +#include <mach/irqs.h> static struct resource uart0[] = { { @@ -89,8 +93,109 @@ struct platform_device mxc_fec_device = { .resource = mxc_fec_resources, }; -/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ +static u64 usb_dma_mask = DMA_BIT_MASK(32); + +static struct resource usbotg_resources[] = { + { + .start = MX51_OTG_BASE_ADDR, + .end = MX51_OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +/* OTG gadget device */ +struct platform_device mxc_usbdr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .num_resources = ARRAY_SIZE(usbotg_resources), + .resource = usbotg_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device mxc_usbdr_host_device = { + .name = "mxc-ehci", + .id = 0, + .num_resources = ARRAY_SIZE(usbotg_resources), + .resource = usbotg_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource usbh1_resources[] = { + { + .start = MX51_OTG_BASE_ADDR + 0x200, + .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_MXC_INT_USB_H1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_usbh1_device = { + .name = "mxc-ehci", + .id = 1, + .num_resources = ARRAY_SIZE(usbh1_resources), + .resource = usbh1_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource mxc_wdt_resources[] = { + { + .start = MX51_WDOG_BASE_ADDR, + .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_wdt = { + .name = "imx2-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_wdt_resources), + .resource = mxc_wdt_resources, +}; + +static struct mxc_gpio_port mxc_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), + .irq = MX51_MXC_INT_GPIO1_LOW, + .virtual_irq_start = MXC_GPIO_IRQ_START + }, + { + .chip.label = "gpio-1", + .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), + .irq = MX51_MXC_INT_GPIO2_LOW, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 + }, + { + .chip.label = "gpio-2", + .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), + .irq = MX51_MXC_INT_GPIO3_LOW, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 + }, + { + .chip.label = "gpio-3", + .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), + .irq = MX51_MXC_INT_GPIO4_LOW, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 + }, +}; + int __init mxc_register_gpios(void) { - return 0; + return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index f339ab8c19be..c879ae71cd5b 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -2,3 +2,7 @@ extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device1; extern struct platform_device mxc_uart_device2; extern struct platform_device mxc_fec_device; +extern struct platform_device mxc_usbdr_host_device; +extern struct platform_device mxc_usbh1_device; +extern struct platform_device mxc_usbdr_udc_device; +extern struct platform_device mxc_wdt; diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c index 60f5bee09f2e..f035f4185274 100644 --- a/arch/arm/mach-nomadik/clock.c +++ b/arch/arm/mach-nomadik/clock.c @@ -32,7 +32,10 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); -/* We have a fixed clock alone, for now */ +static struct clk clk_24 = { + .rate = 2400000, +}; + static struct clk clk_48 = { .rate = 48 * 1000 * 1000, }; @@ -50,18 +53,19 @@ static struct clk clk_default; } static struct clk_lookup lookups[] = { + CLK(&clk_24, "mtu0"), + CLK(&clk_24, "mtu1"), CLK(&clk_48, "uart0"), CLK(&clk_48, "uart1"), CLK(&clk_default, "gpio.0"), CLK(&clk_default, "gpio.1"), CLK(&clk_default, "gpio.2"), CLK(&clk_default, "gpio.3"), + CLK(&clk_default, "rng"), }; -static int __init clk_init(void) +int __init clk_init(void) { clkdev_add_table(lookups, ARRAY_SIZE(lookups)); return 0; } - -arch_initcall(clk_init); diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h index 5563985a2cc7..78da2e7c3985 100644 --- a/arch/arm/mach-nomadik/clock.h +++ b/arch/arm/mach-nomadik/clock.h @@ -11,3 +11,5 @@ struct clk { unsigned long rate; }; + +int __init clk_init(void); diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 91c3c901b469..ac58e3b03b1a 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -31,6 +31,8 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#include "clock.h" + #define __MEM_4K_RESOURCE(x) \ .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} @@ -143,6 +145,12 @@ void __init cpu8815_init_irq(void) /* This modified VIC cell has two register blocks, at 0 and 0x20 */ vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START + 0, ~0, 0); vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0); + + /* + * Init clocks here so that they are available for system timer + * initialization. + */ + clk_init(); } /* diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d28e9e5702a0..ea52b034e963 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -119,6 +119,7 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-sdram.o \ board-rx51-peripherals.o \ + board-rx51-video.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-peripherals.o \ diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index e7d629b3c76a..f474a80b8867 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -137,9 +137,7 @@ static void ads7846_dev_init(void) } gpio_direction_input(ts_gpio); - - omap_set_gpio_debounce(ts_gpio, 1); - omap_set_gpio_debounce_time(ts_gpio, 0xa); + gpio_set_debounce(ts_gpio, 310); } static int ads7846_get_pendown_state(void) diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 5fcb52e71298..fefd7e6e9779 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -209,8 +209,7 @@ static void ads7846_dev_init(void) } gpio_direction_input(ts_gpio); - omap_set_gpio_debounce(ts_gpio, 1); - omap_set_gpio_debounce_time(ts_gpio, 0xa); + gpio_set_debounce(ts_gpio, 310); } static int ads7846_get_pendown_state(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 962d377970e9..69b154cdc75d 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -39,6 +39,7 @@ #include <plat/board.h> #include <plat/common.h> +#include <plat/display.h> #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> @@ -106,6 +107,77 @@ static struct platform_device omap3beagle_nand_device = { .resource = &omap3beagle_nand_resource, }; +/* DSS */ + +static int beagle_enable_dvi(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); + + return 0; +} + +static void beagle_disable_dvi(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); +} + +static struct omap_dss_device beagle_dvi_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "dvi", + .driver_name = "generic_panel", + .phy.dpi.data_lines = 24, + .reset_gpio = 170, + .platform_enable = beagle_enable_dvi, + .platform_disable = beagle_disable_dvi, +}; + +static struct omap_dss_device beagle_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +}; + +static struct omap_dss_device *beagle_dss_devices[] = { + &beagle_dvi_device, + &beagle_tv_device, +}; + +static struct omap_dss_board_info beagle_dss_data = { + .num_devices = ARRAY_SIZE(beagle_dss_devices), + .devices = beagle_dss_devices, + .default_device = &beagle_dvi_device, +}; + +static struct platform_device beagle_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &beagle_dss_data, + }, +}; + +static struct regulator_consumer_supply beagle_vdac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); + +static struct regulator_consumer_supply beagle_vdvi_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); + +static void __init beagle_display_init(void) +{ + int r; + + r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset"); + if (r < 0) { + printk(KERN_ERR "Unable to get DVI reset GPIO\n"); + return; + } + + gpio_direction_output(beagle_dvi_device.reset_gpio, 0); +} + #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -117,15 +189,6 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct platform_device omap3_beagle_lcd_device = { - .name = "omap3beagle_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static struct regulator_consumer_supply beagle_vmmc1_supply = { .supply = "vmmc", }; @@ -181,16 +244,6 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = { .setup = beagle_twl_gpio_setup, }; -static struct regulator_consumer_supply beagle_vdac_supply = { - .supply = "vdac", - .dev = &omap3_beagle_lcd_device.dev, -}; - -static struct regulator_consumer_supply beagle_vdvi_supply = { - .supply = "vdvi", - .dev = &omap3_beagle_lcd_device.dev, -}; - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data beagle_vmmc1 = { .constraints = { @@ -349,14 +402,8 @@ static struct platform_device keys_gpio = { }, }; -static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { - { OMAP_TAG_LCD, &omap3_beagle_lcd_config }, -}; - static void __init omap3_beagle_init_irq(void) { - omap_board_config = omap3_beagle_config; - omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); @@ -367,9 +414,9 @@ static void __init omap3_beagle_init_irq(void) } static struct platform_device *omap3_beagle_devices[] __initdata = { - &omap3_beagle_lcd_device, &leds_gpio, &keys_gpio, + &beagle_dss_device, }; static void __init omap3beagle_flash_init(void) @@ -456,6 +503,8 @@ static void __init omap3_beagle_init(void) /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + + beagle_display_init(); } static void __init omap3_beagle_map_io(void) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 81bba194b030..b95261013812 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -579,9 +579,7 @@ static void ads7846_dev_init(void) printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); gpio_direction_input(OMAP3_EVM_TS_GPIO); - - omap_set_gpio_debounce(OMAP3_EVM_TS_GPIO, 1); - omap_set_gpio_debounce_time(OMAP3_EVM_TS_GPIO, 0xa); + gpio_set_debounce(OMAP3_EVM_TS_GPIO, 310); } static int ads7846_get_pendown_state(void) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 395d049bf010..db06dc910ba7 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -130,8 +130,8 @@ static struct platform_device pandora_keys_gpio = { static void __init pandora_keys_gpio_init(void) { /* set debounce time for GPIO banks 4 and 6 */ - omap_set_gpio_debounce_time(32 * 3, GPIO_DEBOUNCE_TIME); - omap_set_gpio_debounce_time(32 * 5, GPIO_DEBOUNCE_TIME); + gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME); + gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME); } static int board_keymap[] = { diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 2504d41f923e..2f5f8233dd5b 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -328,8 +328,7 @@ static void __init omap3_ads7846_init(void) } gpio_direction_input(OMAP3_TS_GPIO); - omap_set_gpio_debounce(OMAP3_TS_GPIO, 1); - omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa); + gpio_set_debounce(OMAP3_TS_GPIO, 310); } static struct ads7846_platform_data ads7846_config = { diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 966f5f84f2bd..abdf321c2d41 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -45,6 +45,8 @@ /* list all spi devices here */ enum { RX51_SPI_WL1251, + RX51_SPI_MIPID, /* LCD panel */ + RX51_SPI_TSC2005, /* Touch Controller */ }; static struct wl12xx_platform_data wl1251_pdata; @@ -54,6 +56,16 @@ static struct omap2_mcspi_device_config wl1251_mcspi_config = { .single_channel = 1, }; +static struct omap2_mcspi_device_config mipid_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, +}; + +static struct omap2_mcspi_device_config tsc2005_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, +}; + static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { [RX51_SPI_WL1251] = { .modalias = "wl1251", @@ -64,6 +76,22 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .controller_data = &wl1251_mcspi_config, .platform_data = &wl1251_pdata, }, + [RX51_SPI_MIPID] = { + .modalias = "acx565akm", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 6000000, + .controller_data = &mipid_mcspi_config, + }, + [RX51_SPI_TSC2005] = { + .modalias = "tsc2005", + .bus_num = 1, + .chip_select = 0, + /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/ + .max_speed_hz = 6000000, + .controller_data = &tsc2005_mcspi_config, + /* .platform_data = &tsc2005_config,*/ + }, }; #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c new file mode 100644 index 000000000000..b743a4f42649 --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-omap2/board-rx51-video.c + * + * Copyright (C) 2010 Nokia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/spi/spi.h> +#include <linux/mm.h> + +#include <asm/mach-types.h> +#include <plat/mux.h> +#include <plat/display.h> +#include <plat/vram.h> +#include <plat/mcspi.h> + +#include "mux.h" + +#define RX51_LCD_RESET_GPIO 90 + +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) + +static int rx51_lcd_enable(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 1); + return 0; +} + +static void rx51_lcd_disable(struct omap_dss_device *dssdev) +{ + gpio_set_value(dssdev->reset_gpio, 0); +} + +static struct omap_dss_device rx51_lcd_device = { + .name = "lcd", + .driver_name = "panel-acx565akm", + .type = OMAP_DISPLAY_TYPE_SDI, + .phy.sdi.datapairs = 2, + .reset_gpio = RX51_LCD_RESET_GPIO, + .platform_enable = rx51_lcd_enable, + .platform_disable = rx51_lcd_disable, +}; + +static struct omap_dss_device *rx51_dss_devices[] = { + &rx51_lcd_device, +}; + +static struct omap_dss_board_info rx51_dss_board_info = { + .num_devices = ARRAY_SIZE(rx51_dss_devices), + .devices = rx51_dss_devices, + .default_device = &rx51_lcd_device, +}; + +struct platform_device rx51_display_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &rx51_dss_board_info, + }, +}; + +static struct platform_device *rx51_video_devices[] __initdata = { + &rx51_display_device, +}; + +static int __init rx51_video_init(void) +{ + if (!machine_is_nokia_rx51()) + return 0; + + if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) { + pr_err("%s cannot configure MUX for LCD RESET\n", __func__); + return 0; + } + + if (gpio_request(RX51_LCD_RESET_GPIO, "LCD ACX565AKM reset")) { + pr_err("%s failed to get LCD Reset GPIO\n", __func__); + return 0; + } + + gpio_direction_output(RX51_LCD_RESET_GPIO, 1); + + platform_add_devices(rx51_video_devices, + ARRAY_SIZE(rx51_video_devices)); + return 0; +} + +subsys_initcall(rx51_video_init); + +void __init rx51_video_mem_init(void) +{ + /* + * GFX 864x480x32bpp + * VID1/2 1280x720x32bpp double buffered + */ + omap_vram_set_sdram_vram(PAGE_ALIGN(864 * 480 * 4) + + 2 * PAGE_ALIGN(1280 * 720 * 4 * 2), 0); +} + +#else +void __init rx51_video_mem_init(void) { } +#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */ diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index b155c366c650..1b86b5bb87a2 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -36,6 +36,7 @@ #define RX51_GPIO_SLEEP_IND 162 struct omap_sdrc_params *rx51_get_sdram_timings(void); +extern void rx51_video_mem_init(void); static struct gpio_led gpio_leds[] = { { @@ -143,6 +144,7 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { omap2_set_globals_343x(); + rx51_video_mem_init(); omap34xx_map_common_io(); } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 23bc981574f6..37d65d62ed8f 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1836,7 +1836,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), CLK(NULL, "des_ick", &des_ick, CK_242X), - CLK(NULL, "sha_ick", &sha_ick, CK_242X), + CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), CLK(NULL, "aes_ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 2df50d97deb2..b33118fb6a87 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1924,7 +1924,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), CLK(NULL, "des_ick", &des_ick, CK_243X), - CLK(NULL, "sha_ick", &sha_ick, CK_243X), + CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), CLK(NULL, "aes_ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 833be485c89e..41b155acfca7 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3284,7 +3284,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), - CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), + CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 705a7a30a87f..03e6c9ed82a4 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -28,6 +28,7 @@ #include <plat/mux.h> #include <mach/gpio.h> #include <plat/mmc.h> +#include <plat/dma.h> #include "mux.h" @@ -486,8 +487,10 @@ static void omap_init_pmu(void) } -#ifdef CONFIG_OMAP_SHA1_MD5 -static struct resource sha1_md5_resources[] = { +#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) + +#ifdef CONFIG_ARCH_OMAP2 +static struct resource omap2_sham_resources[] = { { .start = OMAP24XX_SEC_SHA1MD5_BASE, .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, @@ -498,20 +501,55 @@ static struct resource sha1_md5_resources[] = { .flags = IORESOURCE_IRQ, } }; +static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); +#else +#define omap2_sham_resources NULL +#define omap2_sham_resources_sz 0 +#endif -static struct platform_device sha1_md5_device = { - .name = "OMAP SHA1/MD5", +#ifdef CONFIG_ARCH_OMAP3 +static struct resource omap3_sham_resources[] = { + { + .start = OMAP34XX_SEC_SHA1MD5_BASE, + .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_34XX_SHA1MD52_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = OMAP34XX_DMA_SHA1MD5_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); +#else +#define omap3_sham_resources NULL +#define omap3_sham_resources_sz 0 +#endif + +static struct platform_device sham_device = { + .name = "omap-sham", .id = -1, - .num_resources = ARRAY_SIZE(sha1_md5_resources), - .resource = sha1_md5_resources, }; -static void omap_init_sha1_md5(void) +static void omap_init_sham(void) { - platform_device_register(&sha1_md5_device); + if (cpu_is_omap24xx()) { + sham_device.resource = omap2_sham_resources; + sham_device.num_resources = omap2_sham_resources_sz; + } else if (cpu_is_omap34xx()) { + sham_device.resource = omap3_sham_resources; + sham_device.num_resources = omap3_sham_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&sham_device); } #else -static inline void omap_init_sha1_md5(void) { } +static inline void omap_init_sham(void) { } #endif /*-------------------------------------------------------------------------*/ @@ -869,7 +907,7 @@ static int __init omap2_init_devices(void) omap_init_pmu(); omap_hdq_init(); omap_init_sti(); - omap_init_sha1_md5(); + omap_init_sham(); omap_init_vout(); return 0; diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 685f34a9634b..fe0de1698edc 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -240,22 +240,23 @@ error_fail: #define ORION_BLINK_HALF_PERIOD 100 /* ms */ -static int dns323_gpio_blink_set(unsigned gpio, +static int dns323_gpio_blink_set(unsigned gpio, int state, unsigned long *delay_on, unsigned long *delay_off) { - static int value = 0; - if (!*delay_on && !*delay_off) + if (delay_on && delay_off && !*delay_on && !*delay_off) *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; - if (ORION_BLINK_HALF_PERIOD == *delay_on - && ORION_BLINK_HALF_PERIOD == *delay_off) { - value = !value; - orion_gpio_set_blink(gpio, value); - return 0; + switch(state) { + case GPIO_LED_NO_BLINK_LOW: + case GPIO_LED_NO_BLINK_HIGH: + orion_gpio_set_blink(gpio, 0); + gpio_set_value(gpio, state); + break; + case GPIO_LED_BLINK: + orion_gpio_set_blink(gpio, 1); } - - return -EINVAL; + return 0; } static struct gpio_led dns323_leds[] = { @@ -263,6 +264,7 @@ static struct gpio_led dns323_leds[] = { .name = "power:blue", .gpio = DNS323_GPIO_LED_POWER2, .default_trigger = "timer", + .active_low = 1, }, { .name = "right:amber", .gpio = DNS323_GPIO_LED_RIGHT_AMBER, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 033b567e50bb..ce1104d1bc17 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -263,11 +263,11 @@ const struct matrix_keymap_data palmtc_keymap_data = { .keymap_size = ARRAY_SIZE(palmtc_matrix_keys), }; -const static unsigned int palmtc_keypad_row_gpios[] = { +static const unsigned int palmtc_keypad_row_gpios[] = { 0, 9, 10, 11 }; -const static unsigned int palmtc_keypad_col_gpios[] = { +static const unsigned int palmtc_keypad_col_gpios[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 79, 80 }; diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 4d2413ed0ffa..c1048a35f187 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -818,6 +818,9 @@ static struct i2c_board_info akita_i2c_board_info[] = { .type = "max7310", .addr = 0x18, .platform_data = &akita_ioexp, + }, { + .type = "wm8750", + .addr = 0x1b, }, }; diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 091c98a639d9..cd3983ad4160 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -114,6 +114,7 @@ #define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0 +#define S3C_PA_WDT S3C2410_PA_WATCHDOG #define S3C_PA_NAND S3C24XX_PA_NAND #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 45799c608d8f..9e39faa283b9 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -49,7 +49,6 @@ #include <linux/io.h> #include <linux/i2c.h> -#include <linux/backlight.h> #include <linux/regulator/machine.h> #include <linux/mfd/pcf50633/core.h> @@ -57,6 +56,7 @@ #include <linux/mfd/pcf50633/adc.h> #include <linux/mfd/pcf50633/gpio.h> #include <linux/mfd/pcf50633/pmic.h> +#include <linux/mfd/pcf50633/backlight.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -254,6 +254,12 @@ static char *gta02_batteries[] = { "battery", }; +static struct pcf50633_bl_platform_data gta02_backlight_data = { + .default_brightness = 0x3f, + .default_brightness_limit = 0, + .ramp_time = 5, +}; + struct pcf50633_platform_data gta02_pcf_pdata = { .resumers = { [0] = PCF50633_INT1_USBINS | @@ -271,6 +277,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = { .charger_reference_current_ma = 1000, + .backlight_data = >a02_backlight_data, + .reg_init_data = { [PCF50633_REGULATOR_AUTO] = { .constraints = { @@ -478,71 +486,6 @@ static struct s3c2410_udc_mach_info gta02_udc_cfg = { }; - - -static void gta02_bl_set_intensity(int intensity) -{ - struct pcf50633 *pcf = gta02_pcf; - int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); - - /* We map 8-bit intensity to 6-bit intensity in hardware. */ - intensity >>= 2; - - /* - * This can happen during, eg, print of panic on blanked console, - * but we can't service i2c without interrupts active, so abort. - */ - if (in_atomic()) { - printk(KERN_ERR "gta02_bl_set_intensity called while atomic\n"); - return; - } - - old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); - if (intensity == old_intensity) - return; - - /* We can't do this anywhere else. */ - pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5); - - if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3)) - old_intensity = 0; - - /* - * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60) - * if seen, you have to re-enable the LED unit. - */ - if (!intensity || !old_intensity) - pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0); - - /* Illegal to set LEDOUT to 0. */ - if (!intensity) - pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, 2); - else - pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, - intensity); - - if (intensity) - pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2); - -} - -static struct generic_bl_info gta02_bl_info = { - .name = "gta02-bl", - .max_intensity = 0xff, - .default_intensity = 0xff, - .set_bl_intensity = gta02_bl_set_intensity, -}; - -static struct platform_device gta02_bl_dev = { - .name = "generic-bl", - .id = 1, - .dev = { - .platform_data = >a02_bl_info, - }, -}; - - - /* USB */ static struct s3c2410_hcd_info gta02_usb_info __initdata = { .port[0] = { @@ -579,7 +522,6 @@ static struct platform_device *gta02_devices[] __initdata = { /* These guys DO need to be children of PMU. */ static struct platform_device *gta02_devices_pmu_children[] = { - >a02_bl_dev, }; diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 69e9fbfea917..f5a59727949f 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -7,6 +7,7 @@ config PLAT_S3C64XX bool depends on ARCH_S3C64XX + select SAMSUNG_WAKEMASK default y help Base platform code for any Samsung S3C64XX device @@ -35,6 +36,11 @@ config S3C64XX_SETUP_SDHCI Internal configuration for default SDHCI setup for S3C6400 and S3C6410 SoCs. +config S3C64XX_DEV_ONENAND1 + bool + help + Compile in platform device definition for OneNAND1 controller + # platform specific device setup config S3C64XX_SETUP_I2C0 @@ -90,8 +96,11 @@ config MACH_SMDK6410 select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 select S3C_DEV_FB + select SAMSUNG_DEV_TS select S3C_DEV_USB_HOST select S3C_DEV_USB_HSOTG + select S3C_DEV_WDT + select HAVE_S3C2410_WATCHDOG select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_FB_24BPP @@ -179,3 +188,34 @@ config MACH_HMT select HAVE_PWM help Machine support for the Airgoo HMT + +config MACH_SMARTQ + bool + select CPU_S3C6410 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_FB + select S3C_DEV_HWMON + select S3C_DEV_RTC + select S3C_DEV_USB_HSOTG + select S3C_DEV_USB_HOST + select S3C64XX_SETUP_SDHCI + select S3C64XX_SETUP_FB_24BPP + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_TS + select HAVE_PWM + help + Shared machine support for SmartQ 5/7 + +config MACH_SMARTQ5 + bool "SmartQ 5" + select MACH_SMARTQ + help + Machine support for the SmartQ 5 + +config MACH_SMARTQ7 + bool "SmartQ 7" + select MACH_SMARTQ + help + Machine support for the SmartQ 7 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index a10f1fc6b023..9d1006938f5c 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -52,6 +52,9 @@ obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o obj-$(CONFIG_MACH_NCP) += mach-ncp.o obj-$(CONFIG_MACH_HMT) += mach-hmt.o +obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o +obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o +obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o # device support @@ -59,3 +62,4 @@ obj-y += dev-uart.o obj-y += dev-audio.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o +obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 7a4138beb665..fbd85a9b7bbf 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -259,6 +259,12 @@ static struct clk init_clocks[] = { .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, }, { + .name = "otg", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_USB, + }, { .name = "timers", .id = -1, .parent = &clk_p, diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c new file mode 100644 index 000000000000..92ffd5bac104 --- /dev/null +++ b/arch/arm/mach-s3c64xx/dev-onenand1.c @@ -0,0 +1,55 @@ +/* + * linux/arch/arm/mach-s3c64xx/dev-onenand1.c + * + * Copyright (c) 2008-2010 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * + * S3C64XX series device definition for OneNAND devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +static struct resource s3c64xx_onenand1_resources[] = { + [0] = { + .start = S3C64XX_PA_ONENAND1, + .end = S3C64XX_PA_ONENAND1 + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C64XX_PA_ONENAND1_BUF, + .end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_ONENAND1, + .end = IRQ_ONENAND1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c64xx_device_onenand1 = { + .name = "samsung-onenand", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources), + .resource = s3c64xx_onenand1_resources, +}; + +void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) +{ + struct onenand_platform_data *pd; + + pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); + if (!pd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + s3c64xx_device_onenand1.dev.platform_data = pd; +} diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index e9ab4ac0b9a8..8e2df26cf14a 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -212,5 +212,9 @@ #define NR_IRQS (IRQ_BOARD_END + 1) +/* Compatibility */ + +#define IRQ_ONENAND IRQ_ONENAND0 + #endif /* __ASM_MACH_S3C64XX_IRQS_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 9fdd50c8c767..e1eab3c94aea 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -52,6 +52,16 @@ #define S3C64XX_PA_SROM (0x70000000) +#define S3C64XX_PA_ONENAND0 (0x70100000) +#define S3C64XX_PA_ONENAND0_BUF (0x20000000) +#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) + +/* NAND and OneNAND1 controllers occupy the same register region + (depending on SoC POP version) */ +#define S3C64XX_PA_ONENAND1 (0x70200000) +#define S3C64XX_PA_ONENAND1_BUF (0x28000000) +#define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) + #define S3C64XX_PA_NAND (0x70200000) #define S3C64XX_PA_FB (0x77100000) #define S3C64XX_PA_USB_HSOTG (0x7C000000) @@ -99,11 +109,15 @@ #define S3C_PA_IIC S3C64XX_PA_IIC0 #define S3C_PA_IIC1 S3C64XX_PA_IIC1 #define S3C_PA_NAND S3C64XX_PA_NAND +#define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 +#define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF +#define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF #define S3C_PA_FB S3C64XX_PA_FB #define S3C_PA_USBHOST S3C64XX_PA_USBHOST #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY #define S3C_PA_RTC S3C64XX_PA_RTC +#define S3C_PA_WDT S3C64XX_PA_WATCHDOG #define SAMSUNG_PA_ADC S3C64XX_PA_ADC diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c new file mode 100644 index 000000000000..028d080dcd35 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -0,0 +1,363 @@ +/* + * linux/arch/arm/mach-s3c64xx/mach-smartq.c + * + * Copyright (C) 2010 Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/delay.h> +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/serial_core.h> +#include <linux/usb/gpio_vbus.h> + +#include <asm/mach-types.h> +#include <asm/mach/map.h> + +#include <mach/map.h> +#include <mach/regs-gpio.h> +#include <mach/regs-modem.h> + +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> +#include <plat/hwmon.h> +#include <plat/regs-serial.h> +#include <plat/udc-hs.h> +#include <plat/usb-control.h> +#include <plat/sdhci.h> +#include <plat/ts.h> + +#include <video/platform_lcd.h> + +#define UCON S3C2410_UCON_DEFAULT +#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) +#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) + +static struct s3c2410_uartcfg smartq_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +static void smartq_usb_host_powercontrol(int port, int to) +{ + pr_debug("%s(%d, %d)\n", __func__, port, to); + + if (port == 0) { + gpio_set_value(S3C64XX_GPL(0), to); + gpio_set_value(S3C64XX_GPL(1), to); + } +} + +static irqreturn_t smartq_usb_host_ocirq(int irq, void *pw) +{ + struct s3c2410_hcd_info *info = pw; + + if (gpio_get_value(S3C64XX_GPL(10)) == 0) { + pr_debug("%s: over-current irq (oc detected)\n", __func__); + s3c2410_usb_report_oc(info, 3); + } else { + pr_debug("%s: over-current irq (oc cleared)\n", __func__); + s3c2410_usb_report_oc(info, 0); + } + + return IRQ_HANDLED; +} + +static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on) +{ + int ret; + + /* This isn't present on a SmartQ 5 board */ + if (machine_is_smartq5()) + return; + + if (on) { + ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)), + smartq_usb_host_ocirq, IRQF_DISABLED | + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "USB host overcurrent", info); + if (ret != 0) + pr_err("failed to request usb oc irq: %d\n", ret); + } else { + free_irq(gpio_to_irq(S3C64XX_GPL(10)), info); + } +} + +static struct s3c2410_hcd_info smartq_usb_host_info = { + .port[0] = { + .flags = S3C_HCDFLG_USED + }, + .port[1] = { + .flags = 0 + }, + + .power_control = smartq_usb_host_powercontrol, + .enable_oc = smartq_usb_host_enableoc, +}; + +static struct gpio_vbus_mach_info smartq_usb_otg_vbus_pdata = { + .gpio_vbus = S3C64XX_GPL(9), + .gpio_pullup = -1, + .gpio_vbus_inverted = true, +}; + +static struct platform_device smartq_usb_otg_vbus_dev = { + .name = "gpio-vbus", + .dev.platform_data = &smartq_usb_otg_vbus_pdata, +}; + +static int __init smartq_bl_init(struct device *dev) +{ + s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2)); + + return 0; +} + +static struct platform_pwm_backlight_data smartq_backlight_data = { + .pwm_id = 1, + .max_brightness = 1000, + .dft_brightness = 600, + .pwm_period_ns = 1000000000 / (1000 * 20), + .init = smartq_bl_init, +}; + +static struct platform_device smartq_backlight_device = { + .name = "pwm-backlight", + .dev = { + .parent = &s3c_device_timer[1].dev, + .platform_data = &smartq_backlight_data, + }, +}; + +static struct s3c2410_ts_mach_info smartq_touchscreen_pdata __initdata = { + .delay = 65535, + .presc = 99, + .oversampling_shift = 4, +}; + +static struct s3c_sdhci_platdata smartq_internal_hsmmc_pdata = { + .max_width = 4, + /*.broken_card_detection = true,*/ +}; + +static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = { + /* Battery voltage (?-4.2V) */ + .in[0] = &(struct s3c_hwmon_chcfg) { + .name = "smartq:battery-voltage", + .mult = 3300, + .div = 2048, + }, + /* Reference voltage (1.2V) */ + .in[1] = &(struct s3c_hwmon_chcfg) { + .name = "smartq:reference-voltage", + .mult = 3300, + .div = 4096, + }, +}; + +static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) +{ + gpio_direction_output(S3C64XX_GPM(3), power); +} + +static struct plat_lcd_data smartq_lcd_power_data = { + .set_power = smartq_lcd_power_set, +}; + +static struct platform_device smartq_lcd_power_device = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smartq_lcd_power_data, +}; + + +static struct platform_device *smartq_devices[] __initdata = { + &s3c_device_hsmmc1, /* Init iNAND first, ... */ + &s3c_device_hsmmc0, /* ... then the external SD card */ + &s3c_device_hsmmc2, + &s3c_device_adc, + &s3c_device_fb, + &s3c_device_hwmon, + &s3c_device_i2c0, + &s3c_device_ohci, + &s3c_device_rtc, + &s3c_device_timer[1], + &s3c_device_ts, + &s3c_device_usb_hsotg, + &smartq_backlight_device, + &smartq_lcd_power_device, + &smartq_usb_otg_vbus_dev, +}; + +static void __init smartq_lcd_mode_set(void) +{ + u32 tmp; + + /* set the LCD type */ + tmp = __raw_readl(S3C64XX_SPCON); + tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; + tmp |= S3C64XX_SPCON_LCD_SEL_RGB; + __raw_writel(tmp, S3C64XX_SPCON); + + /* remove the LCD bypass */ + tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); + tmp &= ~MIFPCON_LCD_BYPASS; + __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); +} + +static void smartq_power_off(void) +{ + gpio_direction_output(S3C64XX_GPK(15), 1); +} + +static int __init smartq_power_off_init(void) +{ + int ret; + + ret = gpio_request(S3C64XX_GPK(15), "Power control"); + if (ret < 0) { + pr_err("%s: failed to get GPK15\n", __func__); + return ret; + } + + /* leave power on */ + gpio_direction_output(S3C64XX_GPK(15), 0); + + + pm_power_off = smartq_power_off; + + return ret; +} + +static int __init smartq_usb_host_init(void) +{ + int ret; + + ret = gpio_request(S3C64XX_GPL(0), "USB power control"); + if (ret < 0) { + pr_err("%s: failed to get GPL0\n", __func__); + return ret; + } + + ret = gpio_request(S3C64XX_GPL(1), "USB host power control"); + if (ret < 0) { + pr_err("%s: failed to get GPL1\n", __func__); + goto err; + } + + if (!machine_is_smartq5()) { + /* This isn't present on a SmartQ 5 board */ + ret = gpio_request(S3C64XX_GPL(10), "USB host overcurrent"); + if (ret < 0) { + pr_err("%s: failed to get GPL10\n", __func__); + goto err2; + } + } + + /* turn power off */ + gpio_direction_output(S3C64XX_GPL(0), 0); + gpio_direction_output(S3C64XX_GPL(1), 0); + if (!machine_is_smartq5()) + gpio_direction_input(S3C64XX_GPL(10)); + + s3c_device_ohci.dev.platform_data = &smartq_usb_host_info; + + return 0; + +err2: + gpio_free(S3C64XX_GPL(1)); +err: + gpio_free(S3C64XX_GPL(0)); + return ret; +} + +static int __init smartq_usb_otg_init(void) +{ + clk_xusbxti.rate = 12000000; + + return 0; +} + +static int __init smartq_wifi_init(void) +{ + int ret; + + ret = gpio_request(S3C64XX_GPK(1), "wifi control"); + if (ret < 0) { + pr_err("%s: failed to get GPK1\n", __func__); + return ret; + } + + ret = gpio_request(S3C64XX_GPK(2), "wifi reset"); + if (ret < 0) { + pr_err("%s: failed to get GPK2\n", __func__); + gpio_free(S3C64XX_GPK(1)); + return ret; + } + + /* turn power on */ + gpio_direction_output(S3C64XX_GPK(1), 1); + + /* reset device */ + gpio_direction_output(S3C64XX_GPK(2), 0); + mdelay(100); + gpio_set_value(S3C64XX_GPK(2), 1); + gpio_direction_input(S3C64XX_GPK(2)); + + return 0; +} + +static struct map_desc smartq_iodesc[] __initdata = {}; +void __init smartq_map_io(void) +{ + s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); + + smartq_lcd_mode_set(); +} + +void __init smartq_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + s3c_hwmon_set_platdata(&smartq_hwmon_pdata); + s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata); + s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata); + s3c24xx_ts_set_platdata(&smartq_touchscreen_pdata); + + WARN_ON(smartq_power_off_init()); + WARN_ON(smartq_usb_host_init()); + WARN_ON(smartq_usb_otg_init()); + WARN_ON(smartq_wifi_init()); + + platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); +} diff --git a/arch/arm/mach-s3c64xx/mach-smartq.h b/arch/arm/mach-s3c64xx/mach-smartq.h new file mode 100644 index 000000000000..8e8b693db3af --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq.h @@ -0,0 +1,20 @@ +/* + * linux/arch/arm/mach-s3c64xx/mach-smartq.h + * + * Copyright (C) 2010 Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MACH_SMARTQ_H +#define __MACH_SMARTQ_H __FILE__ + +#include <linux/init.h> + +extern void __init smartq_map_io(void); +extern void __init smartq_machine_init(void); + +#endif /* __MACH_SMARTQ_H */ diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c new file mode 100644 index 000000000000..1d0326ead90f --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -0,0 +1,185 @@ +/* + * linux/arch/arm/mach-s3c64xx/mach-smartq5.c + * + * Copyright (C) 2010 Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/i2c-gpio.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/leds.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/map.h> +#include <mach/regs-fb.h> +#include <mach/regs-gpio.h> +#include <mach/s3c6410.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +#include "mach-smartq.h" + +static void __init smartq5_lcd_setup_gpio(void) +{ + gpio_request(S3C64XX_GPM(0), "LCD SCEN pin"); + gpio_request(S3C64XX_GPM(1), "LCD SCL pin"); + gpio_request(S3C64XX_GPM(2), "LCD SDA pin"); + gpio_request(S3C64XX_GPM(3), "LCD power"); + + /* turn power off */ + gpio_direction_output(S3C64XX_GPM(0), 1); + gpio_direction_input(S3C64XX_GPM(1)); + gpio_direction_input(S3C64XX_GPM(2)); + gpio_direction_output(S3C64XX_GPM(3), 0); +} + +static struct i2c_gpio_platform_data smartq5_lcd_control = { + .sda_pin = S3C64XX_GPM(2), + .scl_pin = S3C64XX_GPM(1), +}; + +static struct platform_device smartq5_lcd_control_device = { + .name = "i2c-gpio", + .id = 1, + .dev.platform_data = &smartq5_lcd_control, +}; + +static struct gpio_led smartq5_leds[] __initdata = { + { + .name = "smartq5:green", + .active_low = 1, + .gpio = S3C64XX_GPN(8), + }, + { + .name = "smartq5:red", + .active_low = 1, + .gpio = S3C64XX_GPN(9), + }, +}; + +static struct gpio_led_platform_data smartq5_led_data = { + .num_leds = ARRAY_SIZE(smartq5_leds), + .leds = smartq5_leds, +}; + +static struct platform_device smartq5_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &smartq5_led_data, +}; + +/* Labels according to the SmartQ manual */ +static struct gpio_keys_button smartq5_buttons[] = { + { + .gpio = S3C64XX_GPL(14), + .code = KEY_POWER, + .desc = "Power", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(2), + .code = KEY_KPMINUS, + .desc = "Minus", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(12), + .code = KEY_KPPLUS, + .desc = "Plus", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(15), + .code = KEY_ENTER, + .desc = "Move", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, +}; + +static struct gpio_keys_platform_data smartq5_buttons_data = { + .buttons = smartq5_buttons, + .nbuttons = ARRAY_SIZE(smartq5_buttons), +}; + +static struct platform_device smartq5_buttons_device = { + .name = "gpio-keys", + .id = 0, + .num_resources = 0, + .dev = { + .platform_data = &smartq5_buttons_data, + } +}; + +static struct s3c_fb_pd_win smartq5_fb_win0 = { + .win_mode = { + .pixclock = 1000000000000ULL / + ((40+1+216+800)*(10+1+35+480)*80), + .left_margin = 40, + .right_margin = 216, + .upper_margin = 10, + .lower_margin = 35, + .hsync_len = 1, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = { + .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, + .win[0] = &smartq5_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VDEN, +}; + +static struct platform_device *smartq5_devices[] __initdata = { + &smartq5_leds_device, + &smartq5_buttons_device, + &smartq5_lcd_control_device, +}; + +static void __init smartq5_machine_init(void) +{ + s3c_fb_set_platdata(&smartq5_lcd_pdata); + + smartq_machine_init(); + smartq5_lcd_setup_gpio(); + + platform_add_devices(smartq5_devices, ARRAY_SIZE(smartq5_devices)); +} + +MACHINE_START(SMARTQ5, "SmartQ 5") + /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + .init_irq = s3c6410_init_irq, + .map_io = smartq_map_io, + .init_machine = smartq5_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c new file mode 100644 index 000000000000..e0bc78ecb156 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -0,0 +1,201 @@ +/* + * linux/arch/arm/mach-s3c64xx/mach-smartq7.c + * + * Copyright (C) 2010 Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/i2c-gpio.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/leds.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/map.h> +#include <mach/regs-fb.h> +#include <mach/regs-gpio.h> +#include <mach/s3c6410.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +#include "mach-smartq.h" + +static void __init smartq7_lcd_setup_gpio(void) +{ + gpio_request(S3C64XX_GPM(0), "LCD CSB pin"); + gpio_request(S3C64XX_GPM(3), "LCD power"); + gpio_request(S3C64XX_GPM(4), "LCD power status"); + + /* turn power off */ + gpio_direction_output(S3C64XX_GPM(0), 1); + gpio_direction_output(S3C64XX_GPM(3), 0); + gpio_direction_input(S3C64XX_GPM(4)); +} + +static struct i2c_gpio_platform_data smartq7_lcd_control = { + .sda_pin = S3C64XX_GPM(2), + .scl_pin = S3C64XX_GPM(1), + .sda_is_open_drain = 1, + .scl_is_open_drain = 1, +}; + +static struct platform_device smartq7_lcd_control_device = { + .name = "i2c-gpio", + .id = 1, + .dev.platform_data = &smartq7_lcd_control, +}; + +static struct gpio_led smartq7_leds[] __initdata = { + { + .name = "smartq7:red", + .active_low = 1, + .gpio = S3C64XX_GPN(8), + }, + { + .name = "smartq7:green", + .active_low = 1, + .gpio = S3C64XX_GPN(9), + }, +}; + +static struct gpio_led_platform_data smartq7_led_data = { + .num_leds = ARRAY_SIZE(smartq7_leds), + .leds = smartq7_leds, +}; + +static struct platform_device smartq7_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &smartq7_led_data, +}; + +/* Labels according to the SmartQ manual */ +static struct gpio_keys_button smartq7_buttons[] = { + { + .gpio = S3C64XX_GPL(14), + .code = KEY_POWER, + .desc = "Power", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(2), + .code = KEY_FN, + .desc = "Function", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(3), + .code = KEY_KPMINUS, + .desc = "Minus", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(4), + .code = KEY_KPPLUS, + .desc = "Plus", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(12), + .code = KEY_ENTER, + .desc = "Enter", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, + { + .gpio = S3C64XX_GPN(15), + .code = KEY_ESC, + .desc = "Cancel", + .active_low = 1, + .debounce_interval = 5, + .type = EV_KEY, + }, +}; + +static struct gpio_keys_platform_data smartq7_buttons_data = { + .buttons = smartq7_buttons, + .nbuttons = ARRAY_SIZE(smartq7_buttons), +}; + +static struct platform_device smartq7_buttons_device = { + .name = "gpio-keys", + .id = 0, + .num_resources = 0, + .dev = { + .platform_data = &smartq7_buttons_data, + } +}; + +static struct s3c_fb_pd_win smartq7_fb_win0 = { + .win_mode = { + .pixclock = 1000000000000ULL / + ((3+10+5+800)*(1+3+20+480)*80), + .left_margin = 3, + .right_margin = 5, + .upper_margin = 1, + .lower_margin = 20, + .hsync_len = 10, + .vsync_len = 3, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = { + .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, + .win[0] = &smartq7_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK, +}; + +static struct platform_device *smartq7_devices[] __initdata = { + &smartq7_leds_device, + &smartq7_buttons_device, + &smartq7_lcd_control_device, +}; + +static void __init smartq7_machine_init(void) +{ + s3c_fb_set_platdata(&smartq7_lcd_pdata); + + smartq_machine_init(); + smartq7_lcd_setup_gpio(); + + platform_add_devices(smartq7_devices, ARRAY_SIZE(smartq7_devices)); +} + +MACHINE_START(SMARTQ7, "SmartQ 7") + /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + .init_irq = s3c6410_init_irq, + .map_io = smartq_map_io, + .init_machine = smartq7_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 9d51455feb31..d9a03555f88b 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -64,6 +64,8 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/adc.h> +#include <plat/ts.h> #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -262,6 +264,9 @@ static struct platform_device *smdk6410_devices[] __initdata = { &smdk6410_lcd_powerdev, &smdk6410_smsc911x, + &s3c_device_adc, + &s3c_device_ts, + &s3c_device_wdt, }; #ifdef CONFIG_REGULATOR @@ -596,6 +601,12 @@ static struct i2c_board_info i2c_devs1[] __initdata = { { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ }; +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, +}; + static void __init smdk6410_map_io(void) { u32 tmp; @@ -625,6 +636,8 @@ static void __init smdk6410_machine_init(void) s3c_i2c1_set_platdata(NULL); s3c_fb_set_platdata(&smdk6410_lcd_pdata); + s3c24xx_ts_set_platdata(&s3c_ts_platform); + /* configure nCS1 width to 16 bits */ cs1 = __raw_readl(S3C64XX_SROM_BW) & diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index b8ac4597fad7..79412f735a8d 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -18,8 +18,11 @@ #include <linux/io.h> #include <mach/map.h> +#include <mach/irqs.h> #include <plat/pm.h> +#include <plat/wakeup-mask.h> + #include <mach/regs-sys.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> @@ -153,8 +156,25 @@ static void s3c64xx_cpu_suspend(void) panic("sleep resumed to originator?"); } +/* mapping of interrupts to parts of the wakeup mask */ +static struct samsung_wakeup_mask wake_irqs[] = { + { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, }, + { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, }, + { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, }, + { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, }, + { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, }, + { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, }, + { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE}, + { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, + { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE }, + { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, +}; + static void s3c64xx_pm_prepare(void) { + samsung_sync_wakemask(S3C64XX_PWR_CFG, + wake_irqs, ARRAY_SIZE(wake_irqs)); + /* store address of resume. */ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 707e34e3afd1..5e93fe3f3f40 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -37,6 +37,7 @@ #include <plat/clock.h> #include <plat/sdhci.h> #include <plat/iic-core.h> +#include <plat/onenand-core.h> #include <mach/s3c6400.h> void __init s3c6400_map_io(void) @@ -51,6 +52,9 @@ void __init s3c6400_map_io(void) s3c_i2c0_setname("s3c2440-i2c"); s3c_device_nand.name = "s3c6400-nand"; + + s3c_onenand_setname("s3c6400-onenand"); + s3c64xx_onenand1_setname("s3c6400-onenand"); } void __init s3c6400_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 3ab695c691ee..014401c39f36 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -39,6 +39,7 @@ #include <plat/sdhci.h> #include <plat/iic-core.h> #include <plat/adc.h> +#include <plat/onenand-core.h> #include <mach/s3c6400.h> #include <mach/s3c6410.h> @@ -55,6 +56,8 @@ void __init s3c6410_map_io(void) s3c_device_adc.name = "s3c64xx-adc"; s3c_device_nand.name = "s3c6400-nand"; + s3c_onenand_setname("s3c6410-onenand"); + s3c64xx_onenand1_setname("s3c6410-onenand"); } void __init s3c6410_init_clocks(int xtal) diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index 77aeffd17330..f066fae07c57 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig @@ -16,6 +16,10 @@ config CPU_S5P6440 config MACH_SMDK6440 bool "SMDK6440" select CPU_S5P6440 + select SAMSUNG_DEV_TS + select SAMSUNG_DEV_ADC + select S3C_DEV_WDT + select HAVE_S3C2410_WATCHDOG help Machine support for the Samsung SMDK6440 diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index 44facf43d59f..be3c53aab23f 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o # device support obj-y += dev-audio.o +obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index ca3b3206e6f8..b2fe6a58155a 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c @@ -61,6 +61,7 @@ static void s5p6440_idle(void) void __init s5p6440_map_io(void) { /* initialize any device information early */ + s3c_device_adc.name = "s3c64xx-adc"; } void __init s5p6440_init_clocks(int xtal) diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c new file mode 100644 index 000000000000..0a30280019c0 --- /dev/null +++ b/arch/arm/mach-s5p6440/dev-spi.c @@ -0,0 +1,176 @@ +/* linux/arch/arm/mach-s5p6440/dev-spi.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <mach/spi-clocks.h> + +#include <plat/s3c64xx-spi.h> +#include <plat/gpio-cfg.h> + +static char *spi_src_clks[] = { + [S5P6440_SPI_SRCCLK_PCLK] = "pclk", + [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the CS. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s5p6440_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP); + break; + + case 1: + s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s5p6440_spi0_resource[] = { + [0] = { + .start = S5P6440_PA_SPI0, + .end = S5P6440_PA_SPI0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5p6440_spi0_pdata = { + .cfg_gpio = s5p6440_spi_cfg_gpio, + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5p6440_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s5p6440_spi0_resource), + .resource = s5p6440_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6440_spi0_pdata, + }, +}; + +static struct resource s5p6440_spi1_resource[] = { + [0] = { + .start = S5P6440_PA_SPI1, + .end = S5P6440_PA_SPI1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI1_TX, + .end = DMACH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI1_RX, + .end = DMACH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5p6440_spi1_pdata = { + .cfg_gpio = s5p6440_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, +}; + +struct platform_device s5p6440_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s5p6440_spi1_resource), + .resource = s5p6440_spi1_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6440_spi1_pdata, + }, +}; + +void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s5p6440_spi0_pdata; + break; + case 1: + pd = &s5p6440_spi1_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c index 262dc75d5bea..92efc05b1ba2 100644 --- a/arch/arm/mach-s5p6440/gpio.c +++ b/arch/arm/mach-s5p6440/gpio.c @@ -46,6 +46,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, void __iomem *base = ourchip->base; void __iomem *regcon = base; unsigned long con; + unsigned long flags; switch (offset) { case 6: @@ -63,10 +64,14 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, break; } + s3c_gpio_lock(ourchip, flags); + con = __raw_readl(regcon); con &= ~(0xf << con_4bit_shift(offset)); __raw_writel(con, regcon); + s3c_gpio_unlock(ourchip, flags); + return 0; } @@ -78,6 +83,7 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, void __iomem *regcon = base; unsigned long con; unsigned long dat; + unsigned long flags; unsigned con_offset = offset; switch (con_offset) { @@ -96,6 +102,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, break; } + s3c_gpio_lock(ourchip, flags); + con = __raw_readl(regcon); con &= ~(0xf << con_4bit_shift(con_offset)); con |= 0x1 << con_4bit_shift(con_offset); @@ -109,6 +117,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, __raw_writel(con, regcon); __raw_writel(dat, base + GPIODAT_OFF); + s3c_gpio_unlock(ourchip, flags); + return 0; } @@ -117,6 +127,7 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, { void __iomem *reg = chip->base; unsigned int shift; + unsigned long flags; u32 con; switch (off) { @@ -142,11 +153,15 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, cfg <<= shift; } + s3c_gpio_lock(chip, flags); + con = __raw_readl(reg); con &= ~(0xf << shift); con |= cfg; __raw_writel(con, reg); + s3c_gpio_unlock(chip, flags); + return 0; } diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h index a4b9b40d18f2..911854d9ad42 100644 --- a/arch/arm/mach-s5p6440/include/mach/irqs.h +++ b/arch/arm/mach-s5p6440/include/mach/irqs.h @@ -72,7 +72,14 @@ #define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) -#define IRQ_EINT(x) S5P_EINT(x) + +#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE) +/* + * S5P6440 has 0-15 external interrupts in group 0. Only these can be used + * to wake up from sleep. If request is beyond this range, by mistake, a large + * return value for an irq number should be indication of something amiss. + */ +#define S5P_EINT_BASE2 (0xf0000000) /* * Next the external interrupt groups. These are similar to the IRQ_EINT(x) diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 72aedadd412c..44011b91fbd1 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -54,6 +54,9 @@ #define S5P6440_PA_IIC0 (0xEC104000) +#define S5P6440_PA_SPI0 0xEC400000 +#define S5P6440_PA_SPI1 0xEC500000 + #define S5P6440_PA_HSOTG (0xED100000) #define S5P6440_PA_HSMMC0 (0xED800000) @@ -69,8 +72,13 @@ /* PCM */ #define S5P6440_PA_PCM 0xF2100000 +#define S5P6440_PA_ADC (0xF3000000) + /* compatibiltiy defines. */ #define S3C_PA_UART S5P6440_PA_UART #define S3C_PA_IIC S5P6440_PA_IIC0 +#define S3C_PA_WDT S5P6440_PA_WDT + +#define SAMSUNG_PA_ADC S5P6440_PA_ADC #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h new file mode 100644 index 000000000000..5fbca50d1cfb --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h @@ -0,0 +1,17 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S5P6440_PLAT_SPI_CLKS_H +#define __S5P6440_PLAT_SPI_CLKS_H __FILE__ + +#define S5P6440_SPI_SRCCLK_PCLK 0 +#define S5P6440_SPI_SRCCLK_SCLK 1 + +#endif /* __S5P6440_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index d7fede971ca6..8291fecc701a 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -38,6 +38,8 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pll.h> +#include <plat/adc.h> +#include <plat/ts.h> #define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -85,6 +87,15 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { static struct platform_device *smdk6440_devices[] __initdata = { &s5p6440_device_iis, + &s3c_device_adc, + &s3c_device_ts, + &s3c_device_wdt, +}; + +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, }; static void __init smdk6440_map_io(void) @@ -96,6 +107,8 @@ static void __init smdk6440_map_io(void) static void __init smdk6440_machine_init(void) { + s3c24xx_ts_set_platdata(&s3c_ts_platform); + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); } diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index e30a7f76aee6..90a3d8373416 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o # device support obj-y += dev-audio.o +obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c new file mode 100644 index 000000000000..30199525daca --- /dev/null +++ b/arch/arm/mach-s5p6442/dev-spi.c @@ -0,0 +1,123 @@ +/* linux/arch/arm/mach-s5p6442/dev-spi.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <mach/spi-clocks.h> + +#include <plat/s3c64xx-spi.h> +#include <plat/gpio-cfg.h> + +static char *spi_src_clks[] = { + [S5P6442_SPI_SRCCLK_PCLK] = "pclk", + [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the CS. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s5p6442_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s5p6442_spi0_resource[] = { + [0] = { + .start = S5P6442_PA_SPI, + .end = S5P6442_PA_SPI + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5p6442_spi0_pdata = { + .cfg_gpio = s5p6442_spi_cfg_gpio, + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5p6442_device_spi = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s5p6442_spi0_resource), + .resource = s5p6442_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5p6442_spi0_pdata, + }, +}; + +void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s5p6442_spi0_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h index da665809f6e4..02c23749c023 100644 --- a/arch/arm/mach-s5p6442/include/mach/irqs.h +++ b/arch/arm/mach-s5p6442/include/mach/irqs.h @@ -77,8 +77,9 @@ #define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) -#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \ - (S5P_IRQ_EINT_BASE + (x)-16)) +#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) +#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE) + /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT(31) + 1) diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 7568dc0d6be0..32ca424ef7f9 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -54,6 +54,8 @@ #define S5P6442_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5P6442_PA_SDRAM +#define S5P6442_PA_SPI 0xEC300000 + /* I2S */ #define S5P6442_PA_I2S0 0xC0B00000 #define S5P6442_PA_I2S1 0xF2200000 diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h new file mode 100644 index 000000000000..7fd88205a97c --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h @@ -0,0 +1,17 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S5P6442_PLAT_SPI_CLKS_H +#define __S5P6442_PLAT_SPI_CLKS_H __FILE__ + +#define S5P6442_SPI_SRCCLK_PCLK 0 +#define S5P6442_SPI_SRCCLK_SCLK 1 + +#endif /* __S5P6442_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 8593337784e1..b2a11dfa3399 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -5,10 +5,13 @@ # Configuration options for the S5PC100 CPU +if ARCH_S5PC100 + config CPU_S5PC100 bool - select CPU_S5PC100_INIT - select CPU_S5PC100_CLOCK + select PLAT_S5P + select S5P_EXT_INT + select S3C_PL330_DMA help Enable S5PC100 CPU support @@ -17,17 +20,22 @@ config S5PC100_SETUP_FB_24BPP help Common setup code for S5PC1XX with an 24bpp RGB display helper. -config S5PC100_SETUP_SDHCI - bool - select S5PC1XX_SETUP_SDHCI_GPIO - help - Internal helper functions for S5PC100 based SDHCI systems - config S5PC100_SETUP_I2C1 bool help Common setup code for i2c bus 1. +config S5PC100_SETUP_SDHCI + bool + select S5PC100_SETUP_SDHCI_GPIO + help + Internal helper functions for S5PC100 based SDHCI systems + +config S5PC100_SETUP_SDHCI_GPIO + bool + help + Common setup code for SDHCI gpio. + config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 @@ -41,3 +49,5 @@ config MACH_SMDKC100 select S5PC100_SETUP_SDHCI help Machine support for the Samsung SMDKC100 + +endif diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 373bc546eae8..543f3de5131e 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -11,14 +11,24 @@ obj- := # Core support for S5PC100 system -obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o +obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o +obj-$(CONFIG_CPU_S5PC100) += dma.o # Helper and device support obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o + +# device support +obj-y += dev-audio.o +obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o # machine support + obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o + +# device support +obj-y += dev-audio.o diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index d79e7574a852..7b5bdbc9a5df 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -22,47 +22,55 @@ #include <linux/serial_core.h> #include <linux/platform_device.h> -#include <asm/proc-fns.h> - #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <asm/proc-fns.h> + #include <mach/hardware.h> #include <mach/map.h> #include <asm/irq.h> -#include <plat/cpu-freq.h> #include <plat/regs-serial.h> -#include <plat/regs-power.h> +#include <mach/regs-clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> -#include <plat/sdhci.h> #include <plat/iic-core.h> +#include <plat/sdhci.h> +#include <plat/onenand-core.h> + #include <plat/s5pc100.h> /* Initial IO mappings */ static struct map_desc s5pc100_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC2, + .pfn = __phys_to_pfn(S5P_PA_VIC2), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5PC100_VA_OTHERS, + .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), + .length = SZ_4K, + .type = MT_DEVICE, + } }; static void s5pc100_idle(void) { - unsigned long tmp; - - tmp = __raw_readl(S5PC100_PWR_CFG); - tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE; - tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK; - tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE; - __raw_writel(tmp, S5PC100_PWR_CFG); - - tmp = __raw_readl(S5PC100_OTHERS); - tmp |= S5PC100_PMU_INT_DISABLE; - __raw_writel(tmp, S5PC100_OTHERS); + if (!need_resched()) + cpu_do_idle(); - cpu_do_idle(); + local_irq_enable(); } /* s5pc100_map_io @@ -82,26 +90,29 @@ void __init s5pc100_map_io(void) /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); + + s3c_onenand_setname("s5pc100-onenand"); } void __init s5pc100_init_clocks(int xtal) { - printk(KERN_DEBUG "%s: initialising clocks\n", __func__); + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + s3c24xx_register_baseclocks(xtal); - s5pc1xx_register_clocks(); + s5p_register_clocks(xtal); s5pc100_register_clocks(); s5pc100_setup_clocks(); } void __init s5pc100_init_irq(void) { - u32 vic_valid[] = {~0, ~0, ~0}; + u32 vic[] = {~0, ~0, ~0}; /* VIC0, VIC1, and VIC2 are fully populated. */ - s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid)); + s5p_init_irq(vic, ARRAY_SIZE(vic)); } -struct sysdev_class s5pc100_sysclass = { +static struct sysdev_class s5pc100_sysclass = { .name = "s5pc100-core", }; @@ -118,9 +129,10 @@ core_initcall(s5pc100_core_init); int __init s5pc100_init(void) { - printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); + printk(KERN_INFO "S5PC100: Initializing architecture\n"); - s5pc1xx_idle = s5pc100_idle; + /* set idle function */ + pm_idle = s5pc100_idle; return sysdev_register(&s5pc100_sysdev); } diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c new file mode 100644 index 000000000000..18cfe9ae1936 --- /dev/null +++ b/arch/arm/mach-s5pc100/dev-audio.c @@ -0,0 +1,287 @@ +/* linux/arch/arm/mach-s5pc100/dev-audio.c + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/gpio-cfg.h> +#include <plat/audio.h> + +#include <mach/gpio.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +static int s5pc100_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 1: + s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2)); + break; + + case 2: + s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4)); + break; + + case -1: /* Dedicated pins */ + break; + + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_i2s_pdata = { + .cfg_gpio = s5pc100_cfg_i2s, +}; + +static struct resource s5pc100_iis0_resource[] = { + [0] = { + .start = S5PC100_PA_I2S0, + .end = S5PC100_PA_I2S0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pc100_device_iis0 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s5pc100_iis0_resource), + .resource = s5pc100_iis0_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pc100_iis1_resource[] = { + [0] = { + .start = S5PC100_PA_I2S1, + .end = S5PC100_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pc100_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s5pc100_iis1_resource), + .resource = s5pc100_iis1_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pc100_iis2_resource[] = { + [0] = { + .start = S5PC100_PA_I2S2, + .end = S5PC100_PA_I2S2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pc100_device_iis2 = { + .name = "s3c64xx-iis", + .id = 2, + .num_resources = ARRAY_SIZE(s5pc100_iis2_resource), + .resource = s5pc100_iis2_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5)); + break; + + case 1: + s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3)); + break; + + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = s5pc100_pcm_cfg_gpio, +}; + +static struct resource s5pc100_pcm0_resource[] = { + [0] = { + .start = S5PC100_PA_PCM0, + .end = S5PC100_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pc100_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource), + .resource = s5pc100_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5pc100_pcm1_resource[] = { + [0] = { + .start = S5PC100_PA_PCM1, + .end = S5PC100_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pc100_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource), + .resource = s5pc100_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +/* AC97 Controller platform devices */ + +static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4)); + + return 0; +} + +static struct resource s5pc100_ac97_resource[] = { + [0] = { + .start = S5PC100_PA_AC97, + .end = S5PC100_PA_AC97 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_AC97_PCMOUT, + .end = DMACH_AC97_PCMOUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_AC97_PCMIN, + .end = DMACH_AC97_PCMIN, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_AC97_MICIN, + .end = DMACH_AC97_MICIN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = IRQ_AC97, + .end = IRQ_AC97, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_audio_pdata s3c_ac97_pdata = { + .cfg_gpio = s5pc100_ac97_cfg_gpio, +}; + +static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pc100_device_ac97 = { + .name = "s3c-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s5pc100_ac97_resource), + .resource = s5pc100_ac97_resource, + .dev = { + .platform_data = &s3c_ac97_pdata, + .dma_mask = &s5pc100_ac97_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c new file mode 100644 index 000000000000..14618c346057 --- /dev/null +++ b/arch/arm/mach-s5pc100/dev-spi.c @@ -0,0 +1,233 @@ +/* linux/arch/arm/mach-s5pc100/dev-spi.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/spi-clocks.h> + +#include <plat/s3c64xx-spi.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> + +static char *spi_src_clks[] = { + [S5PC100_SPI_SRCCLK_PCLK] = "pclk", + [S5PC100_SPI_SRCCLK_48M] = "spi_48m", + [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the CS. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP); + break; + + case 1: + s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP); + break; + + case 2: + s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s5pc100_spi0_resource[] = { + [0] = { + .start = S5PC100_PA_SPI0, + .end = S5PC100_PA_SPI0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5pc100_spi0_pdata = { + .cfg_gpio = s5pc100_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pc100_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s5pc100_spi0_resource), + .resource = s5pc100_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pc100_spi0_pdata, + }, +}; + +static struct resource s5pc100_spi1_resource[] = { + [0] = { + .start = S5PC100_PA_SPI1, + .end = S5PC100_PA_SPI1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI1_TX, + .end = DMACH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI1_RX, + .end = DMACH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5pc100_spi1_pdata = { + .cfg_gpio = s5pc100_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, +}; + +struct platform_device s5pc100_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s5pc100_spi1_resource), + .resource = s5pc100_spi1_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pc100_spi1_pdata, + }, +}; + +static struct resource s5pc100_spi2_resource[] = { + [0] = { + .start = S5PC100_PA_SPI2, + .end = S5PC100_PA_SPI2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI2_TX, + .end = DMACH_SPI2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI2_RX, + .end = DMACH_SPI2_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI2, + .end = IRQ_SPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5pc100_spi2_pdata = { + .cfg_gpio = s5pc100_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, +}; + +struct platform_device s5pc100_device_spi2 = { + .name = "s3c64xx-spi", + .id = 2, + .num_resources = ARRAY_SIZE(s5pc100_spi2_resource), + .resource = s5pc100_spi2_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pc100_spi2_pdata, + }, +}; + +void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s5pc100_spi0_pdata; + break; + case 1: + pd = &s5pc100_spi1_pdata; + break; + case 2: + pd = &s5pc100_spi2_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c new file mode 100644 index 000000000000..0f5517571e2c --- /dev/null +++ b/arch/arm/mach-s5pc100/dma.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/devs.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/s3c-pl330-pdata.h> + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +static struct resource s5pc100_pdma0_resource[] = { + [0] = { + .start = S5PC100_PA_PDMA0, + .end = S5PC100_PA_PDMA0 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA0, + .end = IRQ_PDMA0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pc100_pdma0_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_IRDA, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_I2S2_RX, + [15] = DMACH_I2S2_TX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_SPI2_RX, + [21] = DMACH_SPI2_TX, + [22] = DMACH_AC97_MICIN, + [23] = DMACH_AC97_PCMIN, + [24] = DMACH_AC97_PCMOUT, + [25] = DMACH_EXTERNAL, + [26] = DMACH_PWM, + [27] = DMACH_SPDIF, + [28] = DMACH_HSI_RX, + [29] = DMACH_HSI_TX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5pc100_device_pdma0 = { + .name = "s3c-pl330", + .id = 1, + .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource), + .resource = s5pc100_pdma0_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pc100_pdma0_pdata, + }, +}; + +static struct resource s5pc100_pdma1_resource[] = { + [0] = { + .start = S5PC100_PA_PDMA1, + .end = S5PC100_PA_PDMA1 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA1, + .end = IRQ_PDMA1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pc100_pdma1_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_IRDA, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_I2S2_RX, + [15] = DMACH_I2S2_TX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_SPI2_RX, + [21] = DMACH_SPI2_TX, + [22] = DMACH_PCM0_RX, + [23] = DMACH_PCM0_TX, + [24] = DMACH_PCM1_RX, + [25] = DMACH_PCM1_TX, + [26] = DMACH_MSM_REQ0, + [27] = DMACH_MSM_REQ1, + [28] = DMACH_MSM_REQ2, + [29] = DMACH_MSM_REQ3, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5pc100_device_pdma1 = { + .name = "s3c-pl330", + .id = 2, + .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource), + .resource = s5pc100_pdma1_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pc100_pdma1_pdata, + }, +}; + +static struct platform_device *s5pc100_dmacs[] __initdata = { + &s5pc100_device_pdma0, + &s5pc100_device_pdma1, +}; + +static int __init s5pc100_dma_init(void) +{ + platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs)); + + return 0; +} +arch_initcall(s5pc100_dma_init); diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index c8e8336a3a12..0fab7f2cd8bf 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c @@ -1,10 +1,10 @@ /* - * arch/arm/plat-s5pc1xx/gpiolib.c + * arch/arm/plat-s5pc100/gpiolib.c * * Copyright 2009 Samsung Electronics Co * Kyungmin Park <kyungmin.park@samsung.com> * - * S5PC1XX - GPIOlib support + * S5PC100 - GPIOlib support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -61,13 +61,12 @@ * L3 8 4Bit None */ -#if 0 -static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) +static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) { return S3C_IRQ_GPIO(chip->base + offset); } -static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) +static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) { int base; @@ -85,7 +84,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) return IRQ_EINT(24 + offset); return -EINVAL; } -#endif + static struct s3c_gpio_cfg gpio_cfg = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -382,31 +381,30 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { }; /* FIXME move from irq-gpio.c */ -extern struct irq_chip s5pc1xx_gpioint; -extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); +extern struct irq_chip s5pc100_gpioint; +extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) { -#if 0 /* Interrupt */ if (chip->config == &gpio_cfg) { int i, irq; - chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; + chip->chip.to_irq = s5pc100_gpiolib_to_irq; for (i = 0; i < chip->chip.ngpio; i++) { irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; - set_irq_chip(irq, &s5pc1xx_gpioint); + set_irq_chip(irq, &s5pc100_gpioint); set_irq_data(irq, &chip->chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - } else if (chip->config == &gpio_cfg_eint) - chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; -#endif + } else if (chip->config == &gpio_cfg_eint) { + chip->chip.to_irq = s5pc100_gpiolib_to_eint; + } } -static __init int s5pc1xx_gpiolib_init(void) +static __init int s5pc100_gpiolib_init(void) { struct s3c_gpio_chip *chip; int nr_chips; @@ -419,10 +417,10 @@ static __init int s5pc1xx_gpiolib_init(void) samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, ARRAY_SIZE(s5pc100_gpio_chips)); -#if 0 + /* Interrupt */ - set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); -#endif + set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); + return 0; } -core_initcall(s5pc1xx_gpiolib_init); +core_initcall(s5pc100_gpiolib_init); diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index e181f5789482..70e02e91ee3c 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S @@ -22,12 +22,14 @@ * aligned and add in the offset when we load the value here. */ - .macro addruart, rx, tmp + .macro addruart, rx, rtmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C_PA_UART - ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) + ldrne \rx, = S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif .endm /* include the reset of the code which will do the work, we're only diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S index 67131939e626..ba76af052c81 100644 --- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S @@ -20,7 +20,7 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =S3C_VA_VIC0 + ldr \base, =VA_VIC0 .endm .macro arch_ret_to_user, tmp1, tmp2 @@ -29,18 +29,18 @@ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp @ check the vic0 - mov \irqnr, # S3C_IRQ_OFFSET + 31 + mov \irqnr, # S5P_IRQ_OFFSET + 31 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] teq \irqstat, #0 @ otherwise try vic1 - addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) + addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) addeq \irqnr, \irqnr, #32 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] teqeq \irqstat, #0 @ otherwise try vic2 - addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) + addeq \tmp, \base, #(VA_VIC2 - VA_VIC0) addeq \irqnr, \irqnr, #32 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] teqeq \irqstat, #0 diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 29a8a12d9b4f..71ae1f52df1d 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -146,6 +146,13 @@ enum s5p_gpio_number { /* define the number of gpios we need to the one after the MP04() range */ #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) +#define EINT_MODE S3C_GPIO_SFN(0x2) + +#define EINT_GPIO_0(x) S5PC100_GPH0(x) +#define EINT_GPIO_1(x) S5PC100_GPH1(x) +#define EINT_GPIO_2(x) S5PC100_GPH2(x) +#define EINT_GPIO_3(x) S5PC100_GPH3(x) + #include <asm-generic/gpio.h> #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index b53fa48a52c6..28aa551dc3a8 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -11,9 +11,104 @@ #include <plat/irqs.h> -/* LCD */ +/* VIC0: system, DMA, timer */ +#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) +#define IRQ_BATF S5P_IRQ_VIC0(17) +#define IRQ_MDMA S5P_IRQ_VIC0(18) +#define IRQ_PDMA0 S5P_IRQ_VIC0(19) +#define IRQ_PDMA1 S5P_IRQ_VIC0(20) +#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) +#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) +#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) +#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) +#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) +#define IRQ_SYSTIMER S5P_IRQ_VIC0(26) +#define IRQ_WDT S5P_IRQ_VIC0(27) +#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) +#define IRQ_RTC_TIC S5P_IRQ_VIC0(29) +#define IRQ_GPIOINT S5P_IRQ_VIC0(30) + +/* VIC1: ARM, power, memory, connectivity */ +#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) +#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) +#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) +#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) +#define IRQ_CORTEX4 S5P_IRQ_VIC1(4) +#define IRQ_IEMAPC S5P_IRQ_VIC1(5) +#define IRQ_IEMIEC S5P_IRQ_VIC1(6) +#define IRQ_ONENAND S5P_IRQ_VIC1(7) +#define IRQ_NFC S5P_IRQ_VIC1(8) +#define IRQ_CFC S5P_IRQ_VIC1(9) +#define IRQ_UART0 S5P_IRQ_VIC1(10) +#define IRQ_UART1 S5P_IRQ_VIC1(11) +#define IRQ_UART2 S5P_IRQ_VIC1(12) +#define IRQ_UART3 S5P_IRQ_VIC1(13) +#define IRQ_IIC S5P_IRQ_VIC1(14) +#define IRQ_SPI0 S5P_IRQ_VIC1(15) +#define IRQ_SPI1 S5P_IRQ_VIC1(16) +#define IRQ_SPI2 S5P_IRQ_VIC1(17) +#define IRQ_IRDA S5P_IRQ_VIC1(18) +#define IRQ_CAN0 S5P_IRQ_VIC1(19) +#define IRQ_CAN1 S5P_IRQ_VIC1(20) +#define IRQ_HSIRX S5P_IRQ_VIC1(21) +#define IRQ_HSITX S5P_IRQ_VIC1(22) +#define IRQ_UHOST S5P_IRQ_VIC1(23) +#define IRQ_OTG S5P_IRQ_VIC1(24) +#define IRQ_MSM S5P_IRQ_VIC1(25) +#define IRQ_HSMMC0 S5P_IRQ_VIC1(26) +#define IRQ_HSMMC1 S5P_IRQ_VIC1(27) +#define IRQ_HSMMC2 S5P_IRQ_VIC1(28) +#define IRQ_MIPICSI S5P_IRQ_VIC1(29) +#define IRQ_MIPIDSI S5P_IRQ_VIC1(30) + +/* VIC2: multimedia, audio, security */ +#define IRQ_LCD0 S5P_IRQ_VIC2(0) +#define IRQ_LCD1 S5P_IRQ_VIC2(1) +#define IRQ_LCD2 S5P_IRQ_VIC2(2) +#define IRQ_LCD3 S5P_IRQ_VIC2(3) +#define IRQ_ROTATOR S5P_IRQ_VIC2(4) +#define IRQ_FIMC0 S5P_IRQ_VIC2(5) +#define IRQ_FIMC1 S5P_IRQ_VIC2(6) +#define IRQ_FIMC2 S5P_IRQ_VIC2(7) +#define IRQ_JPEG S5P_IRQ_VIC2(8) +#define IRQ_2D S5P_IRQ_VIC2(9) +#define IRQ_3D S5P_IRQ_VIC2(10) +#define IRQ_MIXER S5P_IRQ_VIC2(11) +#define IRQ_HDMI S5P_IRQ_VIC2(12) +#define IRQ_IIC1 S5P_IRQ_VIC2(13) +#define IRQ_MFC S5P_IRQ_VIC2(14) +#define IRQ_TVENC S5P_IRQ_VIC2(15) +#define IRQ_I2S0 S5P_IRQ_VIC2(16) +#define IRQ_I2S1 S5P_IRQ_VIC2(17) +#define IRQ_I2S2 S5P_IRQ_VIC2(18) +#define IRQ_AC97 S5P_IRQ_VIC2(19) +#define IRQ_PCM0 S5P_IRQ_VIC2(20) +#define IRQ_PCM1 S5P_IRQ_VIC2(21) +#define IRQ_SPDIF S5P_IRQ_VIC2(22) +#define IRQ_ADC S5P_IRQ_VIC2(23) +#define IRQ_PENDN S5P_IRQ_VIC2(24) +#define IRQ_TC IRQ_PENDN +#define IRQ_KEYPAD S5P_IRQ_VIC2(25) +#define IRQ_CG S5P_IRQ_VIC2(26) +#define IRQ_SEC S5P_IRQ_VIC2(27) +#define IRQ_SECRX S5P_IRQ_VIC2(28) +#define IRQ_SECTX S5P_IRQ_VIC2(29) +#define IRQ_SDMIRQ S5P_IRQ_VIC2(30) +#define IRQ_SDMFIQ S5P_IRQ_VIC2(31) +#define IRQ_VIC_END S5P_IRQ_VIC2(31) + +#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) +#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) + +#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) +#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) + +/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */ +#define NR_IRQS (S3C_IRQ_GPIO(320) + 1) + +/* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 #define IRQ_LCD_VSYNC IRQ_LCD1 #define IRQ_LCD_SYSTEM IRQ_LCD2 -#endif /* __ASM_ARCH_IRQ_H */ +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 4681ebe8bef6..cadae4305688 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -3,9 +3,7 @@ * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * Based on mach-s3c6400/include/mach/map.h - * - * S5PC1XX - Memory map definitions + * S5PC100 - Memory map definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,6 +14,7 @@ #define __ASM_ARCH_MAP_H __FILE__ #include <plat/map-base.h> +#include <plat/map-s5p.h> /* * map-base.h has already defined virtual memory address @@ -31,25 +30,21 @@ * */ +#define S5PC100_PA_ONENAND_BUF (0xB0000000) +#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) + /* Chip ID */ + #define S5PC100_PA_CHIPID (0xE0000000) -#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID -#define S5PC1XX_VA_CHIPID S3C_VA_SYS - -/* System */ -#define S5PC100_PA_CLK (0xE0100000) -#define S5PC100_PA_CLK_OTHER (0xE0200000) -#define S5PC100_PA_PWR (0xE0108000) -#define S5PC1XX_PA_CLK S5PC100_PA_CLK -#define S5PC1XX_PA_PWR S5PC100_PA_PWR -#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER -#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) -#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) -#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000) - -/* GPIO */ -#define S5PC100_PA_GPIO (0xE0300000) -#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO +#define S5P_PA_CHIPID S5PC100_PA_CHIPID + +#define S5PC100_PA_SYSCON (0xE0100000) +#define S5P_PA_SYSCON S5PC100_PA_SYSCON + +#define S5PC100_PA_OTHERS (0xE0200000) +#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) + +#define S5P_PA_GPIO (0xE0300000) #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) /* Interrupt */ @@ -59,6 +54,12 @@ #define S5PC100_VA_VIC_OFFSET 0x10000 #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) +#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0) +#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1) +#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2) + + +#define S5PC100_PA_ONENAND (0xE7100000) /* DMA */ #define S5PC100_PA_MDMA (0xE8100000) @@ -67,84 +68,71 @@ /* Timer */ #define S5PC100_PA_TIMER (0xEA000000) -#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER -#define S5PC1XX_VA_TIMER S3C_VA_TIMER +#define S5P_PA_TIMER S5PC100_PA_TIMER -/* RTC */ -#define S5PC100_PA_RTC (0xEA300000) +#define S5PC100_PA_SYSTIMER (0xEA100000) -/* UART */ #define S5PC100_PA_UART (0xEC000000) -#define S5PC1XX_PA_UART S5PC100_PA_UART -#define S5PC1XX_VA_UART S3C_VA_UART -/* I2C */ -#define S5PC100_PA_I2C (0xEC100000) -#define S5PC100_PA_I2C1 (0xEC200000) +#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) +#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) +#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) +#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00) +#define S5P_SZ_UART SZ_256 + +#define S5PC100_PA_IIC0 (0xEC100000) +#define S5PC100_PA_IIC1 (0xEC200000) + +/* SPI */ +#define S5PC100_PA_SPI0 0xEC300000 +#define S5PC100_PA_SPI1 0xEC400000 +#define S5PC100_PA_SPI2 0xEC500000 /* USB HS OTG */ #define S5PC100_PA_USB_HSOTG (0xED200000) #define S5PC100_PA_USB_HSPHY (0xED300000) -/* SD/MMC */ -#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) -#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0) -#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1) -#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2) - -/* LCD */ #define S5PC100_PA_FB (0xEE000000) -/* Multimedia */ -#define S5PC100_PA_G2D (0xEE800000) -#define S5PC100_PA_JPEG (0xEE500000) -#define S5PC100_PA_ROTATOR (0xEE100000) -#define S5PC100_PA_G3D (0xEF000000) - -/* I2S */ #define S5PC100_PA_I2S0 (0xF2000000) #define S5PC100_PA_I2S1 (0xF2100000) #define S5PC100_PA_I2S2 (0xF2200000) +#define S5PC100_PA_AC97 0xF2300000 + +/* PCM */ +#define S5PC100_PA_PCM0 0xF2400000 +#define S5PC100_PA_PCM1 0xF2500000 + /* KEYPAD */ #define S5PC100_PA_KEYPAD (0xF3100000) -/* ADC & TouchScreen */ -#define S5PC100_PA_TSADC (0xF3000000) +#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) -/* ETC */ #define S5PC100_PA_SDRAM (0x20000000) -#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM +#define S5P_PA_SDRAM S5PC100_PA_SDRAM -/* compatibility defines. */ -#define S3C_PA_RTC S5PC100_PA_RTC +/* compatibiltiy defines. */ #define S3C_PA_UART S5PC100_PA_UART -#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) -#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) -#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800) -#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00) -#define S3C_VA_UART0 (S3C_VA_UART + 0x0) -#define S3C_VA_UART1 (S3C_VA_UART + 0x400) -#define S3C_VA_UART2 (S3C_VA_UART + 0x800) -#define S3C_VA_UART3 (S3C_VA_UART + 0xC00) -#define S3C_UART_OFFSET 0x400 -#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) +#define S3C_PA_IIC S5PC100_PA_IIC0 +#define S3C_PA_IIC1 S5PC100_PA_IIC1 #define S3C_PA_FB S5PC100_PA_FB #define S3C_PA_G2D S5PC100_PA_G2D #define S3C_PA_G3D S5PC100_PA_G3D #define S3C_PA_JPEG S5PC100_PA_JPEG #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR -#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) -#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) -#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) -#define S3C_PA_IIC S5PC100_PA_I2C -#define S3C_PA_IIC1 S5PC100_PA_I2C1 +#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0) +#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1) +#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2) #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY -#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 -#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 -#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 +#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) +#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) +#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD #define S3C_PA_TSADC S5PC100_PA_TSADC +#define S3C_PA_ONENAND S5PC100_PA_ONENAND +#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF +#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF #endif /* __ASM_ARCH_C100_MAP_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h index f2283bdc941e..5d27d286d504 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h @@ -17,6 +17,8 @@ #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) +#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x)) + #define S5P_APLL_LOCK S5P_CLKREG(0x00) #define S5P_MPLL_LOCK S5P_CLKREG(0x04) #define S5P_EPLL_LOCK S5P_CLKREG(0x08) @@ -68,4 +70,8 @@ #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) #define S5P_CLKDIV1_PCLKD1_SHIFT (16) +#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) + +#define S5PC100_SWRESET_RESETVAL 0xc100 + #endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h index 68666913354c..dd6295e1251d 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h +/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h * * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> @@ -12,7 +12,7 @@ #include <mach/map.h> /* S5PC100 */ -#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO +#define S5PC100_GPIO_BASE S5P_VA_GPIO #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) @@ -47,24 +47,29 @@ #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) -#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00) -#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) -#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) +#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) +#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) -/* PDNEN */ -#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) -#define S5PC100_PDNEN_CFG_AUTO (0 << 1) -#define S5PC100_PDNEN_POWERDOWN (1 << 0) -#define S5PC100_PDNEN_NORMAL (0 << 0) +#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) +#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4)) -/* Common part */ -/* External interrupt base is same at both s5pc100 and s5pc110 */ -#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE) +#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00) +#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4)) -#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) -#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) -#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40) +#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4)) + +#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) + +#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) + +/* values for S5P_EXTINT0 */ +#define S5P_EXTINT_LOWLEV (0x00) +#define S5P_EXTINT_HILEV (0x01) +#define S5P_EXTINT_FALLEDGE (0x02) +#define S5P_EXTINT_RISEEDGE (0x03) +#define S5P_EXTINT_BOTHEDGE (0x04) #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h index 751ac15438c8..4d9036d0f288 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h @@ -3,7 +3,7 @@ * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * S5PC1XX - IRQ register definitions + * S5PC100 - IRQ register definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,9 +16,4 @@ #include <mach/map.h> #include <asm/hardware/vic.h> -/* interrupt controller */ -#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0)) -#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1)) -#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2)) - #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h new file mode 100644 index 000000000000..65e426370bb2 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S5PC100_PLAT_SPI_CLKS_H +#define __S5PC100_PLAT_SPI_CLKS_H __FILE__ + +#define S5PC100_SPI_SRCCLK_PCLK 0 +#define S5PC100_SPI_SRCCLK_48M 1 +#define S5PC100_SPI_SRCCLK_SPIBUS 2 + +#endif /* __S5PC100_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index f0d31a2a598c..681f626a9ae1 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h @@ -3,7 +3,7 @@ * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * S5PC1XX - system implementation + * S5PC100 - system implementation * * Based on mach-s3c6400/include/mach/system.h */ @@ -13,14 +13,11 @@ #include <linux/io.h> #include <mach/map.h> -#include <plat/regs-clock.h> - -void (*s5pc1xx_idle)(void); +#include <mach/regs-clock.h> static void arch_idle(void) { - if (s5pc1xx_idle) - s5pc1xx_idle(); + /* nothing here yet */ } static void arch_reset(char mode, const char *cmd) diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index f338c9eec717..20f68730ed18 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h @@ -20,8 +20,8 @@ */ static inline u32 s3c24xx_ostimer_pending(void) { - u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); - return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); } #define TICK_MAX (0xffffffff) diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/mach-s5pc100/init.c index c58710884ceb..19d7b523c137 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-init.c +++ b/arch/arm/mach-s5pc100/init.c @@ -1,9 +1,8 @@ -/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c +/* linux/arch/arm/plat-s5pc100/s5pc100-init.c * * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * - * S5PC100 - CPU initialisation (common with other S5PC1XX chips) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,9 +18,7 @@ #include <plat/s5pc100.h> /* uart registration process */ - void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) { - /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv */ - s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no); + s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); } diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c index fecca7a679b0..2bf86c18bc73 100644 --- a/arch/arm/plat-s5pc1xx/irq-gpio.c +++ b/arch/arm/mach-s5pc100/irq-gpio.c @@ -1,9 +1,9 @@ /* - * arch/arm/plat-s5pc1xx/irq-gpio.c + * arch/arm/mach-s5pc100/irq-gpio.c * * Copyright (C) 2009 Samsung Electronics * - * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) + * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,7 +19,7 @@ #include <mach/map.h> #include <plat/gpio-cfg.h> -#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) +#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) #define CON_OFFSET 0x700 #define MASK_OFFSET 0x900 @@ -49,7 +49,7 @@ static int group_to_pend_offset(int group) return group << 2; } -static int s5pc1xx_get_start(unsigned int group) +static int s5pc100_get_start(unsigned int group) { switch (group) { case 0: return S5PC100_GPIO_A0_START; @@ -80,7 +80,7 @@ static int s5pc1xx_get_start(unsigned int group) return -EINVAL; } -static int s5pc1xx_get_group(unsigned int irq) +static int s5pc100_get_group(unsigned int irq) { irq -= S3C_IRQ_GPIO(0); @@ -134,67 +134,67 @@ static int s5pc1xx_get_group(unsigned int irq) return -EINVAL; } -static int s5pc1xx_get_offset(unsigned int irq) +static int s5pc100_get_offset(unsigned int irq) { struct gpio_chip *chip = get_irq_data(irq); return irq - S3C_IRQ_GPIO(chip->base); } -static void s5pc1xx_gpioint_ack(unsigned int irq) +static void s5pc100_gpioint_ack(unsigned int irq) { int group, offset, pend_offset; unsigned int value; - group = s5pc1xx_get_group(irq); - offset = s5pc1xx_get_offset(irq); + group = s5pc100_get_group(irq); + offset = s5pc100_get_offset(irq); pend_offset = group_to_pend_offset(group); - value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); + value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); value |= 1 << offset; - __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); + __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset); } -static void s5pc1xx_gpioint_mask(unsigned int irq) +static void s5pc100_gpioint_mask(unsigned int irq) { int group, offset, mask_offset; unsigned int value; - group = s5pc1xx_get_group(irq); - offset = s5pc1xx_get_offset(irq); + group = s5pc100_get_group(irq); + offset = s5pc100_get_offset(irq); mask_offset = group_to_mask_offset(group); - value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); value |= 1 << offset; - __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); } -static void s5pc1xx_gpioint_unmask(unsigned int irq) +static void s5pc100_gpioint_unmask(unsigned int irq) { int group, offset, mask_offset; unsigned int value; - group = s5pc1xx_get_group(irq); - offset = s5pc1xx_get_offset(irq); + group = s5pc100_get_group(irq); + offset = s5pc100_get_offset(irq); mask_offset = group_to_mask_offset(group); - value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); value &= ~(1 << offset); - __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); } -static void s5pc1xx_gpioint_mask_ack(unsigned int irq) +static void s5pc100_gpioint_mask_ack(unsigned int irq) { - s5pc1xx_gpioint_mask(irq); - s5pc1xx_gpioint_ack(irq); + s5pc100_gpioint_mask(irq); + s5pc100_gpioint_ack(irq); } -static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) +static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type) { int group, offset, con_offset; unsigned int value; - group = s5pc1xx_get_group(irq); - offset = s5pc1xx_get_offset(irq); + group = s5pc100_get_group(irq); + offset = s5pc100_get_offset(irq); con_offset = group_to_con_offset(group); switch (type) { @@ -221,24 +221,24 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) } - value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); + value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset); value &= ~(0xf << (offset * 0x4)); value |= (type << (offset * 0x4)); - __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); + __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset); return 0; } -struct irq_chip s5pc1xx_gpioint = { +struct irq_chip s5pc100_gpioint = { .name = "GPIO", - .ack = s5pc1xx_gpioint_ack, - .mask = s5pc1xx_gpioint_mask, - .mask_ack = s5pc1xx_gpioint_mask_ack, - .unmask = s5pc1xx_gpioint_unmask, - .set_type = s5pc1xx_gpioint_set_type, + .ack = s5pc100_gpioint_ack, + .mask = s5pc100_gpioint_mask, + .mask_ack = s5pc100_gpioint_mask_ack, + .unmask = s5pc100_gpioint_unmask, + .set_type = s5pc100_gpioint_set_type, }; -void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) +void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) { int group, offset, pend_offset, mask_offset; int real_irq, group_end; @@ -248,17 +248,17 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) for (group = 0; group < group_end; group++) { pend_offset = group_to_pend_offset(group); - pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); + pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); if (!pend) continue; mask_offset = group_to_mask_offset(group); - mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); pend &= ~mask; for (offset = 0; offset < 8; offset++) { if (pend & (1 << offset)) { - real_irq = s5pc1xx_get_start(group) + offset; + real_irq = s5pc100_get_start(group) + offset; generic_handle_irq(S3C_IRQ_GPIO(real_irq)); } } diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index bfe67db34f04..af22f8202a07 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -43,38 +43,48 @@ #include <plat/fb.h> #include <plat/iic.h> -#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) -#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) -#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S3C2440_UFCON_RXTRIG8 | \ + S3C2440_UFCON_TXTRIG16) static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, + .ucon = S5PC100_UCON_DEFAULT, + .ulcon = S5PC100_ULCON_DEFAULT, + .ufcon = S5PC100_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, + .ucon = S5PC100_UCON_DEFAULT, + .ulcon = S5PC100_ULCON_DEFAULT, + .ufcon = S5PC100_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, + .ucon = S5PC100_UCON_DEFAULT, + .ulcon = S5PC100_ULCON_DEFAULT, + .ufcon = S5PC100_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, + .ucon = S5PC100_UCON_DEFAULT, + .ulcon = S5PC100_ULCON_DEFAULT, + .ufcon = S5PC100_UFCON_DEFAULT, }, }; @@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = { static struct s3c_fb_pd_win smdkc100_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { - .refresh = 70, - .pixclock = (8+13+3+800)*(7+5+1+480), + .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80), .left_margin = 8, .right_margin = 13, .upper_margin = 7, @@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { .setup_gpio = s5pc100_fb_gpio_setup_24bpp, }; -static struct map_desc smdkc100_iodesc[] = {}; - static struct platform_device *smdkc100_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, @@ -150,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = { &s3c_device_hsmmc1, &s3c_device_hsmmc2, &smdkc100_lcd_powerdev, + &s5pc100_device_iis0, + &s5pc100_device_ac97, }; static void __init smdkc100_map_io(void) { - s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); + s5p_init_io(NULL, 0, S5P_VA_CHIPID); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); } @@ -178,10 +187,9 @@ static void __init smdkc100_machine_init(void) MACHINE_START(SMDKC100, "SMDKC100") /* Maintainer: Byungho Min <bhmin@samsung.com> */ - .phys_io = S5PC100_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S5PC100_PA_SDRAM + 0x100, - + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = s5pc100_init_irq, .map_io = smdkc100_map_io, .init_machine = smdkc100_machine_init, diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c index 185c8941e644..7769c760c9ef 100644 --- a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c @@ -1,8 +1,8 @@ -/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c +/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c * * Copyright 2009 Samsung Eletronics * - * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 7601c28e240b..0761eac9aaea 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -13,18 +13,68 @@ config CPU_S5PV210 bool select PLAT_S5P select S3C_PL330_DMA + select S5P_EXT_INT help Enable S5PV210 CPU support -choice - prompt "Select machine type" - depends on ARCH_S5PV210 - default MACH_SMDKV210 +config S5PV210_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + +config S5PV210_SETUP_I2C2 + bool + help + Common setup code for i2c bus 2. + +config S5PV210_SETUP_FB_24BPP + bool + help + Common setup code for S5PV210 with an 24bpp RGB display helper. + +config S5PV210_SETUP_SDHCI + bool + select S5PV210_SETUP_SDHCI_GPIO + help + Internal helper functions for S5PV210 based SDHCI systems + +config S5PV210_SETUP_SDHCI_GPIO + bool + help + Common setup code for SDHCI gpio. + +# machine support + +config MACH_AQUILA + bool "Samsung Aquila" + select CPU_S5PV210 + select ARCH_SPARSEMEM_ENABLE + select S5PV210_SETUP_FB_24BPP + select S3C_DEV_FB + help + Machine support for the Samsung Aquila target based on S5PC110 SoC + +config MACH_GONI + bool "GONI" + select CPU_S5PV210 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung GONI board + S5PC110(MCP) is one of package option of S5PV210 + +config S5PC110_DEV_ONENAND + bool + help + Compile in platform device definition for OneNAND1 controller config MACH_SMDKV210 bool "SMDKV210" select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_TS + select S3C_DEV_WDT + select HAVE_S3C2410_WATCHDOG help Machine support for Samsung SMDKV210 @@ -32,10 +82,10 @@ config MACH_SMDKC110 bool "SMDKC110" select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_WDT + select HAVE_S3C2410_WATCHDOG help Machine support for Samsung SMDKC110 S5PC110(MCP) is one of package option of S5PV210 -endchoice - endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 99827813d293..30be9a6a4620 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -17,9 +17,19 @@ obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o # machine support +obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o +obj-$(CONFIG_MACH_GONI) += mach-goni.o # device support obj-y += dev-audio.o +obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o +obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o + +obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o +obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o +obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 2b776eb5d150..411a4a9cbfc7 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -32,6 +32,8 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/s5pv210.h> +#include <plat/iic-core.h> +#include <plat/sdhci.h> /* Initial IO mappings */ @@ -74,7 +76,21 @@ static void s5pv210_idle(void) void __init s5pv210_map_io(void) { +#ifdef CONFIG_S3C_DEV_ADC + s3c_device_adc.name = "s3c64xx-adc"; +#endif + iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); + + /* initialise device information early */ + s5pv210_default_sdhci0(); + s5pv210_default_sdhci1(); + s5pv210_default_sdhci2(); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); + s3c_i2c1_setname("s3c2440-i2c"); + s3c_i2c2_setname("s3c2440-i2c"); } void __init s5pv210_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/mach-s5pv210/dev-onenand.c new file mode 100644 index 000000000000..34997b752f93 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-onenand.c @@ -0,0 +1,50 @@ +/* + * linux/arch/arm/mach-s5pv210/dev-onenand.c + * + * Copyright (c) 2008-2010 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * + * S5PC110 series device definition for OneNAND devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +static struct resource s5pc110_onenand_resources[] = { + [0] = { + .start = S5PC110_PA_ONENAND, + .end = S5PC110_PA_ONENAND + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S5PC110_PA_ONENAND_DMA, + .end = S5PC110_PA_ONENAND_DMA + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s5pc110_device_onenand = { + .name = "s5pc110-onenand", + .id = -1, + .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), + .resource = s5pc110_onenand_resources, +}; + +void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) +{ + struct onenand_platform_data *pd; + + pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); + if (!pd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + s5pc110_device_onenand.dev.platform_data = pd; +} diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c new file mode 100644 index 000000000000..337a62b57a0b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-spi.c @@ -0,0 +1,178 @@ +/* linux/arch/arm/mach-s5pv210/dev-spi.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <mach/spi-clocks.h> + +#include <plat/s3c64xx-spi.h> +#include <plat/gpio-cfg.h> + +static char *spi_src_clks[] = { + [S5PV210_SPI_SRCCLK_PCLK] = "pclk", + [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the CS. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s5pv210_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP); + break; + + case 1: + s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s5pv210_spi0_resource[] = { + [0] = { + .start = S5PV210_PA_SPI0, + .end = S5PV210_PA_SPI0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5pv210_spi0_pdata = { + .cfg_gpio = s5pv210_spi_cfg_gpio, + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, + .high_speed = 1, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pv210_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s5pv210_spi0_resource), + .resource = s5pv210_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_spi0_pdata, + }, +}; + +static struct resource s5pv210_spi1_resource[] = { + [0] = { + .start = S5PV210_PA_SPI1, + .end = S5PV210_PA_SPI1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI1_TX, + .end = DMACH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI1_RX, + .end = DMACH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s5pv210_spi1_pdata = { + .cfg_gpio = s5pv210_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, + .high_speed = 1, +}; + +struct platform_device s5pv210_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_spi1_resource), + .resource = s5pv210_spi1_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_spi1_pdata, + }, +}; + +void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s5pv210_spi0_pdata; + break; + case 1: + pd = &s5pv210_spi1_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 62c5175ef291..96895378ea27 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -17,22 +17,6 @@ /* VIC0: System, DMA, Timer */ -#define IRQ_EINT0 S5P_IRQ_VIC0(0) -#define IRQ_EINT1 S5P_IRQ_VIC0(1) -#define IRQ_EINT2 S5P_IRQ_VIC0(2) -#define IRQ_EINT3 S5P_IRQ_VIC0(3) -#define IRQ_EINT4 S5P_IRQ_VIC0(4) -#define IRQ_EINT5 S5P_IRQ_VIC0(5) -#define IRQ_EINT6 S5P_IRQ_VIC0(6) -#define IRQ_EINT7 S5P_IRQ_VIC0(7) -#define IRQ_EINT8 S5P_IRQ_VIC0(8) -#define IRQ_EINT9 S5P_IRQ_VIC0(9) -#define IRQ_EINT10 S5P_IRQ_VIC0(10) -#define IRQ_EINT11 S5P_IRQ_VIC0(11) -#define IRQ_EINT12 S5P_IRQ_VIC0(12) -#define IRQ_EINT13 S5P_IRQ_VIC0(13) -#define IRQ_EINT14 S5P_IRQ_VIC0(14) -#define IRQ_EINT15 S5P_IRQ_VIC0(15) #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) #define IRQ_BATF S5P_IRQ_VIC0(17) #define IRQ_MDMA S5P_IRQ_VIC0(18) @@ -134,13 +118,15 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) -#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) - -#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) -#define IRQ_EINT(x) S5P_EINT(x) +#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) +#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) /* Set the default NR_IRQS */ +#define NR_IRQS (IRQ_EINT(31) + 1) -#define NR_IRQS (IRQ_EINT(31) + 1) +/* Compatibility */ +#define IRQ_LCD_FIFO IRQ_LCD0 +#define IRQ_LCD_VSYNC IRQ_LCD1 +#define IRQ_LCD_SYSTEM IRQ_LCD2 #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 5adcb9f26e44..34eb168ec950 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,6 +16,9 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> +#define S5PC110_PA_ONENAND (0xB0000000) +#define S5PC110_PA_ONENAND_DMA (0xB0600000) + #define S5PV210_PA_CHIPID (0xE0000000) #define S5P_PA_CHIPID S5PV210_PA_CHIPID @@ -25,13 +28,21 @@ #define S5PV210_PA_GPIO (0xE0200000) #define S5P_PA_GPIO S5PV210_PA_GPIO +/* SPI */ +#define S5PV210_PA_SPI0 0xE1300000 +#define S5PV210_PA_SPI1 0xE1400000 + #define S5PV210_PA_IIC0 (0xE1800000) +#define S5PV210_PA_IIC1 (0xFAB00000) +#define S5PV210_PA_IIC2 (0xE1A00000) #define S5PV210_PA_TIMER (0xE2500000) #define S5P_PA_TIMER S5PV210_PA_TIMER #define S5PV210_PA_SYSTIMER (0xE2600000) +#define S5PV210_PA_WATCHDOG (0xE2700000) + #define S5PV210_PA_UART (0xE2900000) #define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) @@ -47,6 +58,10 @@ #define S5PV210_PA_PDMA0 0xE0900000 #define S5PV210_PA_PDMA1 0xE0A00000 +#define S5PV210_PA_FB (0xF8000000) + +#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) + #define S5PV210_PA_VIC0 (0xF2000000) #define S5P_PA_VIC0 S5PV210_PA_VIC0 @@ -75,8 +90,19 @@ /* AC97 */ #define S5PV210_PA_AC97 0xE2200000 +#define S5PV210_PA_ADC (0xE1700000) + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV210_PA_UART +#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) +#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) +#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) #define S3C_PA_IIC S5PV210_PA_IIC0 +#define S3C_PA_IIC1 S5PV210_PA_IIC1 +#define S3C_PA_IIC2 S5PV210_PA_IIC2 +#define S3C_PA_FB S5PV210_PA_FB +#define S3C_PA_WDT S5PV210_PA_WATCHDOG + +#define SAMSUNG_PA_ADC S5PV210_PA_ADC #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index e56e0e4673ed..2a25ab40c863 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -126,6 +126,7 @@ #define S5P_RST_STAT S5P_CLKREG(0xA000) #define S5P_OSC_CON S5P_CLKREG(0x8000) +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) #define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h new file mode 100644 index 000000000000..60d992989bdc --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-fb.h @@ -0,0 +1,21 @@ +/* + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * Dummy framebuffer to allow build for the moment. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MACH_REGS_FB_H +#define __ASM_ARCH_MACH_REGS_FB_H __FILE__ + +#include <plat/regs-fb-v4.h> + +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) +{ + return 0x2400 + (window * 256 *4 ) + reg; +} + +#endif /* __ASM_ARCH_MACH_REGS_FB_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h new file mode 100644 index 000000000000..49e029b4978a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -0,0 +1,48 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV210 - GPIO (including EINT) register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +#include <mach/map.h> + +#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) +#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) + +#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) +#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) + +#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) +#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) + +#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40) +#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4)) + +#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) + +#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) + +/* values for S5P_EXTINT0 */ +#define S5P_EXTINT_LOWLEV (0x00) +#define S5P_EXTINT_HILEV (0x01) +#define S5P_EXTINT_FALLEDGE (0x02) +#define S5P_EXTINT_RISEEDGE (0x03) +#define S5P_EXTINT_BOTHEDGE (0x04) + +#define EINT_MODE S3C_GPIO_SFN(0xf) + +#define EINT_GPIO_0(x) S5PV210_GPH0(x) +#define EINT_GPIO_1(x) S5PV210_GPH1(x) +#define EINT_GPIO_2(x) S5PV210_GPH2(x) +#define EINT_GPIO_3(x) S5PV210_GPH3(x) + +#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h new file mode 100644 index 000000000000..02acded5f73d --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h @@ -0,0 +1,17 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S5PV210_PLAT_SPI_CLKS_H +#define __S5PV210_PLAT_SPI_CLKS_H __FILE__ + +#define S5PV210_SPI_SRCCLK_PCLK 0 +#define S5PV210_SPI_SRCCLK_SCLK 1 + +#endif /* __S5PV210_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c new file mode 100644 index 000000000000..10bc76ec4025 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -0,0 +1,149 @@ +/* linux/arch/arm/mach-s5pv210/mach-aquila.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/fb.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/regs-fb.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/fb.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +/* Frame Buffer */ +static struct s3c_fb_pd_win aquila_fb_win0 = { + .win_mode = { + .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), + .left_margin = 16, + .right_margin = 16, + .upper_margin = 3, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_pd_win aquila_fb_win1 = { + .win_mode = { + .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), + .left_margin = 16, + .right_margin = 16, + .upper_margin = 3, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_platdata aquila_lcd_pdata __initdata = { + .win[0] = &aquila_fb_win0, + .win[1] = &aquila_fb_win1, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK | VIDCON1_INV_VDEN, + .setup_gpio = s5pv210_fb_gpio_setup_24bpp, +}; + +static struct platform_device *aquila_devices[] __initdata = { + &s3c_device_fb, +}; + +static void __init aquila_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); +} + +static void __init aquila_machine_init(void) +{ + /* FB */ + s3c_fb_set_platdata(&aquila_lcd_pdata); + + platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices)); +} + +MACHINE_START(AQUILA, "Aquila") + /* Maintainers: + Marek Szyprowski <m.szyprowski@samsung.com> + Kyungmin Park <kyungmin.park@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv210_init_irq, + .map_io = aquila_map_io, + .init_machine = aquila_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c new file mode 100644 index 000000000000..4863b13824e4 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -0,0 +1,98 @@ +/* linux/arch/arm/mach-s5pv210/mach-goni.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +static struct platform_device *goni_devices[] __initdata = { +}; + +static void __init goni_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs)); +} + +static void __init goni_machine_init(void) +{ + platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices)); +} + +MACHINE_START(GONI, "GONI") + /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv210_init_irq, + .map_io = goni_map_io, + .init_machine = goni_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 6f9fd3274e2e..4c8903c6d104 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -74,6 +74,7 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { static struct platform_device *smdkc110_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, + &s3c_device_wdt, }; static void __init smdkc110_map_io(void) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 3c29e18528a5..0d4627948040 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -25,6 +25,8 @@ #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/adc.h> +#include <plat/ts.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -74,6 +76,15 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { static struct platform_device *smdkv210_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, + &s3c_device_adc, + &s3c_device_ts, + &s3c_device_wdt, +}; + +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, }; static void __init smdkv210_map_io(void) @@ -85,6 +96,7 @@ static void __init smdkv210_map_io(void) static void __init smdkv210_machine_init(void) { + s3c24xx_ts_set_platdata(&s3c_ts_platform); platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); } diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c new file mode 100644 index 000000000000..a50cbac8720d --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c @@ -0,0 +1,62 @@ +/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base s5pv210 setup information for 24bpp LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/fb.h> + +#include <mach/regs-fb.h> +#include <mach/gpio.h> +#include <mach/map.h> +#include <plat/fb.h> +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +void s5pv210_fb_gpio_setup_24bpp(void) +{ + unsigned int gpio = 0; + + for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + /* Set DISPLAY_CONTROL register for Display path selection. + * + * ouput | RGB | I80 | ITU + * ----------------------------------- + * 00 | MIE | FIMD | FIMD + * 01 | MDNIE | MDNIE | FIMD + * 10 | FIMD | FIMD | FIMD + * 11 | FIMD | FIMD | FIMD + */ + writel(0x2, S5P_MDNIE_SEL); +} diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index 9ec6845840e5..c718253c70b8 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s5pv210/setup-i2c0.c * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * * I2C0 GPIO configuration. @@ -17,9 +17,14 @@ struct platform_device; /* don't need the contents */ +#include <mach/gpio.h> #include <plat/iic.h> +#include <plat/gpio-cfg.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - /* Will be populated later */ + s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c new file mode 100644 index 000000000000..45e0e6ed2ed0 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c1.c @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-s5pv210/setup-i2c1.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C1 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c1.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c new file mode 100644 index 000000000000..b11b4bff69ac --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c2.c @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-s5pv210/setup-i2c2.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C2 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c new file mode 100644 index 000000000000..fe7d86dad14c --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -0,0 +1,104 @@ +/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/mmc/card.h> + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-sdhci.h> + +void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + + /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ + for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + switch (width) { + case 8: + /* GPG1[3:6] special-funtion 3 */ + for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + case 4: + /* GPG0[3:6] special-funtion 2 */ + for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + default: + break; + } + + s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); +} + +void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + + /* Set all the necessary GPG1[0:1] pins to special-function 2 */ + for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Data pin GPG1[3:6] to special-function 2 */ + for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); +} + +void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + + /* Set all the necessary GPG2[0:1] pins to special-function 2 */ + for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + switch (width) { + case 8: + /* Data pin GPG3[3:6] to special-function 3 */ + for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + case 4: + /* Data pin GPG2[3:6] to special-function 2 */ + for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + default: + break; + } + + s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); +} diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c new file mode 100644 index 000000000000..51815ec60c2a --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -0,0 +1,63 @@ +/* linux/arch/arm/mach-s5pv210/setup-sdhci.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <linux/mmc/card.h> +#include <linux/mmc/host.h> + +#include <plat/regs-sdhci.h> +#include <plat/sdhci.h> + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s5pv210_hsmmc_clksrcs[4] = { + [0] = "hsmmc", /* HCLK */ + [1] = "hsmmc", /* HCLK */ + [2] = "sclk_mmc", /* mmc_bus */ + /*[4] = reserved */ +}; + +void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + /* don't need to alter anything acording to card-type */ + + writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c index 4cf7c565aaed..bbfe197fb4d6 100644 --- a/arch/arm/mach-sa1100/leds.c +++ b/arch/arm/mach-sa1100/leds.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-sa1100/leds.c * * SA1100 LEDs dispatcher - * + * * Copyright (C) 2001 Nicolas Pitre */ #include <linux/compiler.h> @@ -18,10 +18,10 @@ sa1100_leds_init(void) { if (machine_is_assabet()) leds_event = assabet_leds_event; - if (machine_is_consus()) - leds_event = consus_leds_event; + if (machine_is_consus()) + leds_event = consus_leds_event; if (machine_is_badge4()) - leds_event = badge4_leds_event; + leds_event = badge4_leds_event; if (machine_is_brutus()) leds_event = brutus_leds_event; if (machine_is_cerf()) diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 37a7112d4117..89d175ce74d2 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -16,16 +16,19 @@ static int __init shark_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (dev->bus->number == 0) - if (dev->devfn == 0) return 255; - else return 11; - else return 255; + if (dev->devfn == 0) + return 255; + else + return 11; + else + return 255; } extern void __init via82c505_preinit(void); static struct hw_pci shark_pci __initdata = { .setup = via82c505_setup, - .swizzle = pci_std_swizzle, + .swizzle = pci_std_swizzle, .map_irq = shark_map_irq, .nr_controllers = 1, .scan = via82c505_scan_bus, diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index b67e571d4bf7..baf6bcc3169c 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -13,7 +13,6 @@ #include <linux/types.h> #include <linux/amba/pl061.h> -#include <linux/types.h> #include <linux/ptrace.h> #include <linux/io.h> #include <asm/hardware/vic.h> diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index c73ed06b6065..f0394baa11fa 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -9,7 +9,7 @@ */ #include <linux/kernel.h> #include <linux/i2c.h> -#include <linux/mfd/ab3100.h> +#include <linux/mfd/abx500.h> #include <linux/regulator/machine.h> #include <linux/amba/bus.h> #include <mach/irqs.h> @@ -46,6 +46,7 @@ /* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */ #define BUCK_SLEEP_SETTING 0xAC +#ifdef CONFIG_AB3100_CORE static struct regulator_consumer_supply supply_ldo_c[] = { { .dev_name = "ab3100-codec", @@ -253,14 +254,68 @@ static struct ab3100_platform_data ab3100_plf_data = { LDO_D_SETTING, }, }; +#endif + +#ifdef CONFIG_AB3550_CORE +static struct abx500_init_settings ab3550_init_settings[] = { + { + .bank = 0, + .reg = AB3550_IMR1, + .setting = 0xff + }, + { + .bank = 0, + .reg = AB3550_IMR2, + .setting = 0xff + }, + { + .bank = 0, + .reg = AB3550_IMR3, + .setting = 0xff + }, + { + .bank = 0, + .reg = AB3550_IMR4, + .setting = 0xff + }, + { + .bank = 0, + .reg = AB3550_IMR5, + /* The two most significant bits are not used */ + .setting = 0x3f + }, +}; + +static struct ab3550_platform_data ab3550_plf_data = { + .irq = { + .base = IRQ_AB3550_BASE, + .count = (IRQ_AB3550_END - IRQ_AB3550_BASE + 1), + }, + .dev_data = { + }, + .init_settings = ab3550_init_settings, + .init_settings_sz = ARRAY_SIZE(ab3550_init_settings), +}; +#endif static struct i2c_board_info __initdata bus0_i2c_board_info[] = { +#if defined(CONFIG_AB3550_CORE) + { + .type = "ab3550", + .addr = 0x4A, + .irq = IRQ_U300_IRQ0_EXT, + .platform_data = &ab3550_plf_data, + }, +#elif defined(CONFIG_AB3100_CORE) { .type = "ab3100", .addr = 0x48, .irq = IRQ_U300_IRQ0_EXT, .platform_data = &ab3100_plf_data, }, +#else + { }, +#endif }; static struct i2c_board_info __initdata bus1_i2c_board_info[] = { diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h index b8155b4e5ffa..193da2df732c 100644 --- a/arch/arm/mach-u300/include/mach/coh901318.h +++ b/arch/arm/mach-u300/include/mach/coh901318.h @@ -103,27 +103,6 @@ struct coh901318_platform { }; /** - * coh901318_get_bytes_left() - Get number of bytes left on a current transfer - * @chan: dma channel handle - * return number of bytes left, or negative on error - */ -u32 coh901318_get_bytes_left(struct dma_chan *chan); - -/** - * coh901318_stop() - Stops dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_stop(struct dma_chan *chan); - -/** - * coh901318_continue() - Resumes a stopped dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_continue(struct dma_chan *chan); - -/** * coh901318_filter_id() - DMA channel filter function * @chan: dma channel handle * @chan_id: id of dma channel to be filter out diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index a6867b12773e..09b1b28fa8fd 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -109,6 +109,13 @@ #define U300_NR_IRQS 48 #endif +#ifdef CONFIG_AB3550_CORE +#define IRQ_AB3550_BASE (U300_NR_IRQS) +#define IRQ_AB3550_END (IRQ_AB3550_BASE + 37) + +#define NR_IRQS (IRQ_AB3550_END + 1) +#else #define NR_IRQS U300_NR_IRQS +#endif #endif diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index c7bc4199e3a8..4556aea9c3c5 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o obj-$(CONFIG_MACH_U5500) += board-u5500.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 072196c57263..bb8d7b771817 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -50,7 +50,7 @@ struct pl022_config_chip ab4500_chip_info = { static struct spi_board_info u8500_spi_devices[] = { { - .modalias = "ab4500", + .modalias = "ab8500", .controller_data = &ab4500_chip_info, .max_speed_hz = 12000000, .bus_num = 0, diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 1b2c9890e8b4..fe84b9021c7a 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -16,6 +16,7 @@ #include <asm/clkdev.h> +#include <plat/mtu.h> #include <mach/hardware.h> #include "clock.h" @@ -59,6 +60,9 @@ #define PRCM_DMACLK_MGT 0x074 #define PRCM_B2R2CLK_MGT 0x078 #define PRCM_TVCLK_MGT 0x07C +#define PRCM_TCR 0x1C8 +#define PRCM_TCR_STOPPED (1 << 16) +#define PRCM_TCR_DOZE_MODE (1 << 17) #define PRCM_UNIPROCLK_MGT 0x278 #define PRCM_SSPCLK_MGT 0x280 #define PRCM_RNGCLK_MGT 0x284 @@ -120,10 +124,95 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); +/* + * The MTU has a separate, rather complex muxing setup + * with alternative parents (peripheral cluster or + * ULP or fixed 32768 Hz) depending on settings + */ +static unsigned long clk_mtu_get_rate(struct clk *clk) +{ + void __iomem *addr = __io_address(U8500_PRCMU_BASE) + + PRCM_TCR; + u32 tcr = readl(addr); + int mtu = (int) clk->data; + /* + * One of these is selected eventually + * TODO: Replace the constant with a reference + * to the ULP source once this is modeled. + */ + unsigned long clk32k = 32768; + unsigned long mturate; + unsigned long retclk; + + /* Get the rate from the parent as a default */ + if (clk->parent_periph) + mturate = clk_get_rate(clk->parent_periph); + else if (clk->parent_cluster) + mturate = clk_get_rate(clk->parent_cluster); + else + /* We need to be connected SOMEWHERE */ + BUG(); + + /* + * Are we in doze mode? + * In this mode the parent peripheral or the fixed 32768 Hz + * clock is fed into the block. + */ + if (!(tcr & PRCM_TCR_DOZE_MODE)) { + /* + * Here we're using the clock input from the APE ULP + * clock domain. But first: are the timers stopped? + */ + if (tcr & PRCM_TCR_STOPPED) { + clk32k = 0; + mturate = 0; + } else { + /* Else default mode: 0 and 2.4 MHz */ + clk32k = 0; + if (cpu_is_u5500()) + /* DB5500 divides by 8 */ + mturate /= 8; + else if (cpu_is_u8500ed()) { + /* + * This clocking setting must not be used + * in the ED chip, it is simply not + * connected anywhere! + */ + mturate = 0; + BUG(); + } else + /* + * In this mode the ulp38m4 clock is divided + * by a factor 16, on the DB8500 typically + * 38400000 / 16 ~ 2.4 MHz. + * TODO: Replace the constant with a reference + * to the ULP source once this is modeled. + */ + mturate = 38400000 / 16; + } + } + + /* Return the clock selected for this MTU */ + if (tcr & (1 << mtu)) + retclk = clk32k; + else + retclk = mturate; + + pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); + return retclk; +} + unsigned long clk_get_rate(struct clk *clk) { unsigned long rate; + /* + * If there is a custom getrate callback for this clock, + * it will take precedence. + */ + if (clk->get_rate) + return clk->get_rate(clk); + if (clk->ops && clk->ops->get_rate) return clk->ops->get_rate(clk); @@ -341,8 +430,9 @@ static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); /* Peripheral Cluster #6 */ -static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL); -static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL); +/* MTU ID in data */ +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); @@ -357,8 +447,9 @@ static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); /* Peripheral Cluster #7 */ static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); -static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL); -static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL); +/* MTU ID in data */ +static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); @@ -411,7 +502,7 @@ static struct clk_lookup u8500_common_clks[] = { CLK(apetraceclk, "apetrace", NULL), CLK(mcdeclk, "mcde", NULL), CLK(ipi2clk, "ipi2", NULL), - CLK(dmaclk, "dma40", NULL), + CLK(dmaclk, "dma40.0", NULL), CLK(b2r2clk, "b2r2", NULL), CLK(tvclk, "tv", NULL), }; @@ -503,15 +594,17 @@ static struct clk_lookup u8500_v1_clks[] = { CLK(uiccclk, "uicc", NULL), }; -static int __init clk_init(void) +int __init clk_init(void) { if (cpu_is_u8500ed()) { clk_prcmu_ops.enable = clk_prcmu_ed_enable; clk_prcmu_ops.disable = clk_prcmu_ed_disable; + clk_per6clk.rate = 100000000; } else if (cpu_is_u5500()) { /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; + clk_per6clk.rate = 26000000; } clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); @@ -522,4 +615,3 @@ static int __init clk_init(void) return 0; } -arch_initcall(clk_init); diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h index e4f99b65026f..a05802501527 100644 --- a/arch/arm/mach-ux500/clock.h +++ b/arch/arm/mach-ux500/clock.h @@ -28,6 +28,9 @@ struct clkops { * @ops: pointer to clkops struct used to control this clock * @name: name, for debugging * @enabled: refcount. positive if enabled, zero if disabled + * @get_rate: custom callback for getting the clock rate + * @data: custom per-clock data for example for the get_rate + * callback * @rate: fixed rate for clocks which don't implement * ops->getrate * @prcmu_cg_off: address offset of the combined enable/disable register @@ -67,6 +70,8 @@ struct clk { const struct clkops *ops; const char *name; unsigned int enabled; + unsigned long (*get_rate)(struct clk *); + void *data; unsigned long rate; struct list_head list; @@ -117,9 +122,26 @@ struct clk clk_##_name = { \ .parent_periph = _kernclk \ } +#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcc_ops, \ + .cluster = _pclust, \ + .prcc_bus = _bus_en, \ + .prcc_kernel = _kernel_en, \ + .parent_cluster = &clk_per##_pclust##clk, \ + .parent_periph = _kernclk, \ + .get_rate = _callback, \ + .data = (void *) _data \ + } + + #define CLK(_clk, _devname, _conname) \ { \ .clk = &clk_##_clk, \ .dev_id = _devname, \ .con_id = _conname, \ } + +int __init clk_db8500_ed_fixup(void); +int __init clk_init(void); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index d04299f3b6b5..f21c444edd99 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -32,6 +32,7 @@ static struct platform_device *platform_devs[] __initdata = { &u8500_gpio_devs[6], &u8500_gpio_devs[7], &u8500_gpio_devs[8], + &u8500_dma40_device, }; /* minimum static i/o mapping required to boot U8500 platforms */ @@ -71,6 +72,9 @@ void __init u8500_init_devices(void) { ux500_init_devices(); + if (cpu_is_u8500ed()) + dma40_u8500ed_fixup(); + /* Register the platform devices */ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index d81ad023963c..e0fd747e447a 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -62,6 +62,12 @@ void __init ux500_init_irq(void) { gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29); gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); + + /* + * Init clocks here so that they are available for system timer + * initialization. + */ + clk_init(); } #ifdef CONFIG_CACHE_L2X0 diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 20334236afce..822903421943 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -12,9 +12,13 @@ #include <linux/gpio.h> #include <linux/amba/bus.h> +#include <plat/ste_dma40.h> + #include <mach/hardware.h> #include <mach/setup.h> +#include "ste-dma40-db8500.h" + static struct nmk_gpio_platform_data u8500_gpio_data[] = { GPIO_DATA("GPIO-0-31", 0), GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */ @@ -105,3 +109,108 @@ struct platform_device u8500_i2c4_device = { .resource = u8500_i2c4_resources, .num_resources = ARRAY_SIZE(u8500_i2c4_resources), }; + +static struct resource dma40_resources[] = { + [0] = { + .start = U8500_DMA_BASE, + .end = U8500_DMA_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + .name = "base", + }, + [1] = { + .start = U8500_DMA_LCPA_BASE, + .end = U8500_DMA_LCPA_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + .name = "lcpa", + }, + [2] = { + .start = U8500_DMA_LCLA_BASE, + .end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1, + .flags = IORESOURCE_MEM, + .name = "lcla", + }, + [3] = { + .start = IRQ_DMA, + .end = IRQ_DMA, + .flags = IORESOURCE_IRQ} +}; + +/* Default configuration for physcial memcpy */ +struct stedma40_chan_cfg dma40_memcpy_conf_phy = { + .channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE | + STEDMA40_LOW_PRIORITY_CHANNEL | + STEDMA40_PCHAN_BASIC_MODE), + .dir = STEDMA40_MEM_TO_MEM, + + .src_info.endianess = STEDMA40_LITTLE_ENDIAN, + .src_info.data_width = STEDMA40_BYTE_WIDTH, + .src_info.psize = STEDMA40_PSIZE_PHY_1, + + .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, + .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dst_info.psize = STEDMA40_PSIZE_PHY_1, + +}; +/* Default configuration for logical memcpy */ +struct stedma40_chan_cfg dma40_memcpy_conf_log = { + .channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE | + STEDMA40_LOW_PRIORITY_CHANNEL | + STEDMA40_LCHAN_SRC_LOG_DST_LOG | + STEDMA40_NO_TIM_FOR_LINK), + .dir = STEDMA40_MEM_TO_MEM, + + .src_info.endianess = STEDMA40_LITTLE_ENDIAN, + .src_info.data_width = STEDMA40_BYTE_WIDTH, + .src_info.psize = STEDMA40_PSIZE_LOG_1, + + .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, + .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dst_info.psize = STEDMA40_PSIZE_LOG_1, + +}; + +/* + * Mapping between destination event lines and physical device address. + * The event line is tied to a device and therefor the address is constant. + */ +static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV]; + +/* Mapping between source event lines and physical device address */ +static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; + +/* Reserved event lines for memcpy only */ +static int dma40_memcpy_event[] = { + STEDMA40_MEMCPY_TX_1, + STEDMA40_MEMCPY_TX_2, + STEDMA40_MEMCPY_TX_3, + STEDMA40_MEMCPY_TX_4, +}; + +static struct stedma40_platform_data dma40_plat_data = { + .dev_len = STEDMA40_NR_DEV, + .dev_rx = dma40_rx_map, + .dev_tx = dma40_tx_map, + .memcpy = dma40_memcpy_event, + .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), + .memcpy_conf_phy = &dma40_memcpy_conf_phy, + .memcpy_conf_log = &dma40_memcpy_conf_log, + .llis_per_log = 8, +}; + +struct platform_device u8500_dma40_device = { + .dev = { + .platform_data = &dma40_plat_data, + }, + .name = "dma40", + .id = 0, + .num_resources = ARRAY_SIZE(dma40_resources), + .resource = dma40_resources +}; + +void dma40_u8500ed_fixup(void) +{ + dma40_plat_data.memcpy = NULL; + dma40_plat_data.memcpy_len = 0; + dma40_resources[0].start = U8500_DMA_BASE_ED; + dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; +} diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 9169e1e382a3..85fc6a80b386 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -7,6 +7,18 @@ #ifndef __MACH_DB8500_REGS_H #define __MACH_DB8500_REGS_H +/* Base address and bank offsets for ESRAM */ +#define U8500_ESRAM_BASE 0x40000000 +#define U8500_ESRAM_BANK_SIZE 0x00020000 +#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE +#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) +#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) +/* Use bank 4 for DMA LCLA and LCPA */ +#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 +#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK4 + 0x4000) + #define U8500_PER3_BASE 0x80000000 #define U8500_STM_BASE 0x80100000 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 0422af00a56e..c2b2f2574947 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -25,5 +25,8 @@ extern struct platform_device ux500_i2c3_device; extern struct platform_device u8500_i2c0_device; extern struct platform_device u8500_i2c4_device; +extern struct platform_device u8500_dma40_device; + +void dma40_u8500ed_fixup(void); #endif diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h new file mode 100644 index 000000000000..e7016278dfa9 --- /dev/null +++ b/arch/arm/mach-ux500/ste-dma40-db8500.h @@ -0,0 +1,154 @@ +/* + * arch/arm/mach-ux500/ste_dma40_db8500.h + * DB8500-SoC-specific configuration for DMA40 + * + * Copyright (C) ST-Ericsson 2007-2010 + * License terms: GNU General Public License (GPL) version 2 + * Author: Per Friden <per.friden@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ +#ifndef STE_DMA40_DB8500_H +#define STE_DMA40_DB8500_H + +#define STEDMA40_NR_DEV 64 + +enum dma_src_dev_type { + STEDMA40_DEV_SPI0_RX = 0, + STEDMA40_DEV_SD_MMC0_RX = 1, + STEDMA40_DEV_SD_MMC1_RX = 2, + STEDMA40_DEV_SD_MMC2_RX = 3, + STEDMA40_DEV_I2C1_RX = 4, + STEDMA40_DEV_I2C3_RX = 5, + STEDMA40_DEV_I2C2_RX = 6, + STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */ + STEDMA40_DEV_SSP0_RX = 8, + STEDMA40_DEV_SSP1_RX = 9, + STEDMA40_DEV_MCDE_RX = 10, + STEDMA40_DEV_UART2_RX = 11, + STEDMA40_DEV_UART1_RX = 12, + STEDMA40_DEV_UART0_RX = 13, + STEDMA40_DEV_MSP2_RX = 14, + STEDMA40_DEV_I2C0_RX = 15, + STEDMA40_DEV_USB_OTG_IEP_8 = 16, + STEDMA40_DEV_USB_OTG_IEP_1_9 = 17, + STEDMA40_DEV_USB_OTG_IEP_2_10 = 18, + STEDMA40_DEV_USB_OTG_IEP_3_11 = 19, + STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20, + STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21, + STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22, + STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23, + STEDMA40_DEV_SRC_SXA0_RX_TX = 24, + STEDMA40_DEV_SRC_SXA1_RX_TX = 25, + STEDMA40_DEV_SRC_SXA2_RX_TX = 26, + STEDMA40_DEV_SRC_SXA3_RX_TX = 27, + STEDMA40_DEV_SD_MM2_RX = 28, + STEDMA40_DEV_SD_MM0_RX = 29, + STEDMA40_DEV_MSP1_RX = 30, + /* + * This channel is either SlimBus or MSP, + * never both at the same time. + */ + STEDMA40_SLIM0_CH0_RX = 31, + STEDMA40_DEV_MSP0_RX = 31, + STEDMA40_DEV_SD_MM1_RX = 32, + STEDMA40_DEV_SPI2_RX = 33, + STEDMA40_DEV_I2C3_RX2 = 34, + STEDMA40_DEV_SPI1_RX = 35, + STEDMA40_DEV_USB_OTG_IEP_4_12 = 36, + STEDMA40_DEV_USB_OTG_IEP_5_13 = 37, + STEDMA40_DEV_USB_OTG_IEP_6_14 = 38, + STEDMA40_DEV_USB_OTG_IEP_7_15 = 39, + STEDMA40_DEV_SPI3_RX = 40, + STEDMA40_DEV_SD_MM3_RX = 41, + STEDMA40_DEV_SD_MM4_RX = 42, + STEDMA40_DEV_SD_MM5_RX = 43, + STEDMA40_DEV_SRC_SXA4_RX_TX = 44, + STEDMA40_DEV_SRC_SXA5_RX_TX = 45, + STEDMA40_DEV_SRC_SXA6_RX_TX = 46, + STEDMA40_DEV_SRC_SXA7_RX_TX = 47, + STEDMA40_DEV_CAC1_RX = 48, + /* RX channels 49 and 50 are unused */ + STEDMA40_DEV_MSHC_RX = 51, + STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52, + STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53, + STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54, + STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55, + /* RX channels 56 thru 60 are unused */ + STEDMA40_DEV_CAC0_RX = 61, + /* RX channels 62 and 63 are unused */ +}; + +enum dma_dest_dev_type { + STEDMA40_DEV_SPI0_TX = 0, + STEDMA40_DEV_SD_MMC0_TX = 1, + STEDMA40_DEV_SD_MMC1_TX = 2, + STEDMA40_DEV_SD_MMC2_TX = 3, + STEDMA40_DEV_I2C1_TX = 4, + STEDMA40_DEV_I2C3_TX = 5, + STEDMA40_DEV_I2C2_TX = 6, + STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */ + STEDMA40_DEV_SSP0_TX = 8, + STEDMA40_DEV_SSP1_TX = 9, + /* TX channel 10 is unused */ + STEDMA40_DEV_UART2_TX = 11, + STEDMA40_DEV_UART1_TX = 12, + STEDMA40_DEV_UART0_TX= 13, + STEDMA40_DEV_MSP2_TX = 14, + STEDMA40_DEV_I2C0_TX = 15, + STEDMA40_DEV_USB_OTG_OEP_8 = 16, + STEDMA40_DEV_USB_OTG_OEP_1_9 = 17, + STEDMA40_DEV_USB_OTG_OEP_2_10= 18, + STEDMA40_DEV_USB_OTG_OEP_3_11 = 19, + STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20, + STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21, + STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22, + STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23, + STEDMA40_DEV_DST_SXA0_RX_TX = 24, + STEDMA40_DEV_DST_SXA1_RX_TX = 25, + STEDMA40_DEV_DST_SXA2_RX_TX = 26, + STEDMA40_DEV_DST_SXA3_RX_TX = 27, + STEDMA40_DEV_SD_MM2_TX = 28, + STEDMA40_DEV_SD_MM0_TX = 29, + STEDMA40_DEV_MSP1_TX = 30, + /* + * This channel is either SlimBus or MSP, + * never both at the same time. + */ + STEDMA40_SLIM0_CH0_TX = 31, + STEDMA40_DEV_MSP0_TX = 31, + STEDMA40_DEV_SD_MM1_TX = 32, + STEDMA40_DEV_SPI2_TX = 33, + /* Secondary I2C3 channel */ + STEDMA40_DEV_I2C3_TX2 = 34, + STEDMA40_DEV_SPI1_TX = 35, + STEDMA40_DEV_USB_OTG_OEP_4_12 = 36, + STEDMA40_DEV_USB_OTG_OEP_5_13 = 37, + STEDMA40_DEV_USB_OTG_OEP_6_14 = 38, + STEDMA40_DEV_USB_OTG_OEP_7_15 = 39, + STEDMA40_DEV_SPI3_TX = 40, + STEDMA40_DEV_SD_MM3_TX = 41, + STEDMA40_DEV_SD_MM4_TX = 42, + STEDMA40_DEV_SD_MM5_TX = 43, + STEDMA40_DEV_DST_SXA4_RX_TX = 44, + STEDMA40_DEV_DST_SXA5_RX_TX = 45, + STEDMA40_DEV_DST_SXA6_RX_TX = 46, + STEDMA40_DEV_DST_SXA7_RX_TX = 47, + STEDMA40_DEV_CAC1_TX = 48, + STEDMA40_DEV_CAC1_TX_HAC1_TX = 49, + STEDMA40_DEV_HAC1_TX = 50, + STEDMA40_MEMXCPY_TX_0 = 51, + STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52, + STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53, + STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54, + STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55, + STEDMA40_MEMCPY_TX_1 = 56, + STEDMA40_MEMCPY_TX_2 = 57, + STEDMA40_MEMCPY_TX_3 = 58, + STEDMA40_MEMCPY_TX_4 = 59, + STEDMA40_MEMCPY_TX_5 = 60, + STEDMA40_DEV_CAC0_TX = 61, + STEDMA40_DEV_CAC0_TX_HAC0_TX = 62, + STEDMA40_DEV_HAC0_TX = 63, +}; + +#endif diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c index e2958eb567f9..b2eda4dc1c34 100644 --- a/arch/arm/mach-w90x900/dev.c +++ b/arch/arm/mach-w90x900/dev.c @@ -423,6 +423,33 @@ void nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd) } #endif +/* AUDIO controller*/ +static u64 nuc900_device_audio_dmamask = -1; +static struct resource nuc900_ac97_resource[] = { + [0] = { + .start = W90X900_PA_ACTL, + .end = W90X900_PA_ACTL + W90X900_SZ_ACTL - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_ACTL, + .end = IRQ_ACTL, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device nuc900_device_audio = { + .name = "nuc900-audio", + .id = -1, + .num_resources = ARRAY_SIZE(nuc900_ac97_resource), + .resource = nuc900_ac97_resource, + .dev = { + .dma_mask = &nuc900_device_audio_dmamask, + .coherent_dma_mask = -1, + } +}; + /*Here should be your evb resourse,such as LCD*/ static struct platform_device *nuc900_public_dev[] __initdata = { @@ -434,6 +461,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = { &nuc900_device_emc, &nuc900_device_spi, &nuc900_device_wdt, + &nuc900_device_audio, }; /* Provide adding specific CPU platform devices API */ diff --git a/arch/arm/mach-w90x900/include/mach/mfp.h b/arch/arm/mach-w90x900/include/mach/mfp.h new file mode 100644 index 000000000000..94c0e71617c6 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/mfp.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-w90x900/include/mach/mfp.h + * + * Copyright (c) 2010 Nuvoton technology corporation. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/map.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation;version 2 of the License. + * + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +extern void mfp_set_groupf(struct device *dev); +extern void mfp_set_groupc(struct device *dev); +extern void mfp_set_groupi(struct device *dev); +extern void mfp_set_groupg(struct device *dev); + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c index a47dc9a708ee..fb7fb627b1a5 100644 --- a/arch/arm/mach-w90x900/mfp.c +++ b/arch/arm/mach-w90x900/mfp.c @@ -36,9 +36,12 @@ #define GPIOG0TO1 (0x03 << 14) #define GPIOG2TO3 (0x03 << 16) +#define GPIOG22TO23 (0x03 << 22) + #define ENSPI (0x0a << 14) #define ENI2C0 (0x01 << 14) #define ENI2C1 (0x01 << 16) +#define ENAC97 (0x02 << 22) static DEFINE_MUTEX(mfp_mutex); @@ -146,6 +149,9 @@ void mfp_set_groupg(struct device *dev) } else if (strcmp(dev_id, "nuc900-i2c1") == 0) { mfpen &= ~(GPIOG2TO3); mfpen |= ENI2C1;/*enable i2c1*/ + } else if (strcmp(dev_id, "nuc900-audio") == 0) { + mfpen &= ~(GPIOG22TO23); + mfpen |= ENAC97;/*enable AC97*/ } else { mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ } diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 06a90dcfc60a..37c8157e116e 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -91,7 +91,11 @@ ENTRY(v7_flush_kern_cache_all) THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) bl v7_flush_dcache_all mov r0, #0 +#ifdef CONFIG_SMP + mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable +#else mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#endif ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) mov pc, lr diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c index 5eb4fd93893d..ac163de7dc01 100644 --- a/arch/arm/mm/copypage-feroceon.c +++ b/arch/arm/mm/copypage-feroceon.c @@ -18,7 +18,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom) { asm("\ stmfd sp!, {r4-r9, lr} \n\ - mov ip, %0 \n\ + mov ip, %2 \n\ 1: mov lr, r1 \n\ ldmia r1!, {r2 - r9} \n\ pld [lr, #32] \n\ @@ -64,7 +64,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom) mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\ ldmfd sp!, {r4-r9, pc}" : - : "I" (PAGE_SIZE)); + : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE)); } void feroceon_copy_user_highpage(struct page *to, struct page *from, diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c index 7c2eb55cd4a9..cb589cbb2b6c 100644 --- a/arch/arm/mm/copypage-v4wb.c +++ b/arch/arm/mm/copypage-v4wb.c @@ -27,7 +27,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom) { asm("\ stmfd sp!, {r4, lr} @ 2\n\ - mov r2, %0 @ 1\n\ + mov r2, %2 @ 1\n\ ldmia r1!, {r3, r4, ip, lr} @ 4\n\ 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ stmia r0!, {r3, r4, ip, lr} @ 4\n\ @@ -44,7 +44,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom) mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ ldmfd sp!, {r4, pc} @ 3" : - : "I" (PAGE_SIZE / 64)); + : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64)); } void v4wb_copy_user_highpage(struct page *to, struct page *from, diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c index 172e6a55458e..30c7d048a324 100644 --- a/arch/arm/mm/copypage-v4wt.c +++ b/arch/arm/mm/copypage-v4wt.c @@ -25,7 +25,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom) { asm("\ stmfd sp!, {r4, lr} @ 2\n\ - mov r2, %0 @ 1\n\ + mov r2, %2 @ 1\n\ ldmia r1!, {r3, r4, ip, lr} @ 4\n\ 1: stmia r0!, {r3, r4, ip, lr} @ 4\n\ ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ @@ -40,7 +40,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom) mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ ldmfd sp!, {r4, pc} @ 3" : - : "I" (PAGE_SIZE / 64)); + : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64)); } void v4wt_copy_user_highpage(struct page *to, struct page *from, diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c index 747ad4140fc7..f9cde0702f1e 100644 --- a/arch/arm/mm/copypage-xsc3.c +++ b/arch/arm/mm/copypage-xsc3.c @@ -34,7 +34,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom) { asm("\ stmfd sp!, {r4, r5, lr} \n\ - mov lr, %0 \n\ + mov lr, %2 \n\ \n\ pld [r1, #0] \n\ pld [r1, #32] \n\ @@ -67,7 +67,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom) \n\ ldmfd sp!, {r4, r5, pc}" : - : "I" (PAGE_SIZE / 64 - 1)); + : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64 - 1)); } void xsc3_mc_copy_user_highpage(struct page *to, struct page *from, diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 92f5801f99c1..cbfb2edcf7d1 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr, if (addr < TASK_SIZE) return do_page_fault(addr, fsr, regs); + if (user_mode(regs)) + goto bad_area; + index = pgd_index(addr); /* diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 77b030f5ec09..086816b205b8 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -48,7 +48,16 @@ void *kmap_atomic(struct page *page, enum km_type type) debug_kmap_atomic(type); - kmap = kmap_high_get(page); +#ifdef CONFIG_DEBUG_HIGHMEM + /* + * There is no cache coherency issue when non VIVT, so force the + * dedicated kmap usage for better debugging purposes in that case. + */ + if (!cache_is_vivt()) + kmap = NULL; + else +#endif + kmap = kmap_high_get(page); if (kmap) return kmap; diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 1ba6cf5a2c02..f6a999465323 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -678,10 +678,10 @@ void __init mem_init(void) void free_initmem(void) { #ifdef CONFIG_HAVE_TCM - extern char *__tcm_start, *__tcm_end; + extern char __tcm_start, __tcm_end; - totalram_pages += free_area(__phys_to_pfn(__pa(__tcm_start)), - __phys_to_pfn(__pa(__tcm_end)), + totalram_pages += free_area(__phys_to_pfn(__pa(&__tcm_start)), + __phys_to_pfn(__pa(&__tcm_end)), "TCM link"); #endif diff --git a/arch/arm/nwfpe/ChangeLog b/arch/arm/nwfpe/ChangeLog index eeb5a7c5ff09..fa8028b1e1cf 100644 --- a/arch/arm/nwfpe/ChangeLog +++ b/arch/arm/nwfpe/ChangeLog @@ -72,7 +72,7 @@ 1998-11-23 Scott Bambrough <scottb@netwinder.org> * README.FPE - fix typo in description of lfm/sfm instructions - * NOTES - Added file to describe known bugs/problems + * NOTES - Added file to describe known bugs/problems * fpmodule.c - Changed version number to 0.94 1998-11-20 Scott Bambrough <scottb@netwinder.org> diff --git a/arch/arm/nwfpe/fpsr.h b/arch/arm/nwfpe/fpsr.h index 859b300d89fd..bd425dc13b61 100644 --- a/arch/arm/nwfpe/fpsr.h +++ b/arch/arm/nwfpe/fpsr.h @@ -30,7 +30,7 @@ one byte. EXCEPTION TRAP ENABLE BYTE SYSTEM CONTROL BYTE CUMULATIVE EXCEPTION FLAGS BYTE - + The FPCR is a 32 bit register consisting of bit flags. */ diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index cb0b63874482..2a8646173c2f 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> + * Copyright (C) 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -50,7 +51,26 @@ #define MX35_H1_TLL_BIT (1 << 5) #define MX35_H1_USBTE_BIT (1 << 4) -int mxc_set_usbcontrol(int port, unsigned int flags) +#define MXC_OTG_OFFSET 0 +#define MXC_H1_OFFSET 0x200 + +/* USB_CTRL */ +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ +#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ + +/* USB_PHY_CTRL_FUNC */ +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ + +#define MXC_USBCMD_OFFSET 0x140 + +/* USBCMD */ +#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ + +int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; #ifdef CONFIG_ARCH_MX3 @@ -186,9 +206,85 @@ int mxc_set_usbcontrol(int port, unsigned int flags) return 0; } #endif /* CONFIG_MACH_MX27 */ +#ifdef CONFIG_ARCH_MX51 + if (cpu_is_mx51()) { + void __iomem *usb_base; + u32 usbotg_base; + u32 usbother_base; + int ret = 0; + + usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + + switch (port) { + case 0: /* OTG port */ + usbotg_base = usb_base + MXC_OTG_OFFSET; + break; + case 1: /* Host 1 port */ + usbotg_base = usb_base + MXC_H1_OFFSET; + break; + default: + printk(KERN_ERR"%s no such port %d\n", __func__, port); + ret = -ENOENT; + goto error; + } + usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; + + switch (port) { + case 0: /*OTG port */ + if (flags & MXC_EHCI_INTERNAL_PHY) { + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ + else + v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) + v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ + else + v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ + __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); + } + break; + case 1: /* Host 1 */ + /*Host ULPI */ + v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ + else + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ + else + v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); + + v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ + __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + + v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); + if (flags & MXC_EHCI_ITC_NO_THRESHOLD) + /* Interrupt Threshold Control:Immediate (no threshold) */ + v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; + __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); + break; + } + +error: + iounmap(usb_base); + return ret; + } +#endif printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); return -EINVAL; } -EXPORT_SYMBOL(mxc_set_usbcontrol); +EXPORT_SYMBOL(mxc_initialize_usb_hw); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 70b23893f094..71437c61cfd7 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -3,7 +3,7 @@ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * Based on code from Freescale, - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -38,7 +38,6 @@ static int gpio_table_size; #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) -#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) @@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); - if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { + if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index fc5fec9b55f0..36ff3cedee1a 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -26,6 +26,7 @@ enum mx31moboard_boards { MX31DEVBOARD = 1, MX31MARXBOT = 2, MX31SMARTBOT = 3, + MX31EYEBOT = 4, }; /* @@ -35,7 +36,7 @@ enum mx31moboard_boards { extern void mx31moboard_devboard_init(void); extern void mx31moboard_marxbot_init(void); -extern void mx31moboard_smartbot_init(void); +extern void mx31moboard_smartbot_init(int board); #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index e51465d7b224..cbaed295a2bf 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -719,6 +719,23 @@ enum iomux_pins { #define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) + /* * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index b4f975e6a665..ab0f95d953d0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -37,6 +38,11 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ + PAD_CTL_SRE_FAST) /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> @@ -57,6 +63,7 @@ typedef enum iomux_config { #define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) @@ -208,18 +215,19 @@ typedef enum iomux_config { #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) @@ -299,7 +307,7 @@ typedef enum iomux_config { #define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) #define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 4b9b8368c0c0..7fc5f9946199 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -25,6 +25,18 @@ #define MXC_EHCI_INTERNAL_PHY (1 << 7) #define MXC_EHCI_IPPUE_DOWN (1 << 8) #define MXC_EHCI_IPPUE_UP (1 << 9) +#define MXC_EHCI_WAKEUP_ENABLED (1 << 10) +#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) + +#define MXC_USBCTRL_OFFSET 0 +#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 +#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc + +#define MX5_USBOTHER_REGS_OFFSET 0x800 + +/* USB_PHY_CTRL_FUNC2*/ +#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3 +#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0 struct mxc_usbh_platform_data { int (*init)(struct platform_device *pdev); @@ -35,7 +47,7 @@ struct mxc_usbh_platform_data { struct otg_transceiver *otg; }; -int mxc_set_usbcontrol(int port, unsigned int flags); +int mxc_initialize_usb_hw(int port, unsigned int flags); #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index c1ce51abdba6..f9a1b059a76c 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -54,14 +54,14 @@ #define MX2_TSTAT_COMP (1 << 0) /* MX31, MX35, MX25, MXC91231, MX5 */ -#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ -#define MX3_TCTL_CLK_IPG (1 << 6) -#define MX3_TCTL_FRR (1 << 9) -#define MX3_IR 0x0c -#define MX3_TSTAT 0x08 -#define MX3_TSTAT_OF1 (1 << 0) -#define MX3_TCN 0x24 -#define MX3_TCMP 0x10 +#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ +#define V2_TCTL_CLK_IPG (1 << 6) +#define V2_TCTL_FRR (1 << 9) +#define V2_IR 0x0c +#define V2_TSTAT 0x08 +#define V2_TSTAT_OF1 (1 << 0) +#define V2_TCN 0x24 +#define V2_TCMP 0x10 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) #define timer_is_v2() (!timer_is_v1()) @@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void) unsigned int tmp; if (timer_is_v2()) - __raw_writel(0, timer_base + MX3_IR); + __raw_writel(0, timer_base + V2_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); @@ -86,7 +86,7 @@ static inline void gpt_irq_disable(void) static inline void gpt_irq_enable(void) { if (timer_is_v2()) - __raw_writel(1<<0, timer_base + MX3_IR); + __raw_writel(1<<0, timer_base + V2_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); @@ -102,7 +102,7 @@ static void gpt_irq_acknowledge(void) __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); } else if (timer_is_v2()) - __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); + __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); } static cycle_t mx1_2_get_cycles(struct clocksource *cs) @@ -110,9 +110,9 @@ static cycle_t mx1_2_get_cycles(struct clocksource *cs) return __raw_readl(timer_base + MX1_2_TCN); } -static cycle_t mx3_get_cycles(struct clocksource *cs) +static cycle_t v2_get_cycles(struct clocksource *cs) { - return __raw_readl(timer_base + MX3_TCN); + return __raw_readl(timer_base + V2_TCN); } static struct clocksource clocksource_mxc = { @@ -129,7 +129,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) unsigned int c = clk_get_rate(timer_clk); if (timer_is_v2()) - clocksource_mxc.read = mx3_get_cycles; + clocksource_mxc.read = v2_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, clocksource_mxc.shift); @@ -153,16 +153,16 @@ static int mx1_2_set_next_event(unsigned long evt, -ETIME : 0; } -static int mx3_set_next_event(unsigned long evt, +static int v2_set_next_event(unsigned long evt, struct clock_event_device *unused) { unsigned long tcmp; - tcmp = __raw_readl(timer_base + MX3_TCN) + evt; + tcmp = __raw_readl(timer_base + V2_TCN) + evt; - __raw_writel(tcmp, timer_base + MX3_TCMP); + __raw_writel(tcmp, timer_base + V2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ? + return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -192,8 +192,8 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, - timer_base + MX3_TCMP); + __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, + timer_base + V2_TCMP); else __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, timer_base + MX1_2_TCMP); @@ -245,7 +245,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) uint32_t tstat; if (timer_is_v2()) - tstat = __raw_readl(timer_base + MX3_TSTAT); + tstat = __raw_readl(timer_base + V2_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); @@ -276,7 +276,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) unsigned int c = clk_get_rate(timer_clk); if (timer_is_v2()) - clockevent_mxc.set_next_event = mx3_set_next_event; + clockevent_mxc.set_next_event = v2_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, clockevent_mxc.shift); @@ -308,7 +308,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) - tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; + tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index afa6709db0b3..9b86d2a60d43 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -19,6 +19,7 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/common.h> /* ***************************************** @@ -144,6 +145,7 @@ void __init tzic_init_irq(void __iomem *irqbase) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } + mxc_register_gpios(); pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h new file mode 100644 index 000000000000..4d12ea4ca361 --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -0,0 +1,239 @@ +/* + * arch/arm/plat-nomadik/include/plat/ste_dma40.h + * + * Copyright (C) ST-Ericsson 2007-2010 + * License terms: GNU General Public License (GPL) version 2 + * Author: Per Friden <per.friden@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ + + +#ifndef STE_DMA40_H +#define STE_DMA40_H + +#include <linux/dmaengine.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/dmaengine.h> + +/* dev types for memcpy */ +#define STEDMA40_DEV_DST_MEMORY (-1) +#define STEDMA40_DEV_SRC_MEMORY (-1) + +/* + * Description of bitfields of channel_type variable is available in + * the info structure. + */ + +/* Priority */ +#define STEDMA40_INFO_PRIO_TYPE_POS 2 +#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS) +#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS) + +/* Mode */ +#define STEDMA40_INFO_CH_MODE_TYPE_POS 6 +#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS) +#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS) +#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS) + +/* Mode options */ +#define STEDMA40_INFO_CH_MODE_OPT_POS 8 +#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) +#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) + +/* Interrupt */ +#define STEDMA40_INFO_TIM_POS 10 +#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS) +#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS) + +/* End of channel_type configuration */ + +#define STEDMA40_ESIZE_8_BIT 0x0 +#define STEDMA40_ESIZE_16_BIT 0x1 +#define STEDMA40_ESIZE_32_BIT 0x2 +#define STEDMA40_ESIZE_64_BIT 0x3 + +/* The value 4 indicates that PEN-reg shall be set to 0 */ +#define STEDMA40_PSIZE_PHY_1 0x4 +#define STEDMA40_PSIZE_PHY_2 0x0 +#define STEDMA40_PSIZE_PHY_4 0x1 +#define STEDMA40_PSIZE_PHY_8 0x2 +#define STEDMA40_PSIZE_PHY_16 0x3 + +/* + * The number of elements differ in logical and + * physical mode + */ +#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2 +#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4 +#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 +#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 + +enum stedma40_flow_ctrl { + STEDMA40_NO_FLOW_CTRL, + STEDMA40_FLOW_CTRL, +}; + +enum stedma40_endianess { + STEDMA40_LITTLE_ENDIAN, + STEDMA40_BIG_ENDIAN +}; + +enum stedma40_periph_data_width { + STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, + STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, + STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT, + STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT +}; + +struct stedma40_half_channel_info { + enum stedma40_endianess endianess; + enum stedma40_periph_data_width data_width; + int psize; + enum stedma40_flow_ctrl flow_ctrl; +}; + +enum stedma40_xfer_dir { + STEDMA40_MEM_TO_MEM, + STEDMA40_MEM_TO_PERIPH, + STEDMA40_PERIPH_TO_MEM, + STEDMA40_PERIPH_TO_PERIPH +}; + + +/** + * struct stedma40_chan_cfg - Structure to be filled by client drivers. + * + * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH + * @channel_type: priority, mode, mode options and interrupt configuration. + * @src_dev_type: Src device type + * @dst_dev_type: Dst device type + * @src_info: Parameters for dst half channel + * @dst_info: Parameters for dst half channel + * @pre_transfer_data: Data to be passed on to the pre_transfer() function. + * @pre_transfer: Callback used if needed before preparation of transfer. + * Only called if device is set. size of bytes to transfer + * (in case of multiple element transfer size is size of the first element). + * + * + * This structure has to be filled by the client drivers. + * It is recommended to do all dma configurations for clients in the machine. + * + */ +struct stedma40_chan_cfg { + enum stedma40_xfer_dir dir; + unsigned int channel_type; + int src_dev_type; + int dst_dev_type; + struct stedma40_half_channel_info src_info; + struct stedma40_half_channel_info dst_info; + void *pre_transfer_data; + int (*pre_transfer) (struct dma_chan *chan, + void *data, + int size); +}; + +/** + * struct stedma40_platform_data - Configuration struct for the dma device. + * + * @dev_len: length of dev_tx and dev_rx + * @dev_tx: mapping between destination event line and io address + * @dev_rx: mapping between source event line and io address + * @memcpy: list of memcpy event lines + * @memcpy_len: length of memcpy + * @memcpy_conf_phy: default configuration of physical channel memcpy + * @memcpy_conf_log: default configuration of logical channel memcpy + * @llis_per_log: number of max linked list items per logical channel + * + */ +struct stedma40_platform_data { + u32 dev_len; + const dma_addr_t *dev_tx; + const dma_addr_t *dev_rx; + int *memcpy; + u32 memcpy_len; + struct stedma40_chan_cfg *memcpy_conf_phy; + struct stedma40_chan_cfg *memcpy_conf_log; + unsigned int llis_per_log; +}; + +/** + * setdma40_set_psize() - Used for changing the package size of an + * already configured dma channel. + * + * @chan: dmaengine handle + * @src_psize: new package side for src. (STEDMA40_PSIZE*) + * @src_psize: new package side for dst. (STEDMA40_PSIZE*) + * + * returns 0 on ok, otherwise negative error number. + */ +int stedma40_set_psize(struct dma_chan *chan, + int src_psize, + int dst_psize); + +/** + * stedma40_filter() - Provides stedma40_chan_cfg to the + * ste_dma40 dma driver via the dmaengine framework. + * does some checking of what's provided. + * + * Never directly called by client. It used by dmaengine. + * @chan: dmaengine handle. + * @data: Must be of type: struct stedma40_chan_cfg and is + * the configuration of the framework. + * + * + */ + +bool stedma40_filter(struct dma_chan *chan, void *data); + +/** + * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from + * scattergatter lists. + * + * @chan: dmaengine handle + * @sgl_dst: Destination scatter list + * @sgl_src: Source scatter list + * @sgl_len: The length of each scatterlist. Both lists must be of equal length + * and each element must match the corresponding element in the other scatter + * list. + * @flags: is actually enum dma_ctrl_flags. See dmaengine.h + */ + +struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan, + struct scatterlist *sgl_dst, + struct scatterlist *sgl_src, + unsigned int sgl_len, + unsigned long flags); + +/** + * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave + * (=device) + * + * @chan: dmaengine handle + * @addr: source or destination physicall address. + * @size: bytes to transfer + * @direction: direction of transfer + * @flags: is actually enum dma_ctrl_flags. See dmaengine.h + */ + +static inline struct +dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, + dma_addr_t addr, + unsigned int size, + enum dma_data_direction direction, + unsigned long flags) +{ + struct scatterlist sg; + sg_init_table(&sg, 1); + sg.dma_address = addr; + sg.length = size; + + return chan->device->device_prep_slave_sg(chan, &sg, 1, + direction, flags); +} + +#endif diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 0ff3798769ab..08aaa4a7f65f 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -13,7 +13,9 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/clockchips.h> +#include <linux/clk.h> #include <linux/jiffies.h> +#include <linux/err.h> #include <asm/mach/time.h> #include <plat/mtu.h> @@ -124,13 +126,25 @@ static struct irqaction nmdk_timer_irq = { void __init nmdk_timer_init(void) { unsigned long rate; - u32 cr = MTU_CRn_32BITS;; + struct clk *clk0; + struct clk *clk1; + u32 cr; + + clk0 = clk_get_sys("mtu0", NULL); + BUG_ON(IS_ERR(clk0)); + + clk1 = clk_get_sys("mtu1", NULL); + BUG_ON(IS_ERR(clk1)); + + clk_enable(clk0); + clk_enable(clk1); /* * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500: * use a divide-by-16 counter if it's more than 16MHz */ - rate = CLOCK_TICK_RATE; + cr = MTU_CRn_32BITS;; + rate = clk_get_rate(clk0); if (rate > 16 << 20) { rate /= 16; cr |= MTU_CRn_PRESCALE_16; @@ -153,6 +167,14 @@ void __init nmdk_timer_init(void) nmdk_clksrc.name); /* Timer 1 is used for events, fix according to rate */ + cr = MTU_CRn_32BITS; + rate = clk_get_rate(clk1); + if (rate > 16 << 20) { + rate /= 16; + cr |= MTU_CRn_PRESCALE_16; + } else { + cr |= MTU_CRn_PRESCALE_1; + } writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); nmdk_clkevt.max_delta_ns = diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index dc2ac42d6319..393e9219a5b6 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -624,79 +624,58 @@ do { \ __raw_writel(l, base + reg); \ } while(0) -void omap_set_gpio_debounce(int gpio, int enable) +/** + * _set_gpio_debounce - low level gpio debounce time + * @bank: the gpio bank we're acting upon + * @gpio: the gpio number on this @gpio + * @debounce: debounce time to use + * + * OMAP's debounce time is in 31us steps so we need + * to convert and round up to the closest unit. + */ +static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, + unsigned debounce) { - struct gpio_bank *bank; - void __iomem *reg; - unsigned long flags; - u32 val, l = 1 << get_gpio_index(gpio); + void __iomem *reg = bank->base; + u32 val; + u32 l; + + if (debounce < 32) + debounce = 0x01; + else if (debounce > 7936) + debounce = 0xff; + else + debounce = (debounce / 0x1f) - 1; - if (cpu_class_is_omap1()) - return; + l = 1 << get_gpio_index(gpio); - bank = get_gpio_bank(gpio); - reg = bank->base; + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCINGTIME; + else + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; + + __raw_writel(debounce, reg); + reg = bank->base; if (cpu_is_omap44xx()) reg += OMAP4_GPIO_DEBOUNCENABLE; else reg += OMAP24XX_GPIO_DEBOUNCE_EN; - if (!(bank->mod_usage & l)) { - printk(KERN_ERR "GPIO %d not requested\n", gpio); - return; - } - - spin_lock_irqsave(&bank->lock, flags); val = __raw_readl(reg); - if (enable && !(val & l)) + if (debounce) { val |= l; - else if (!enable && (val & l)) - val &= ~l; - else - goto done; - - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - bank->dbck_enable_mask = val; - if (enable) + if (cpu_is_omap34xx() || cpu_is_omap44xx()) clk_enable(bank->dbck); - else + } else { + val &= ~l; + if (cpu_is_omap34xx() || cpu_is_omap44xx()) clk_disable(bank->dbck); } __raw_writel(val, reg); -done: - spin_unlock_irqrestore(&bank->lock, flags); } -EXPORT_SYMBOL(omap_set_gpio_debounce); - -void omap_set_gpio_debounce_time(int gpio, int enc_time) -{ - struct gpio_bank *bank; - void __iomem *reg; - - if (cpu_class_is_omap1()) - return; - - bank = get_gpio_bank(gpio); - reg = bank->base; - - if (!bank->mod_usage) { - printk(KERN_ERR "GPIO not requested\n"); - return; - } - - enc_time &= 0xff; - - if (cpu_is_omap44xx()) - reg += OMAP4_GPIO_DEBOUNCINGTIME; - else - reg += OMAP24XX_GPIO_DEBOUNCE_VAL; - - __raw_writel(enc_time, reg); -} -EXPORT_SYMBOL(omap_set_gpio_debounce_time); #ifdef CONFIG_ARCH_OMAP2PLUS static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, @@ -1656,6 +1635,20 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) return 0; } +static int gpio_debounce(struct gpio_chip *chip, unsigned offset, + unsigned debounce) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_debounce(bank, offset, debounce); + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct gpio_bank *bank; @@ -1909,6 +1902,7 @@ static int __init _omap_gpio_init(void) bank->chip.direction_input = gpio_input; bank->chip.get = gpio_get; bank->chip.direction_output = gpio_output; + bank->chip.set_debounce = gpio_debounce; bank->chip.set = gpio_set; bank->chip.to_irq = gpio_2irq; if (bank_is_mpuio(bank)) { diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 2845fdc658b0..98fc8b4a4cc4 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -82,5 +82,10 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) +/* Security */ +#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000) +#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) +#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) + #endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 58583732b29a..452e18438b41 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -234,32 +234,6 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) } } - -/* Watchdog */ - -static struct resource s3c_wdt_resource[] = { - [0] = { - .start = S3C24XX_PA_WATCHDOG, - .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_WDT, - .end = IRQ_WDT, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_wdt = { - .name = "s3c2410-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_wdt_resource), - .resource = s3c_wdt_resource, -}; - -EXPORT_SYMBOL(s3c_device_wdt); - /* IIS */ static struct resource s3c_iis_resource[] = { diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 92bd75607b43..11d6a1bbd90d 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -7,7 +7,7 @@ config PLAT_S5P bool - depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210) + depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210) default y select ARM_VIC select NO_IOPORT @@ -24,3 +24,9 @@ config PLAT_S5P select SAMSUNG_IRQ_UART help Base platform code for Samsung's S5P series SoC. + +config S5P_EXT_INT + bool + help + Use the external interrupts (other than GPIO interrupts.) + Note: Do not choose this for S5P6440. diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 0ec09a9c36bd..39c242bb9d58 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -16,3 +16,5 @@ obj-y += dev-uart.o obj-y += cpu.o obj-y += clock.o obj-y += irq.o +obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o + diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 24a931fd8d3b..b5e255265f20 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -148,6 +148,7 @@ static struct clk *s5p_clks[] __initdata = { &clk_fout_vpll, &clk_arm, &clk_vpll, + &clk_xusbxti, }; void __init s5p_register_clocks(unsigned long xtal_freq) diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index f92e5de3a755..75cb8c37ca2c 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -19,12 +19,14 @@ #include <plat/cpu.h> #include <plat/s5p6440.h> #include <plat/s5p6442.h> +#include <plat/s5pc100.h> #include <plat/s5pv210.h> /* table of supported CPUs */ static const char name_s5p6440[] = "S5P6440"; static const char name_s5p6442[] = "S5P6442"; +static const char name_s5pc100[] = "S5PC100"; static const char name_s5pv210[] = "S5PV210/S5PC110"; static struct cpu_table cpu_ids[] __initdata = { @@ -45,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = { .init = s5p6442_init, .name = name_s5p6442, }, { + .idcode = 0x43100000, + .idmask = 0xfffff000, + .map_io = s5pc100_map_io, + .init_clocks = s5pc100_init_clocks, + .init_uarts = s5pc100_init_uarts, + .init = s5pc100_init, + .name = name_s5pc100, + }, { .idcode = 0x43110000, .idmask = 0xfffff000, .map_io = s5pv210_map_io, diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 9ff3d718be39..3fb3a3a17465 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -87,4 +87,11 @@ #define IRQ_TIMER3 S5P_TIMER_IRQ(3) #define IRQ_TIMER4 S5P_TIMER_IRQ(4) +#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ + : ((x) - 16 + S5P_EINT_BASE2)) + +#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \ + ((irq) - S5P_EINT_BASE1) : \ + ((irq) + 16 - S5P_EINT_BASE2)) + #endif /* __ASM_PLAT_S5P_IRQS_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h new file mode 100644 index 000000000000..5f6099dd7cad --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5pc100.h @@ -0,0 +1,33 @@ +/* arch/arm/plat-s5p/include/plat/s5pc100.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5pc100 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5PC100 related SoCs */ + +extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5pc100_register_clocks(void); +extern void s5pc100_setup_clocks(void); + +#ifdef CONFIG_CPU_S5PC100 + +extern int s5pc100_init(void); +extern void s5pc100_init_irq(void); +extern void s5pc100_map_io(void); +extern void s5pc100_init_clocks(int xtal); + +#define s5pc100_init_uarts s5pc100_common_init_uarts + +#else +#define s5pc100_init_clocks NULL +#define s5pc100_init_uarts NULL +#define s5pc100_map_io NULL +#define s5pc100_init NULL +#endif diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c new file mode 100644 index 000000000000..e56c8075df97 --- /dev/null +++ b/arch/arm/plat-s5p/irq-eint.c @@ -0,0 +1,218 @@ +/* linux/arch/arm/plat-s5p/irq-eint.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P - IRQ EINT support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/sysdev.h> +#include <linux/gpio.h> + +#include <asm/hardware/vic.h> + +#include <plat/regs-irqtype.h> + +#include <mach/map.h> +#include <plat/cpu.h> +#include <plat/pm.h> + +#include <plat/gpio-cfg.h> +#include <mach/regs-gpio.h> + +static inline void s5p_irq_eint_mask(unsigned int irq) +{ + u32 mask; + + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); + mask |= eint_irq_to_bit(irq); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); +} + +static void s5p_irq_eint_unmask(unsigned int irq) +{ + u32 mask; + + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); + mask &= ~(eint_irq_to_bit(irq)); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); +} + +static inline void s5p_irq_eint_ack(unsigned int irq) +{ + __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); +} + +static void s5p_irq_eint_maskack(unsigned int irq) +{ + /* compiler should in-line these */ + s5p_irq_eint_mask(irq); + s5p_irq_eint_ack(irq); +} + +static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) +{ + int offs = EINT_OFFSET(irq); + int shift; + u32 ctrl, mask; + u32 newvalue = 0; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + newvalue = S5P_EXTINT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S5P_EXTINT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S5P_EXTINT_BOTHEDGE; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S5P_EXTINT_LOWLEV; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S5P_EXTINT_HILEV; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -EINVAL; + } + + shift = (offs & 0x7) * 4; + mask = 0x7 << shift; + + ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); + ctrl &= ~mask; + ctrl |= newvalue << shift; + __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); + + if ((0 <= offs) && (offs < 8)) + s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); + + else if ((8 <= offs) && (offs < 16)) + s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); + + else if ((16 <= offs) && (offs < 24)) + s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); + + else if ((24 <= offs) && (offs < 32)) + s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); + + else + printk(KERN_ERR "No such irq number %d", offs); + + return 0; +} + +static struct irq_chip s5p_irq_eint = { + .name = "s5p-eint", + .mask = s5p_irq_eint_mask, + .unmask = s5p_irq_eint_unmask, + .mask_ack = s5p_irq_eint_maskack, + .ack = s5p_irq_eint_ack, + .set_type = s5p_irq_eint_set_type, +#ifdef CONFIG_PM + .set_wake = s3c_irqext_wake, +#endif +}; + +/* s5p_irq_demux_eint + * + * This function demuxes the IRQ from the group0 external interrupts, + * from EINTs 16 to 31. It is designed to be inlined into the specific + * handler s5p_irq_demux_eintX_Y. + * + * Each EINT pend/mask registers handle eight of them. + */ +static inline void s5p_irq_demux_eint(unsigned int start) +{ + u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); + u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); + unsigned int irq; + + status &= ~mask; + status &= 0xff; + + while (status) { + irq = fls(status) - 1; + generic_handle_irq(irq + start); + status &= ~(1 << irq); + } +} + +static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) +{ + s5p_irq_demux_eint(IRQ_EINT(16)); + s5p_irq_demux_eint(IRQ_EINT(24)); +} + +static inline void s5p_irq_vic_eint_mask(unsigned int irq) +{ + void __iomem *base = get_irq_chip_data(irq); + + s5p_irq_eint_mask(irq); + writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR); +} + +static void s5p_irq_vic_eint_unmask(unsigned int irq) +{ + void __iomem *base = get_irq_chip_data(irq); + + s5p_irq_eint_unmask(irq); + writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE); +} + +static inline void s5p_irq_vic_eint_ack(unsigned int irq) +{ + __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); +} + +static void s5p_irq_vic_eint_maskack(unsigned int irq) +{ + s5p_irq_vic_eint_mask(irq); + s5p_irq_vic_eint_ack(irq); +} + +static struct irq_chip s5p_irq_vic_eint = { + .name = "s5p_vic_eint", + .mask = s5p_irq_vic_eint_mask, + .unmask = s5p_irq_vic_eint_unmask, + .mask_ack = s5p_irq_vic_eint_maskack, + .ack = s5p_irq_vic_eint_ack, + .set_type = s5p_irq_eint_set_type, +#ifdef CONFIG_PM + .set_wake = s3c_irqext_wake, +#endif +}; + +int __init s5p_init_irq_eint(void) +{ + int irq; + + for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) + set_irq_chip(irq, &s5p_irq_vic_eint); + + for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { + set_irq_chip(irq, &s5p_irq_eint); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); + return 0; +} + +arch_initcall(s5p_init_irq_eint); diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig deleted file mode 100644 index c7bd2bbda239..000000000000 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -# Copyright 2009 Samsung Electronics Co. -# Byungho Min <bhmin@samsung.com> -# -# Licensed under GPLv2 - -config PLAT_S5PC1XX - bool - depends on ARCH_S5PC1XX - default y - select PLAT_S3C - select ARM_VIC - select NO_IOPORT - select ARCH_REQUIRE_GPIOLIB - select SAMSUNG_CLKSRC - select SAMSUNG_IRQ_UART - select SAMSUNG_IRQ_VIC_TIMER - select S3C_GPIO_TRACK - select S3C_GPIO_PULL_UPDOWN - select S5P_GPIO_DRVSTR - select S3C_GPIO_CFG_S3C24XX - select S3C_GPIO_CFG_S3C64XX - select SAMSUNG_GPIOLIB_4BIT - help - Base platform code for any Samsung S5PC1XX device - -if PLAT_S5PC1XX - -# Configuration options shared by all S3C64XX implementations - -config CPU_S5PC100_INIT - bool - help - Common initialisation code for the S5PC1XX - -config CPU_S5PC100_CLOCK - bool - help - Common clock support code for the S5PC1XX - -# platform specific device setup - -config S5PC1XX_SETUP_SDHCI_GPIO - bool - help - Common setup code for SDHCI gpio. - -endif diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile deleted file mode 100644 index 9ce6409a9e02..000000000000 --- a/arch/arm/plat-s5pc1xx/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# arch/arm/plat-s5pc1xx/Makefile -# -# Copyright 2009 Samsung Electronics Co. -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := dummy.o -obj- := - -# Core files - -obj-y += dev-uart.o -obj-y += cpu.o -obj-y += irq.o -obj-y += clock.o - -# CPU support - -obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o -obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o - -# Device setup - -obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c deleted file mode 100644 index 387f23190c3c..000000000000 --- a/arch/arm/plat-s5pc1xx/clock.c +++ /dev/null @@ -1,709 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/clock.c - * - * Copyright 2009 Samsung Electronics Co. - * - * S5PC1XX Base clock support - * - * Based on plat-s3c64xx/clock.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <plat/regs-clock.h> -#include <plat/devs.h> -#include <plat/clock.h> - -struct clk clk_27m = { - .name = "clk_27m", - .id = -1, - .rate = 27000000, -}; - -static int clk_48m_ctrl(struct clk *clk, int enable) -{ - unsigned long flags; - u32 val; - - /* can't rely on clock lock, this register has other usages */ - local_irq_save(flags); - - val = __raw_readl(S5PC100_CLKSRC1); - if (enable) - val |= S5PC100_CLKSRC1_CLK48M_MASK; - else - val &= ~S5PC100_CLKSRC1_CLK48M_MASK; - - __raw_writel(val, S5PC100_CLKSRC1); - local_irq_restore(flags); - - return 0; -} - -struct clk clk_48m = { - .name = "clk_48m", - .id = -1, - .rate = 48000000, - .enable = clk_48m_ctrl, -}; - -struct clk clk_54m = { - .name = "clk_54m", - .id = -1, - .rate = 54000000, -}; - -struct clk clk_hd0 = { - .name = "hclkd0", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - -struct clk clk_pd0 = { - .name = "pclkd0", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - -static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) -{ - unsigned int ctrlbit = clk->ctrlbit; - u32 con; - - con = __raw_readl(reg); - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; - __raw_writel(con, reg); - - return 0; -} - -static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); -} - -static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); -} - -static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); -} - -static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); -} - -static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); -} - -static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); -} - -static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); -} - -static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); -} - -static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); -} - -static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); -} - -int s5pc100_sclk0_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); -} - -int s5pc100_sclk1_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); -} - -static struct clk s5pc100_init_clocks_disable[] = { - { - .name = "dsi", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_DSI, - }, { - .name = "csi", - .id = -1, - .parent = &clk_h, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_CSI, - }, { - .name = "ccan", - .id = 0, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, - }, { - .name = "ccan", - .id = 1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, - }, { - .name = "keypad", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, - }, { - .name = "hclkd2", - .id = -1, - .parent = NULL, - .enable = s5pc100_clk_d20_ctrl, - .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, - }, { - .name = "iis-d2", - .id = -1, - .parent = NULL, - .enable = s5pc100_clk_d20_ctrl, - .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, - }, -}; - -static struct clk s5pc100_init_clocks[] = { - /* System1 (D0_0) devices */ - { - .name = "intc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_INTC, - }, { - .name = "tzic", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_TZIC, - }, { - .name = "cf-ata", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_CFCON, - }, { - .name = "mdma", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_MDMA, - }, { - .name = "g2d", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_G2D, - }, { - .name = "secss", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_SECSS, - }, { - .name = "cssys", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, - }, - - /* Memory (D0_1) devices */ - { - .name = "dmc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_DMC, - }, { - .name = "sromc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_SROMC, - }, { - .name = "onenand", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, - }, { - .name = "nand", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_NFCON, - }, { - .name = "intmem", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, - }, { - .name = "ebi", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_EBI, - }, - - /* System2 (D0_2) devices */ - { - .name = "seckey", - .id = -1, - .parent = &clk_pd0, - .enable = s5pc100_clk_d02_ctrl, - .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, - }, { - .name = "sdm", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc100_clk_d02_ctrl, - .ctrlbit = S5PC100_CLKGATE_D02_SDM, - }, - - /* File (D1_0) devices */ - { - .name = "pdma", - .id = 0, - .parent = &clk_h, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, - }, { - .name = "pdma", - .id = 1, - .parent = &clk_h, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, - }, { - .name = "usb-host", - .id = -1, - .parent = &clk_h, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, - }, { - .name = "otg", - .id = -1, - .parent = &clk_h, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, - }, { - .name = "modem", - .id = -1, - .parent = &clk_h, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, - }, { - .name = "hsmmc", - .id = 0, - .parent = &clk_48m, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, - }, { - .name = "hsmmc", - .id = 1, - .parent = &clk_48m, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, - }, { - .name = "hsmmc", - .id = 2, - .parent = &clk_48m, - .enable = s5pc100_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, - }, - - /* Multimedia1 (D1_1) devices */ - { - .name = "lcd", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_LCD, - }, { - .name = "rotator", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, - }, { - .name = "fimc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, - }, { - .name = "fimc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, - }, { - .name = "fimc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, - }, { - .name = "jpeg", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_JPEG, - }, { - .name = "g3d", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_G3D, - }, - - /* Multimedia2 (D1_2) devices */ - { - .name = "tv", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_TV, - }, { - .name = "vp", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_VP, - }, { - .name = "mixer", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_MIXER, - }, { - .name = "hdmi", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_HDMI, - }, { - .name = "mfc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_MFC, - }, - - /* System (D1_3) devices */ - { - .name = "chipid", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, - }, { - .name = "gpio", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_GPIO, - }, { - .name = "apc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_APC, - }, { - .name = "iec", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_IEC, - }, { - .name = "timers", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_PWM, - }, { - .name = "systimer", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, - }, { - .name = "watchdog", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_WDT, - }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_RTC, - }, - - /* Connectivity (D1_4) devices */ - { - .name = "uart", - .id = 0, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART0, - }, { - .name = "uart", - .id = 1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART1, - }, { - .name = "uart", - .id = 2, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART2, - }, { - .name = "uart", - .id = 3, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART3, - }, { - .name = "i2c", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_IIC, - }, { - .name = "hdmi-i2c", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, - }, { - .name = "spi", - .id = 0, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI0, - }, { - .name = "spi", - .id = 1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI1, - }, { - .name = "spi", - .id = 2, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI2, - }, { - .name = "irda", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_IRDA, - }, { - .name = "hsitx", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HSITX, - }, { - .name = "hsirx", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, - }, - - /* Audio (D1_5) devices */ - { - .name = "iis", - .id = 0, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS0, - }, { - .name = "iis", - .id = 1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS1, - }, { - .name = "iis", - .id = 2, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS2, - }, { - .name = "ac97", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_AC97, - }, { - .name = "pcm", - .id = 0, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_PCM0, - }, { - .name = "pcm", - .id = 1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_PCM1, - }, { - .name = "spdif", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, - }, { - .name = "adc", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_TSADC, - }, { - .name = "cg", - .id = -1, - .parent = &clk_p, - .enable = s5pc100_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_CG, - }, - - /* Audio (D2_0) devices: all disabled */ - - /* Special Clocks 0 */ - { - .name = "sclk_hpm", - .id = -1, - .parent = NULL, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, - }, { - .name = "sclk_onenand", - .id = -1, - .parent = NULL, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, - }, { - .name = "spi_48", - .id = 0, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, - }, { - .name = "spi_48", - .id = 1, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, - }, { - .name = "spi_48", - .id = 2, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, - }, { - .name = "mmc_48", - .id = 0, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, - }, { - .name = "mmc_48", - .id = 1, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, - }, { - .name = "mmc_48", - .id = 2, - .parent = &clk_48m, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, - }, - /* Special Clocks 1 */ -}; - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_epll, - &clk_pd0, - &clk_hd0, - &clk_27m, - &clk_48m, - &clk_54m, -}; - -void __init s5pc1xx_register_clocks(void) -{ - struct clk *clkp; - int ret; - int ptr; - int size; - - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - s3c_register_clocks(s5pc100_init_clocks, - ARRAY_SIZE(s5pc100_init_clocks)); - - clkp = s5pc100_init_clocks_disable; - size = ARRAY_SIZE(s5pc100_init_clocks_disable); - - for (ptr = 0; ptr < size; ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - (clkp->enable)(clkp, 0); - } - - s3c_pwmclk_init(); -} diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c deleted file mode 100644 index 02baeaa2a121..000000000000 --- a/arch/arm/plat-s5pc1xx/cpu.c +++ /dev/null @@ -1,122 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/cpu.c - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC1XX CPU Support - * - * Based on plat-s3c64xx/cpu.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <asm/mach/map.h> - -#include <plat/regs-serial.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> - -#include <plat/s5pc100.h> - -/* table of supported CPUs */ - -static const char name_s5pc100[] = "S5PC100"; - -static struct cpu_table cpu_ids[] __initdata = { - { - .idcode = 0x43100000, - .idmask = 0xfffff000, - .map_io = s5pc100_map_io, - .init_clocks = s5pc100_init_clocks, - .init_uarts = s5pc100_init_uarts, - .init = s5pc100_init, - .name = name_s5pc100, - }, -}; -/* minimal IO mapping */ - -/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */ -#define UART_OFFS (S3C_PA_UART & 0xffff) - -static struct map_desc s5pc1xx_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER, - .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_GPIO, - .pfn = __phys_to_pfn(S5PC100_PA_GPIO), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_CHIPID, - .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), - .length = SZ_16, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_CLK, - .pfn = __phys_to_pfn(S5PC1XX_PA_CLK), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_PWR, - .pfn = __phys_to_pfn(S5PC1XX_PA_PWR), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)(S5PC1XX_VA_UART), - .pfn = __phys_to_pfn(S5PC1XX_PA_UART), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_VIC(0), - .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_VIC(1), - .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_VIC(2), - .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5PC1XX_VA_TIMER, - .pfn = __phys_to_pfn(S5PC1XX_PA_TIMER), - .length = SZ_256, - .type = MT_DEVICE, - }, -}; - -/* read cpu identification code */ - -void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size) -{ - unsigned long idcode; - - /* initialise the io descriptors we need for initialisation */ - iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc)); - iotable_init(mach_desc, size); - - idcode = __raw_readl(S5PC1XX_VA_CHIPID); - s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); -} diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c deleted file mode 100644 index 586c95c60bfe..000000000000 --- a/arch/arm/plat-s5pc1xx/dev-uart.c +++ /dev/null @@ -1,145 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/dev-uart.c - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * Based on plat-s3c64xx/dev-uart.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> - -#include <plat/devs.h> - -/* Serial port registrations */ - -/* 64xx uarts are closer together */ - -static struct resource s5pc1xx_uart0_resource[] = { - [0] = { - .start = S3C_PA_UART0, - .end = S3C_PA_UART0 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX0, - .end = IRQ_S3CUART_RX0, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX0, - .end = IRQ_S3CUART_TX0, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR0, - .end = IRQ_S3CUART_ERR0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s5pc1xx_uart1_resource[] = { - [0] = { - .start = S3C_PA_UART1, - .end = S3C_PA_UART1 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX1, - .end = IRQ_S3CUART_RX1, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX1, - .end = IRQ_S3CUART_TX1, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR1, - .end = IRQ_S3CUART_ERR1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource s5pc1xx_uart2_resource[] = { - [0] = { - .start = S3C_PA_UART2, - .end = S3C_PA_UART2 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX2, - .end = IRQ_S3CUART_RX2, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX2, - .end = IRQ_S3CUART_TX2, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR2, - .end = IRQ_S3CUART_ERR2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource s5pc1xx_uart3_resource[] = { - [0] = { - .start = S3C_PA_UART3, - .end = S3C_PA_UART3 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX3, - .end = IRQ_S3CUART_RX3, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX3, - .end = IRQ_S3CUART_TX3, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR3, - .end = IRQ_S3CUART_ERR3, - .flags = IORESOURCE_IRQ, - }, -}; - - -struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { - [0] = { - .resources = s5pc1xx_uart0_resource, - .nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource), - }, - [1] = { - .resources = s5pc1xx_uart1_resource, - .nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource), - }, - [2] = { - .resources = s5pc1xx_uart2_resource, - .nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource), - }, - [3] = { - .resources = s5pc1xx_uart3_resource, - .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), - }, -}; diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h deleted file mode 100644 index 33ad267e8477..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h +++ /dev/null @@ -1,44 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h - * - * Copyright 2009 Samsung Electronics Co. - * - * External Interrupt (GPH0 ~ GPH3) control register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0) -#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4) -#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8) -#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC) -#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4)) - -#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80) -#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84) -#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88) -#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C) -#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90) -#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94) -#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98) -#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C) -#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4)) - -#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100) -#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104) -#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108) -#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C) -#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4)) - -#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140) -#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144) -#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148) -#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C) -#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4)) - -#define S5PC1XX_WKUP_INT_LOWLEV (0x00) -#define S5PC1XX_WKUP_INT_HILEV (0x01) -#define S5PC1XX_WKUP_INT_FALLEDGE (0x02) -#define S5PC1XX_WKUP_INT_RISEEDGE (0x03) -#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04) diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h deleted file mode 100644 index 409c804315e8..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ /dev/null @@ -1,198 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC1XX - Common IRQ support - * - * Based on plat-s3c64xx/include/plat/irqs.h - */ - -#ifndef __ASM_PLAT_S5PC1XX_IRQS_H -#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - * note, since we're using the VICs, our start must be a - * mulitple of 32 to allow the common code to work - */ - -#define S3C_IRQ_OFFSET (32) - -#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) - -#define S3C_VIC0_BASE S3C_IRQ(0) -#define S3C_VIC1_BASE S3C_IRQ(32) -#define S3C_VIC2_BASE S3C_IRQ(64) - -/* UART interrupts, each UART has 4 intterupts per channel so - * use the space between the ISA and S3C main interrupts. Note, these - * are not in the same order as the S3C24XX series! */ - -#define IRQ_S3CUART_BASE0 (16) -#define IRQ_S3CUART_BASE1 (20) -#define IRQ_S3CUART_BASE2 (24) -#define IRQ_S3CUART_BASE3 (28) - -#define UART_IRQ_RXD (0) -#define UART_IRQ_ERR (1) -#define UART_IRQ_TXD (2) -#define UART_IRQ_MODEM (3) - -#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) - -/* VIC based IRQs */ - -#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) -#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) -#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x)) - -/* - * VIC0: system, DMA, timer - */ -#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0) -#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1) -#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2) -#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3) -#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4) -#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5) -#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6) -#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7) -#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8) -#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9) -#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10) -#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11) -#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12) -#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13) -#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14) -#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15) -#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16) -#define IRQ_BATF S5PC1XX_IRQ_VIC0(17) -#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) -#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) -#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) -#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21) -#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22) -#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23) -#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24) -#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25) -#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) -#define IRQ_WDT S5PC1XX_IRQ_VIC0(27) -#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) -#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29) -#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30) - -/* - * VIC1: ARM, power, memory, connectivity - */ -#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0) -#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1) -#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2) -#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3) -#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4) -#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5) -#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6) -#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7) -#define IRQ_NFC S5PC1XX_IRQ_VIC1(8) -#define IRQ_CFC S5PC1XX_IRQ_VIC1(9) -#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10) -#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11) -#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12) -#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13) -#define IRQ_IIC S5PC1XX_IRQ_VIC1(14) -#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15) -#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16) -#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17) -#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18) -#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19) -#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20) -#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21) -#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22) -#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23) -#define IRQ_OTG S5PC1XX_IRQ_VIC1(24) -#define IRQ_MSM S5PC1XX_IRQ_VIC1(25) -#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26) -#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27) -#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28) -#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29) -#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30) - -/* - * VIC2: multimedia, audio, security - */ -#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0) -#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1) -#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2) -#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3) -#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4) -#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5) -#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6) -#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7) -#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8) -#define IRQ_2D S5PC1XX_IRQ_VIC2(9) -#define IRQ_3D S5PC1XX_IRQ_VIC2(10) -#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11) -#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12) -#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13) -#define IRQ_MFC S5PC1XX_IRQ_VIC2(14) -#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15) -#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16) -#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17) -#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18) -#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19) -#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20) -#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21) -#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22) -#define IRQ_ADC S5PC1XX_IRQ_VIC2(23) -#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24) -#define IRQ_TC IRQ_PENDN -#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25) -#define IRQ_CG S5PC1XX_IRQ_VIC2(26) -#define IRQ_SEC S5PC1XX_IRQ_VIC2(27) -#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28) -#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29) -#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) -#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) - -#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x)) -#define IRQ_TIMER0 IRQ_TIMER(0) -#define IRQ_TIMER1 IRQ_TIMER(1) -#define IRQ_TIMER2 IRQ_TIMER(2) -#define IRQ_TIMER3 IRQ_TIMER(3) -#define IRQ_TIMER4 IRQ_TIMER(4) - -/* External interrupt */ -#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6) - -#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) -#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) -#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0)) - -/* GPIO interrupt */ -#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) -#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) - -/* - * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs - */ -#define NR_IRQS (S3C_IRQ_GPIO(320) + 1) - -#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ - diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h deleted file mode 100644 index 21afef1573e7..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/pll.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/plat-s5pc1xx/include/plat/pll.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC1XX PLL code - * - * Based on plat-s3c64xx/include/plat/pll.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) -#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) -#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) -#define S5P_PLL_MDIV_SHIFT (16) -#define S5P_PLL_PDIV_SHIFT (8) -#define S5P_PLL_SDIV_SHIFT (0) - -#include <asm/div64.h> - -static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk, - u32 pllcon) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK; - pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK; - sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h deleted file mode 100644 index 24dec4e52538..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ /dev/null @@ -1,252 +0,0 @@ -/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC1XX clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_CLOCK_H -#define __PLAT_REGS_CLOCK_H __FILE__ - -#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x)) -#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x)) - -/* s5pc100 register for clock */ -#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00) -#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04) -#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08) -#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C) - -#define S5PC100_APLL_CON S5PC100_CLKREG(0x100) -#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104) -#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108) -#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C) - -#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200) -#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204) -#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208) -#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C) - -#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300) -#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304) -#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308) -#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C) -#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310) - -#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400) - -#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500) -#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504) -#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508) - -#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520) -#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524) -#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528) -#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C) -#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530) -#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534) - -#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540) - -#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560) -#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564) - -/* EPLL_CON */ -#define S5PC100_EPLL_EN (1<<31) -#define S5PC100_EPLL_MASK 0xffffffff -#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) - -/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ -#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) -#define S5PC100_CLKSRC1_CLK48M_SHIFT (24) - -/* CLKDIV0 */ -#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) -#define S5PC100_CLKDIV0_APLL_SHIFT (0) -#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) -#define S5PC100_CLKDIV0_ARM_SHIFT (4) -#define S5PC100_CLKDIV0_D0_MASK (0x7<<8) -#define S5PC100_CLKDIV0_D0_SHIFT (8) -#define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12) -#define S5PC100_CLKDIV0_PCLKD0_SHIFT (12) -#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) -#define S5PC100_CLKDIV0_SECSS_SHIFT (16) - -/* CLKDIV1 (OneNAND clock only used in one place, removed) */ -#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) -#define S5PC100_CLKDIV1_APLL2_SHIFT (0) -#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) -#define S5PC100_CLKDIV1_MPLL_SHIFT (4) -#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) -#define S5PC100_CLKDIV1_MPLL2_SHIFT (8) -#define S5PC100_CLKDIV1_D1_MASK (0x7<<12) -#define S5PC100_CLKDIV1_D1_SHIFT (12) -#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) -#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) -#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) -#define S5PC100_CLKDIV1_CAM_SHIFT (24) - -/* CLKDIV2 => removed in clksrc update */ -/* CLKDIV3 => removed in clksrc update, or not needed */ -/* CLKDIV4 => removed in clksrc update, or not needed */ - -/* HCLKD0/PCLKD0 Clock Gate 0 Registers */ -#define S5PC100_CLKGATE_D00_INTC (1<<0) -#define S5PC100_CLKGATE_D00_TZIC (1<<1) -#define S5PC100_CLKGATE_D00_CFCON (1<<2) -#define S5PC100_CLKGATE_D00_MDMA (1<<3) -#define S5PC100_CLKGATE_D00_G2D (1<<4) -#define S5PC100_CLKGATE_D00_SECSS (1<<5) -#define S5PC100_CLKGATE_D00_CSSYS (1<<6) - -/* HCLKD0/PCLKD0 Clock Gate 1 Registers */ -#define S5PC100_CLKGATE_D01_DMC (1<<0) -#define S5PC100_CLKGATE_D01_SROMC (1<<1) -#define S5PC100_CLKGATE_D01_ONENAND (1<<2) -#define S5PC100_CLKGATE_D01_NFCON (1<<3) -#define S5PC100_CLKGATE_D01_INTMEM (1<<4) -#define S5PC100_CLKGATE_D01_EBI (1<<5) - -/* PCLKD0 Clock Gate 2 Registers */ -#define S5PC100_CLKGATE_D02_SECKEY (1<<1) -#define S5PC100_CLKGATE_D02_SDM (1<<2) - -/* HCLKD1/PCLKD1 Clock Gate 0 Registers */ -#define S5PC100_CLKGATE_D10_PDMA0 (1<<0) -#define S5PC100_CLKGATE_D10_PDMA1 (1<<1) -#define S5PC100_CLKGATE_D10_USBHOST (1<<2) -#define S5PC100_CLKGATE_D10_USBOTG (1<<3) -#define S5PC100_CLKGATE_D10_MODEMIF (1<<4) -#define S5PC100_CLKGATE_D10_HSMMC0 (1<<5) -#define S5PC100_CLKGATE_D10_HSMMC1 (1<<6) -#define S5PC100_CLKGATE_D10_HSMMC2 (1<<7) - -/* HCLKD1/PCLKD1 Clock Gate 1 Registers */ -#define S5PC100_CLKGATE_D11_LCD (1<<0) -#define S5PC100_CLKGATE_D11_ROTATOR (1<<1) -#define S5PC100_CLKGATE_D11_FIMC0 (1<<2) -#define S5PC100_CLKGATE_D11_FIMC1 (1<<3) -#define S5PC100_CLKGATE_D11_FIMC2 (1<<4) -#define S5PC100_CLKGATE_D11_JPEG (1<<5) -#define S5PC100_CLKGATE_D11_DSI (1<<6) -#define S5PC100_CLKGATE_D11_CSI (1<<7) -#define S5PC100_CLKGATE_D11_G3D (1<<8) - -/* HCLKD1/PCLKD1 Clock Gate 2 Registers */ -#define S5PC100_CLKGATE_D12_TV (1<<0) -#define S5PC100_CLKGATE_D12_VP (1<<1) -#define S5PC100_CLKGATE_D12_MIXER (1<<2) -#define S5PC100_CLKGATE_D12_HDMI (1<<3) -#define S5PC100_CLKGATE_D12_MFC (1<<4) - -/* HCLKD1/PCLKD1 Clock Gate 3 Registers */ -#define S5PC100_CLKGATE_D13_CHIPID (1<<0) -#define S5PC100_CLKGATE_D13_GPIO (1<<1) -#define S5PC100_CLKGATE_D13_APC (1<<2) -#define S5PC100_CLKGATE_D13_IEC (1<<3) -#define S5PC100_CLKGATE_D13_PWM (1<<6) -#define S5PC100_CLKGATE_D13_SYSTIMER (1<<7) -#define S5PC100_CLKGATE_D13_WDT (1<<8) -#define S5PC100_CLKGATE_D13_RTC (1<<9) - -/* HCLKD1/PCLKD1 Clock Gate 4 Registers */ -#define S5PC100_CLKGATE_D14_UART0 (1<<0) -#define S5PC100_CLKGATE_D14_UART1 (1<<1) -#define S5PC100_CLKGATE_D14_UART2 (1<<2) -#define S5PC100_CLKGATE_D14_UART3 (1<<3) -#define S5PC100_CLKGATE_D14_IIC (1<<4) -#define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5) -#define S5PC100_CLKGATE_D14_SPI0 (1<<6) -#define S5PC100_CLKGATE_D14_SPI1 (1<<7) -#define S5PC100_CLKGATE_D14_SPI2 (1<<8) -#define S5PC100_CLKGATE_D14_IRDA (1<<9) -#define S5PC100_CLKGATE_D14_CCAN0 (1<<10) -#define S5PC100_CLKGATE_D14_CCAN1 (1<<11) -#define S5PC100_CLKGATE_D14_HSITX (1<<12) -#define S5PC100_CLKGATE_D14_HSIRX (1<<13) - -/* HCLKD1/PCLKD1 Clock Gate 5 Registers */ -#define S5PC100_CLKGATE_D15_IIS0 (1<<0) -#define S5PC100_CLKGATE_D15_IIS1 (1<<1) -#define S5PC100_CLKGATE_D15_IIS2 (1<<2) -#define S5PC100_CLKGATE_D15_AC97 (1<<3) -#define S5PC100_CLKGATE_D15_PCM0 (1<<4) -#define S5PC100_CLKGATE_D15_PCM1 (1<<5) -#define S5PC100_CLKGATE_D15_SPDIF (1<<6) -#define S5PC100_CLKGATE_D15_TSADC (1<<7) -#define S5PC100_CLKGATE_D15_KEYIF (1<<8) -#define S5PC100_CLKGATE_D15_CG (1<<9) - -/* HCLKD2 Clock Gate 0 Registers */ -#define S5PC100_CLKGATE_D20_HCLKD2 (1<<0) -#define S5PC100_CLKGATE_D20_I2SD2 (1<<1) - -/* Special Clock Gate 0 Registers */ -#define S5PC100_CLKGATE_SCLK0_HPM (1<<0) -#define S5PC100_CLKGATE_SCLK0_PWI (1<<1) -#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) -#define S5PC100_CLKGATE_SCLK0_UART (1<<3) -#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) -#define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5) -#define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6) -#define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7) -#define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8) -#define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9) -#define S5PC100_CLKGATE_SCLK0_IRDA (1<<10) -#define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11) -#define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12) -#define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13) -#define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14) -#define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15) -#define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16) -#define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17) - -/* Special Clock Gate 1 Registers */ -#define S5PC100_CLKGATE_SCLK1_LCD (1<<0) -#define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1) -#define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2) -#define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3) -#define S5PC100_CLKGATE_SCLK1_TV54 (1<<4) -#define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5) -#define S5PC100_CLKGATE_SCLK1_MIXER (1<<6) -#define S5PC100_CLKGATE_SCLK1_HDMI (1<<7) -#define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8) -#define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9) -#define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10) -#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) -#define S5PC100_CLKGATE_SCLK1_CAM (1<<12) - -#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000) -#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008) -#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100) -#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104) -#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200) -#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300) -#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304) -#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308) -#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400) -#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414) -#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420) - -#define S5PC100_SWRESET_RESETVAL 0xc100 -#define S5PC100_OTHER_SYS_INT 24 -#define S5PC100_OTHER_STA_TYPE 23 -#define STA_TYPE_EXPON 0 -#define STA_TYPE_SFR 1 - -#define S5PC100_SLEEP_CFG_OSC_EN 0 - -/* OTHERS Resgister */ -#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) -#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) - -/* MIPI D-PHY Control Register 0 */ -#define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1) -#define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0) - -#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h deleted file mode 100644 index 02ffa491b53a..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h +++ /dev/null @@ -1,84 +0,0 @@ -/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h - * - * Copyright 2009 Samsung Electronics Co. - * Jongse Won <jongse.won@samsung.com> - * - * S5PC1XX clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARM_REGS_PWR -#define __ASM_ARM_REGS_PWR __FILE__ - -#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x)) - -/* s5pc100 (0xE0108000) register for power management */ -#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0) -#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4) -#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10) -#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14) -#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18) -#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C) -#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100) -#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104) -#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108) -#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110) -#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114) -#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200) -#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300) -#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304) -#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308) -#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400) -#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404) -#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408) -#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C) -#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410) -#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414) -#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418) -#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C) -#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500) -#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504) -#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508) -#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C) -#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510) -#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514) -#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518) -#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C) -#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520) -#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600) -#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604) -#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608) -#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C) -#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610) -#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614) -#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618) -#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C) -#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620) -#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700) -#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704) -#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708) -#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C) -#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710) -#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714) -#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718) -#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C) -#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724) - -/* PWR_CFG */ -#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31) -#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5) -#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5) -#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5) -#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5) -#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5) - -/* SLEEP_CFG */ -#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0) - -/* OTHERS */ -#define S5PC100_PMU_INT_DISABLE (1 << 24) - -#endif /* __ASM_ARM_REGS_PWR */ diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h deleted file mode 100644 index 2531f34a56f3..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h +++ /dev/null @@ -1,64 +0,0 @@ -/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * Header file for s5pc100 cpu support - * - * Based on plat-s3c64xx/include/plat/s3c6400.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Common init code for S5PC100 related SoCs */ -extern int s5pc100_init(void); -extern void s5pc100_map_io(void); -extern void s5pc100_init_clocks(int xtal); -extern int s5pc100_register_baseclocks(unsigned long xtal); -extern void s5pc100_init_irq(void); -extern void s5pc100_init_io(struct map_desc *mach_desc, int size); -extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s5pc100_register_clocks(void); -extern void s5pc100_setup_clocks(void); -extern struct sysdev_class s5pc100_sysclass; - -#define s5pc100_init_uarts s5pc100_common_init_uarts - -/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */ -extern void s5pc1xx_init_irq(u32 *vic_valid, int num); -extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size); - -/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */ -extern struct clk clk_hpll; -extern struct clk clk_hd0; -extern struct clk clk_pd0; -extern struct clk clk_54m; -extern void s5pc1xx_register_clocks(void); -extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable); -extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable); - -/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ -extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; -extern struct platform_device s3c_device_g2d; -extern struct platform_device s3c_device_g3d; -extern struct platform_device s3c_device_vpp; -extern struct platform_device s3c_device_tvenc; -extern struct platform_device s3c_device_tvscaler; -extern struct platform_device s3c_device_rotator; -extern struct platform_device s3c_device_jpeg; -extern struct platform_device s3c_device_onenand; -extern struct platform_device s3c_device_usb_otghcd; -extern struct platform_device s3c_device_keypad; -extern struct platform_device s3c_device_ts; -extern struct platform_device s3c_device_g3d; -extern struct platform_device s3c_device_smc911x; -extern struct platform_device s3c_device_fimc0; -extern struct platform_device s3c_device_fimc1; -extern struct platform_device s3c_device_mfc; -extern struct platform_device s3c_device_ac97; -extern struct platform_device s3c_device_fimc0; -extern struct platform_device s3c_device_fimc1; -extern struct platform_device s3c_device_fimc2; - diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c deleted file mode 100644 index 373122f57d56..000000000000 --- a/arch/arm/plat-s5pc1xx/irq-eint.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * linux/arch/arm/plat-s5pc1xx/irq-eint.c - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * Kyungin Park <kyungmin.park@samsung.com> - * - * Based on plat-s3c64xx/irq-eint.c - * - * S5PC1XX - Interrupt handling for IRQ_EINT(x) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/sysdev.h> -#include <linux/pm.h> -#include <linux/gpio.h> - -#include <asm/hardware/vic.h> - -#include <mach/map.h> - -#include <plat/gpio-cfg.h> -#include <plat/gpio-ext.h> -#include <plat/pm.h> -#include <plat/regs-gpio.h> -#include <plat/regs-irqtype.h> - -/* - * bank is a group of external interrupt - * bank0 means EINT0 ... EINT7 - * bank1 means EINT8 ... EINT15 - * bank2 means EINT16 ... EINT23 - * bank3 means EINT24 ... EINT31 - */ - -static inline int s3c_get_eint(unsigned int irq) -{ - int real; - - if (irq < IRQ_EINT16_31) - real = (irq - IRQ_EINT0); - else - real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0; - - return real; -} - -static inline int s3c_get_bank(unsigned int irq) -{ - return s3c_get_eint(irq) >> 3; -} - -static inline int s3c_eint_to_bit(unsigned int irq) -{ - int real, bit; - - real = s3c_get_eint(irq); - bit = 1 << (real & (8 - 1)); - - return bit; -} - -static inline void s3c_irq_eint_mask(unsigned int irq) -{ - u32 mask; - u32 bank = s3c_get_bank(irq); - - mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); - mask |= s3c_eint_to_bit(irq); - __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); -} - -static void s3c_irq_eint_unmask(unsigned int irq) -{ - u32 mask; - u32 bank = s3c_get_bank(irq); - - mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); - mask &= ~(s3c_eint_to_bit(irq)); - __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); -} - -static inline void s3c_irq_eint_ack(unsigned int irq) -{ - u32 bank = s3c_get_bank(irq); - - __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank)); -} - -static void s3c_irq_eint_maskack(unsigned int irq) -{ - /* compiler should in-line these */ - s3c_irq_eint_mask(irq); - s3c_irq_eint_ack(irq); -} - -static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) -{ - u32 bank = s3c_get_bank(irq); - int real = s3c_get_eint(irq); - int gpio, shift, sfn; - u32 ctrl, con = 0; - - switch (type) { - case IRQ_TYPE_NONE: - printk(KERN_WARNING "No edge setting!\n"); - break; - - case IRQ_TYPE_EDGE_RISING: - con = S5PC1XX_WKUP_INT_RISEEDGE; - break; - - case IRQ_TYPE_EDGE_FALLING: - con = S5PC1XX_WKUP_INT_FALLEDGE; - break; - - case IRQ_TYPE_EDGE_BOTH: - con = S5PC1XX_WKUP_INT_BOTHEDGE; - break; - - case IRQ_TYPE_LEVEL_LOW: - con = S5PC1XX_WKUP_INT_LOWLEV; - break; - - case IRQ_TYPE_LEVEL_HIGH: - con = S5PC1XX_WKUP_INT_HILEV; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -EINVAL; - } - - gpio = real & (8 - 1); - shift = gpio << 2; - - ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank)); - ctrl &= ~(0x7 << shift); - ctrl |= con << shift; - __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank)); - - switch (real) { - case 0 ... 7: - gpio = S5PC100_GPH0(gpio); - break; - case 8 ... 15: - gpio = S5PC100_GPH1(gpio); - break; - case 16 ... 23: - gpio = S5PC100_GPH2(gpio); - break; - case 24 ... 31: - gpio = S5PC100_GPH3(gpio); - break; - default: - return -EINVAL; - } - - sfn = S3C_GPIO_SFN(0x2); - s3c_gpio_cfgpin(gpio, sfn); - - return 0; -} - -static struct irq_chip s3c_irq_eint = { - .name = "EINT", - .mask = s3c_irq_eint_mask, - .unmask = s3c_irq_eint_unmask, - .mask_ack = s3c_irq_eint_maskack, - .ack = s3c_irq_eint_ack, - .set_type = s3c_irq_eint_set_type, - .set_wake = s3c_irqext_wake, -}; - -/* s3c_irq_demux_eint - * - * This function demuxes the IRQ from external interrupts, - * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into - * the specific handlers s3c_irq_demux_eintX_Y. - */ -static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) -{ - u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3))); - u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3))); - unsigned int irq; - - status &= ~mask; - status &= (1 << (end - start + 1)) - 1; - - for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { - if (status & 1) - generic_handle_irq(irq); - - status >>= 1; - } -} - -static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_eint(16, 23); - s3c_irq_demux_eint(24, 31); -} - -/* - * Handle EINT0 ... EINT15 at VIC directly - */ -static void s3c_irq_vic_eint_mask(unsigned int irq) -{ - void __iomem *base = get_irq_chip_data(irq); - unsigned int real; - - s3c_irq_eint_mask(irq); - real = s3c_get_eint(irq); - writel(1 << real, base + VIC_INT_ENABLE_CLEAR); -} - -static void s3c_irq_vic_eint_unmask(unsigned int irq) -{ - void __iomem *base = get_irq_chip_data(irq); - unsigned int real; - - s3c_irq_eint_unmask(irq); - real = s3c_get_eint(irq); - writel(1 << real, base + VIC_INT_ENABLE); -} - -static inline void s3c_irq_vic_eint_ack(unsigned int irq) -{ - u32 bit; - u32 bank = s3c_get_bank(irq); - - bit = s3c_eint_to_bit(irq); - __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank)); -} - -static void s3c_irq_vic_eint_maskack(unsigned int irq) -{ - /* compiler should in-line these */ - s3c_irq_vic_eint_mask(irq); - s3c_irq_vic_eint_ack(irq); -} - -static struct irq_chip s3c_irq_vic_eint = { - .name = "EINT", - .mask = s3c_irq_vic_eint_mask, - .unmask = s3c_irq_vic_eint_unmask, - .mask_ack = s3c_irq_vic_eint_maskack, - .ack = s3c_irq_vic_eint_ack, - .set_type = s3c_irq_eint_set_type, - .set_wake = s3c_irqext_wake, -}; - -static int __init s5pc1xx_init_irq_eint(void) -{ - int irq; - - for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) { - set_irq_chip(irq, &s3c_irq_vic_eint); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { - set_irq_chip(irq, &s3c_irq_eint); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31); - - return 0; -} - -arch_initcall(s5pc1xx_init_irq_eint); diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c deleted file mode 100644 index bfc524827819..000000000000 --- a/arch/arm/plat-s5pc1xx/irq.c +++ /dev/null @@ -1,75 +0,0 @@ -/* arch/arm/plat-s5pc1xx/irq.c - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC1XX - Interrupt handling - * - * Based on plat-s3c64xx/irq.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <asm/hardware/vic.h> - -#include <mach/map.h> -#include <plat/irq-vic-timer.h> -#include <plat/irq-uart.h> -#include <plat/cpu.h> - -/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] - * are consecutive when looking up the interrupt in the demux routines. - */ -static struct s3c_uart_irq uart_irqs[] = { - [0] = { - .regs = (void *)S3C_VA_UART0, - .base_irq = IRQ_S3CUART_BASE0, - .parent_irq = IRQ_UART0, - }, - [1] = { - .regs = (void *)S3C_VA_UART1, - .base_irq = IRQ_S3CUART_BASE1, - .parent_irq = IRQ_UART1, - }, - [2] = { - .regs = (void *)S3C_VA_UART2, - .base_irq = IRQ_S3CUART_BASE2, - .parent_irq = IRQ_UART2, - }, - [3] = { - .regs = (void *)S3C_VA_UART3, - .base_irq = IRQ_S3CUART_BASE3, - .parent_irq = IRQ_UART3, - }, -}; - -void __init s5pc1xx_init_irq(u32 *vic_valid, int num) -{ - int i; - - printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); - - /* initialise the pair of VICs */ - for (i = 0; i < num; i++) - vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET), - vic_valid[i], 0); - - /* add the timer sub-irqs */ - - s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); - s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); - s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); - s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); - s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); - - s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); -} - - diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c deleted file mode 100644 index 2bf6c57a96a2..000000000000 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ /dev/null @@ -1,876 +0,0 @@ -/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c - * - * Copyright 2009 Samsung Electronics, Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC100 based common clock support - * - * Based on plat-s3c64xx/s3c6400-clock.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/sysdev.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> - -#include <plat/cpu-freq.h> - -#include <plat/regs-clock.h> -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/cpu.h> -#include <plat/pll.h> -#include <plat/devs.h> -#include <plat/s5pc100.h> - -/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call - * ext_xtal_mux for want of an actual name from the manual. -*/ - -static struct clk clk_ext_xtal_mux = { - .name = "ext_xtal", - .id = -1, -}; - -#define clk_fin_apll clk_ext_xtal_mux -#define clk_fin_mpll clk_ext_xtal_mux -#define clk_fin_epll clk_ext_xtal_mux -#define clk_fin_hpll clk_ext_xtal_mux - -#define clk_fout_mpll clk_mpll -#define clk_vclk_54m clk_54m - -/* APLL */ -static struct clk clk_fout_apll = { - .name = "fout_apll", - .id = -1, - .rate = 27000000, -}; - -static struct clk *clk_src_apll_list[] = { - [0] = &clk_fin_apll, - [1] = &clk_fout_apll, -}; - -static struct clksrc_sources clk_src_apll = { - .sources = clk_src_apll_list, - .nr_sources = ARRAY_SIZE(clk_src_apll_list), -}; - -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", - .id = -1, - }, - .sources = &clk_src_apll, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, }, -}; - -static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK; - ratio >>= S5PC100_CLKDIV0_APLL_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_apll = { - .name = "dout_apll", - .id = -1, - .parent = &clk_mout_apll.clk, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_apll_get_rate, - }, -}; - -static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK; - ratio >>= S5PC100_CLKDIV0_ARM_SHIFT; - - return rate / (ratio + 1); -} - -static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - - if (parent < rate) - return rate; - - div = (parent / rate) - 1; - if (div > S5PC100_CLKDIV0_ARM_MASK) - div = S5PC100_CLKDIV0_ARM_MASK; - - return parent / (div + 1); -} - -static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - u32 div; - u32 val; - - if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1)) - return -EINVAL; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - - val = __raw_readl(S5PC100_CLKDIV0); - val &= S5PC100_CLKDIV0_ARM_MASK; - val |= (div - 1); - __raw_writel(val, S5PC100_CLKDIV0); - - return 0; -} - -static struct clk clk_arm = { - .name = "armclk", - .id = -1, - .parent = &clk_dout_apll, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_arm_get_rate, - .set_rate = s5pc100_clk_arm_set_rate, - .round_rate = s5pc100_clk_arm_round_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK; - ratio >>= S5PC100_CLKDIV0_D0_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_d0_bus = { - .name = "dout_d0_bus", - .id = -1, - .parent = &clk_arm, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_d0_bus_get_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK; - ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_pclkd0 = { - .name = "dout_pclkd0", - .id = -1, - .parent = &clk_dout_d0_bus, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_pclkd0_get_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK; - ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_apll2 = { - .name = "dout_apll2", - .id = -1, - .parent = &clk_mout_apll.clk, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_apll2_get_rate, - }, -}; - -/* MPLL */ -static struct clk *clk_src_mpll_list[] = { - [0] = &clk_fin_mpll, - [1] = &clk_fout_mpll, -}; - -static struct clksrc_sources clk_src_mpll = { - .sources = clk_src_mpll_list, - .nr_sources = ARRAY_SIZE(clk_src_mpll_list), -}; - -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", - .id = -1, - }, - .sources = &clk_src_mpll, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, }, -}; - -static struct clk *clkset_am_list[] = { - [0] = &clk_mout_mpll.clk, - [1] = &clk_dout_apll2, -}; - -static struct clksrc_sources clk_src_am = { - .sources = clkset_am_list, - .nr_sources = ARRAY_SIZE(clkset_am_list), -}; - -static struct clksrc_clk clk_mout_am = { - .clk = { - .name = "mout_am", - .id = -1, - }, - .sources = &clk_src_am, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, }, -}; - -static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK; - ratio >>= S5PC100_CLKDIV1_D1_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_d1_bus = { - .name = "dout_d1_bus", - .id = -1, - .parent = &clk_mout_am.clk, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_d1_bus_get_rate, - }, -}; - -static struct clk *clkset_onenand_list[] = { - [0] = &clk_dout_d0_bus, - [1] = &clk_dout_d1_bus, -}; - -static struct clksrc_sources clk_src_onenand = { - .sources = clkset_onenand_list, - .nr_sources = ARRAY_SIZE(clkset_onenand_list), -}; - -static struct clksrc_clk clk_mout_onenand = { - .clk = { - .name = "mout_onenand", - .id = -1, - }, - .sources = &clk_src_onenand, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, }, -}; - -static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK; - ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_pclkd1 = { - .name = "dout_pclkd1", - .id = -1, - .parent = &clk_dout_d1_bus, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_pclkd1_get_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; - ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_mpll2 = { - .name = "dout_mpll2", - .id = -1, - .parent = &clk_mout_am.clk, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_mpll2_get_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK; - ratio >>= S5PC100_CLKDIV1_CAM_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_cam = { - .name = "dout_cam", - .id = -1, - .parent = &clk_dout_mpll2, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_cam_get_rate, - }, -}; - -static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned int ratio; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; - ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT; - - return rate / (ratio + 1); -} - -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .id = -1, - .parent = &clk_mout_am.clk, - .ops = &(struct clk_ops) { - .get_rate = s5pc100_clk_dout_mpll_get_rate, - }, -}; - -/* EPLL */ -static struct clk clk_fout_epll = { - .name = "fout_epll", - .id = -1, -}; - -static struct clk *clk_src_epll_list[] = { - [0] = &clk_fin_epll, - [1] = &clk_fout_epll, -}; - -static struct clksrc_sources clk_src_epll = { - .sources = clk_src_epll_list, - .nr_sources = ARRAY_SIZE(clk_src_epll_list), -}; - -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", - .id = -1, - }, - .sources = &clk_src_epll, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, }, -}; - -/* HPLL */ -static struct clk clk_fout_hpll = { - .name = "fout_hpll", - .id = -1, -}; - -static struct clk *clk_src_hpll_list[] = { - [0] = &clk_27m, - [1] = &clk_fout_hpll, -}; - -static struct clksrc_sources clk_src_hpll = { - .sources = clk_src_hpll_list, - .nr_sources = ARRAY_SIZE(clk_src_hpll_list), -}; - -static struct clksrc_clk clk_mout_hpll = { - .clk = { - .name = "mout_hpll", - .id = -1, - }, - .sources = &clk_src_hpll, - .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, }, -}; - -/* Peripherals */ -/* - * The peripheral clocks are all controlled via clocksource followed - * by an optional divider and gate stage. We currently roll this into - * one clock which hides the intermediate clock from the mux. - * - * Note, the JPEG clock can only be an even divider... - * - * The scaler and LCD clocks depend on the S5PC100 version, and also - * have a common parent divisor so are not included here. - */ - -static struct clk clk_iis_cd0 = { - .name = "iis_cdclk0", - .id = -1, -}; - -static struct clk clk_iis_cd1 = { - .name = "iis_cdclk1", - .id = -1, -}; - -static struct clk clk_iis_cd2 = { - .name = "iis_cdclk2", - .id = -1, -}; - -static struct clk clk_pcm_cd0 = { - .name = "pcm_cdclk0", - .id = -1, -}; - -static struct clk clk_pcm_cd1 = { - .name = "pcm_cdclk1", - .id = -1, -}; - -static struct clk *clkset_audio0_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd0, - &clk_pcm_cd0, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio0 = { - .sources = clkset_audio0_list, - .nr_sources = ARRAY_SIZE(clkset_audio0_list), -}; - -static struct clk *clkset_spi_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll2, - &clk_fin_epll, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_spi = { - .sources = clkset_spi_list, - .nr_sources = ARRAY_SIZE(clkset_spi_list), -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, -}; - -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; - -static struct clk *clkset_audio1_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd1, - &clk_pcm_cd1, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio1 = { - .sources = clkset_audio1_list, - .nr_sources = ARRAY_SIZE(clkset_audio1_list), -}; - -static struct clk *clkset_audio2_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_iis_cd2, - &clk_mout_hpll.clk, -}; - -static struct clksrc_sources clkset_audio2 = { - .sources = clkset_audio2_list, - .nr_sources = ARRAY_SIZE(clkset_audio2_list), -}; - -static struct clksrc_clk clksrc_audio[] = { - { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio0, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, - }, { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio1, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, - }, { - .clk = { - .name = "audio-bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_audio2, - .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, - }, -}; - -static struct clk *clkset_spdif_list[] = { - &clksrc_audio[0].clk, - &clksrc_audio[1].clk, - &clksrc_audio[2].clk, -}; - -static struct clksrc_sources clkset_spdif = { - .sources = clkset_spdif_list, - .nr_sources = ARRAY_SIZE(clkset_spdif_list), -}; - -static struct clk *clkset_lcd_fimc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_mout_hpll.clk, - &clk_vclk_54m, -}; - -static struct clksrc_sources clkset_lcd_fimc = { - .sources = clkset_lcd_fimc_list, - .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), -}; - -static struct clk *clkset_mmc_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_fin_epll, - &clk_mout_hpll.clk , -}; - -static struct clksrc_sources clkset_mmc = { - .sources = clkset_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_mmc_list), -}; - -static struct clk *clkset_usbhost_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - &clk_mout_hpll.clk, - &clk_48m, -}; - -static struct clksrc_sources clkset_usbhost = { - .sources = clkset_usbhost_list, - .nr_sources = ARRAY_SIZE(clkset_usbhost_list), -}; - -static struct clksrc_clk clksrc_clks[] = { - { - .clk = { - .name = "spi_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, - }, { - .clk = { - .name = "spi_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, - }, { - .clk = { - .name = "spi_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_spi, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, - }, { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_uart, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, - }, { - .clk = { - .name = "spdif", - .id = -1, - }, - .sources = &clkset_spdif, - .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, - }, { - .clk = { - .name = "lcd", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, - }, { - .clk = { - .name = "fimc", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, - }, { - .clk = { - .name = "fimc", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, - }, { - .clk = { - .name = "fimc", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, - .enable = s5pc100_sclk1_ctrl, - }, - .sources = &clkset_lcd_fimc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, - }, { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, - }, { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, - }, { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_mmc, - .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, - }, { - .clk = { - .name = "usbhost", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, - .enable = s5pc100_sclk0_ctrl, - }, - .sources = &clkset_usbhost, - .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, - .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, - } -}; - -/* Clock initialisation code */ - -static struct clksrc_clk *init_parents[] = { - &clk_mout_apll, - &clk_mout_mpll, - &clk_mout_am, - &clk_mout_onenand, - &clk_mout_epll, - &clk_mout_hpll, -}; - -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - -void __init_or_cpufreq s5pc100_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long xtal; - unsigned long armclk; - unsigned long hclkd0; - unsigned long hclk; - unsigned long pclkd0; - unsigned long pclk; - unsigned long apll, mpll, epll, hpll; - unsigned int ptr; - u32 clkdiv0, clkdiv1; - - printk(KERN_DEBUG "%s: registering clocks\n", __func__); - - clkdiv0 = __raw_readl(S5PC100_CLKDIV0); - clkdiv1 = __raw_readl(S5PC100_CLKDIV1); - - printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); - - xtal_clk = clk_get(NULL, "xtal"); - BUG_ON(IS_ERR(xtal_clk)); - - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - - apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON)); - mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON)); - epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); - hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); - - printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz" - ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n", - print_mhz(apll), print_mhz(mpll), - print_mhz(epll), print_mhz(hpll)); - - armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); - armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); - hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); - pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); - hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); - pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); - - printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz," - " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz," - " PCLK=%ld.%03ld MHz\n", - print_mhz(armclk), print_mhz(hclkd0), - print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk)); - - clk_fout_apll.rate = apll; - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_hpll.rate = hpll; - - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = armclk; - - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++) - s3c_set_clksrc(clksrc_audio + ptr, true); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) - s3c_set_clksrc(clksrc_clks + ptr, true); -} - -static struct clk *clks[] __initdata = { - &clk_ext_xtal_mux, - &clk_dout_apll, - &clk_dout_d0_bus, - &clk_dout_pclkd0, - &clk_dout_apll2, - &clk_mout_apll.clk, - &clk_mout_mpll.clk, - &clk_mout_epll.clk, - &clk_mout_hpll.clk, - &clk_mout_am.clk, - &clk_dout_d1_bus, - &clk_mout_onenand.clk, - &clk_dout_pclkd1, - &clk_dout_mpll2, - &clk_dout_cam, - &clk_dout_mpll, - &clk_fout_epll, - &clk_iis_cd0, - &clk_iis_cd1, - &clk_iis_cd2, - &clk_pcm_cd0, - &clk_pcm_cd1, - &clk_arm, -}; - -void __init s5pc100_register_clocks(void) -{ - struct clk *clkp; - int ret; - int ptr; - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio)); - s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); -} diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 229919e9744c..2753fb3e4f73 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -6,7 +6,7 @@ config PLAT_SAMSUNG bool - depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX + depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX select NO_IOPORT default y help @@ -170,6 +170,11 @@ config S3C_DEV_I2C1 help Compile in platform device definitions for I2C channel 1 +config S3C_DEV_I2C2 + bool + help + Compile in platform device definitions for I2C channel 2 + config S3C_DEV_FB bool help @@ -185,11 +190,22 @@ config S3C_DEV_USB_HSOTG help Compile in platform device definition for USB high-speed OtG +config S3C_DEV_WDT + bool + default y if ARCH_S3C2410 + help + Complie in platform device definition for Watchdog Timer + config S3C_DEV_NAND bool help Compile in platform device definition for NAND controller +config S3C_DEV_ONENAND + bool + help + Compile in platform device definition for OneNAND controller + config S3C_DEV_RTC bool help @@ -269,4 +285,12 @@ config SAMSUNG_PM_CHECK_CHUNKSIZE See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> +config SAMSUNG_WAKEMASK + bool + depends on PM + help + Compile support for wakeup-mask controls found on the S3C6400 + and above. This code allows a set of interrupt to wakeup-mask + mappings. See <plat/wakeup-mask.h> + endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 48288499a3b9..b1d82cc5e716 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -36,11 +36,14 @@ obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_S3C_DEV_I2C2) += dev-i2c2.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o obj-y += dev-uart.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o +obj-$(CONFIG_S3C_DEV_WDT) += dev-wdt.o obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o +obj-$(CONFIG_S3C_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o @@ -58,6 +61,8 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm-gpio.o obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o +obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o + # PWM support obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 210030d5cfe1..04d9521ddc9f 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -66,6 +66,7 @@ struct adc_device { struct s3c_adc_client *cur; struct s3c_adc_client *ts_pend; void __iomem *regs; + spinlock_t lock; unsigned int prescale; @@ -74,7 +75,7 @@ struct adc_device { static struct adc_device *adc_dev; -static LIST_HEAD(adc_pending); +static LIST_HEAD(adc_pending); /* protected by adc_device.lock */ #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) @@ -145,7 +146,7 @@ int s3c_adc_start(struct s3c_adc_client *client, if (client->is_ts && adc->ts_pend) return -EAGAIN; - local_irq_save(flags); + spin_lock_irqsave(&adc->lock, flags); client->channel = channel; client->nr_samples = nr_samples; @@ -157,7 +158,8 @@ int s3c_adc_start(struct s3c_adc_client *client, if (!adc->cur) s3c_adc_try(adc); - local_irq_restore(flags); + + spin_unlock_irqrestore(&adc->lock, flags); return 0; } @@ -237,6 +239,10 @@ EXPORT_SYMBOL_GPL(s3c_adc_register); void s3c_adc_release(struct s3c_adc_client *client) { + unsigned long flags; + + spin_lock_irqsave(&adc_dev->lock, flags); + /* We should really check that nothing is in progress. */ if (adc_dev->cur == client) adc_dev->cur = NULL; @@ -255,6 +261,8 @@ void s3c_adc_release(struct s3c_adc_client *client) if (adc_dev->cur == NULL) s3c_adc_try(adc_dev); + + spin_unlock_irqrestore(&adc_dev->lock, flags); kfree(client); } EXPORT_SYMBOL_GPL(s3c_adc_release); @@ -264,7 +272,6 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) struct adc_device *adc = pw; struct s3c_adc_client *client = adc->cur; enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; - unsigned long flags; unsigned data0, data1; if (!client) { @@ -296,12 +303,12 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) client->select_cb(client, 1); s3c_adc_convert(adc); } else { - local_irq_save(flags); + spin_lock(&adc->lock); (client->select_cb)(client, 0); adc->cur = NULL; s3c_adc_try(adc); - local_irq_restore(flags); + spin_unlock(&adc->lock); } exit: @@ -326,6 +333,8 @@ static int s3c_adc_probe(struct platform_device *pdev) return -ENOMEM; } + spin_lock_init(&adc->lock); + adc->pdev = pdev; adc->prescale = S3C2410_ADCCON_PRSCVL(49); @@ -407,13 +416,17 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev) static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) { struct adc_device *adc = platform_get_drvdata(pdev); + unsigned long flags; u32 con; + spin_lock_irqsave(&adc->lock, flags); + con = readl(adc->regs + S3C2410_ADCCON); con |= S3C2410_ADCCON_STDBM; writel(con, adc->regs + S3C2410_ADCCON); disable_irq(adc->irq); + spin_unlock_irqrestore(&adc->lock, flags); clk_disable(adc->clk); return 0; @@ -422,6 +435,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) static int s3c_adc_resume(struct platform_device *pdev) { struct adc_device *adc = platform_get_drvdata(pdev); + unsigned long flags; clk_enable(adc->clk); enable_irq(adc->irq); diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c new file mode 100644 index 000000000000..07036dee09e7 --- /dev/null +++ b/arch/arm/plat-samsung/dev-i2c2.c @@ -0,0 +1,70 @@ +/* linux/arch/arm/plat-s3c/dev-i2c2.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S3C series device definition for i2c device 2 + * + * Based on plat-samsung/dev-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/gfp.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/regs-iic.h> +#include <plat/iic.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +static struct resource s3c_i2c_resource[] = { + [0] = { + .start = S3C_PA_IIC2, + .end = S3C_PA_IIC2 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CAN0, + .end = IRQ_CAN0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_i2c2 = { + .name = "s3c2410-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(s3c_i2c_resource), + .resource = s3c_i2c_resource, +}; + +static struct s3c2410_platform_i2c default_i2c_data2 __initdata = { + .flags = 0, + .bus_num = 2, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, +}; + +void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) + pd = &default_i2c_data2; + + npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c2_cfg_gpio; + + s3c_device_i2c2.dev.platform_data = npd; +} diff --git a/arch/arm/plat-samsung/dev-onenand.c b/arch/arm/plat-samsung/dev-onenand.c new file mode 100644 index 000000000000..45ec73287d8c --- /dev/null +++ b/arch/arm/plat-samsung/dev-onenand.c @@ -0,0 +1,55 @@ +/* + * linux/arch/arm/plat-samsung/dev-onenand.c + * + * Copyright (c) 2008-2010 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * + * S3C64XX/S5PC100 series device definition for OneNAND devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +static struct resource s3c_onenand_resources[] = { + [0] = { + .start = S3C_PA_ONENAND, + .end = S3C_PA_ONENAND + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C_PA_ONENAND_BUF, + .end = S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_ONENAND, + .end = IRQ_ONENAND, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_onenand = { + .name = "samsung-onenand", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_onenand_resources), + .resource = s3c_onenand_resources, +}; + +void s3c_onenand_set_platdata(struct onenand_platform_data *pdata) +{ + struct onenand_platform_data *pd; + + pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); + if (!pd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + s3c_device_onenand.dev.platform_data = pd; +} diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c new file mode 100644 index 000000000000..5efca87cddbd --- /dev/null +++ b/arch/arm/plat-samsung/dev-wdt.c @@ -0,0 +1,40 @@ +/* linux/arch/arm/plat-samsung/dev-wdt.c + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C series device definition for the watchdog timer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/devs.h> + +static struct resource s3c_wdt_resource[] = { + [0] = { + .start = S3C_PA_WDT, + .end = S3C_PA_WDT + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_WDT, + .end = IRQ_WDT, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_wdt = { + .name = "s3c2410-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_wdt_resource), + .resource = s3c_wdt_resource, +}; +EXPORT_SYMBOL(s3c_device_wdt); diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index ef69e56b2885..e6144e4b9118 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -45,6 +45,7 @@ extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; +extern struct platform_device s3c_device_i2c2; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; @@ -57,9 +58,20 @@ extern struct platform_device s3c_device_hsmmc2; extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; +extern struct platform_device s5pc100_device_spi0; +extern struct platform_device s5pc100_device_spi1; +extern struct platform_device s5pc100_device_spi2; +extern struct platform_device s5pv210_device_spi0; +extern struct platform_device s5pv210_device_spi1; +extern struct platform_device s5p6440_device_spi0; +extern struct platform_device s5p6440_device_spi1; + extern struct platform_device s3c_device_hwmon; extern struct platform_device s3c_device_nand; +extern struct platform_device s3c_device_onenand; +extern struct platform_device s3c64xx_device_onenand1; +extern struct platform_device s5pc110_device_onenand; extern struct platform_device s3c_device_usbgadget; extern struct platform_device s3c_device_usb_hsotg; @@ -76,10 +88,18 @@ extern struct platform_device s5p6442_device_pcm0; extern struct platform_device s5p6442_device_pcm1; extern struct platform_device s5p6442_device_iis0; extern struct platform_device s5p6442_device_iis1; +extern struct platform_device s5p6442_device_spi; extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; +extern struct platform_device s5pc100_device_ac97; +extern struct platform_device s5pc100_device_pcm0; +extern struct platform_device s5pc100_device_pcm1; +extern struct platform_device s5pc100_device_iis0; +extern struct platform_device s5pc100_device_iis1; +extern struct platform_device s5pc100_device_iis2; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 1f85649d8c18..27d3b497b55b 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -84,4 +84,11 @@ extern void s3c64xx_fb_gpio_setup_24bpp(void); */ extern void s5pc100_fb_gpio_setup_24bpp(void); +/** + * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s5pv210_fb_gpio_setup_24bpp(void); + #endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 34efdd2b032c..db4112c6f2be 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -43,6 +43,11 @@ struct s3c_gpio_chip; * layouts. Provide an point to vector control routine and provide any * per-bank configuration information that other systems such as the * external interrupt code will need. + * + * @sa s3c_gpio_cfgpin + * @sa s3c_gpio_getcfg + * @sa s3c_gpio_setpull + * @sa s3c_gpio_getpull */ struct s3c_gpio_cfg { unsigned int cfg_eint; @@ -70,11 +75,25 @@ struct s3c_gpio_cfg { /** * s3c_gpio_cfgpin() - Change the GPIO function of a pin. * @pin pin The pin number to configure. - * @pin to The configuration for the pin's function. + * @to to The configuration for the pin's function. * * Configure which function is actually connected to the external * pin, such as an gpio input, output or some form of special function * connected to an internal peripheral block. + * + * The @to parameter can be one of the generic S3C_GPIO_INPUT, S3C_GPIO_OUTPUT + * or S3C_GPIO_SFN() to indicate one of the possible values that the helper + * will then generate the correct bit mask and shift for the configuration. + * + * If a bank of GPIOs all needs to be set to special-function 2, then + * the following code will work: + * + * for (gpio = start; gpio < end; gpio++) + * s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + * + * The @to parameter can also be a specific value already shifted to the + * correct position in the control register, although these are discouraged + * in newer kernels and are only being kept for compatibility. */ extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); @@ -108,6 +127,8 @@ extern unsigned s3c_gpio_getcfg(unsigned int pin); * This function sets the state of the pull-{up,down} resistor for the * specified pin. It will return 0 if successfull, or a negative error * code if the pin cannot support the requested pull setting. + * + * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. */ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h index 36397ca20962..f182669b8e8e 100644 --- a/arch/arm/plat-samsung/include/plat/iic-core.h +++ b/arch/arm/plat-samsung/include/plat/iic-core.h @@ -32,4 +32,11 @@ static inline void s3c_i2c1_setname(char *name) #endif } +static inline void s3c_i2c2_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_I2C2 + s3c_device_i2c2.name = name; +#endif +} + #endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 3083df00dee6..133308bf595d 100644 --- a/arch/arm/plat-samsung/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h @@ -54,9 +54,11 @@ struct s3c2410_platform_i2c { */ extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); +extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c); /* defined by architecture to configure gpio */ extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); +extern void s3c_i2c2_cfg_gpio(struct platform_device *dev); #endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-samsung/include/plat/onenand-core.h b/arch/arm/plat-samsung/include/plat/onenand-core.h new file mode 100644 index 000000000000..7701cb7020c8 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/onenand-core.h @@ -0,0 +1,37 @@ +/* + * linux/arch/arm/plat-samsung/onenand-core.h + * + * Copyright (c) 2010 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * Marek Szyprowski <m.szyprowski@samsung.com> + * + * Samsung OneNAD Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_ONENAND_CORE_H +#define __ASM_ARCH_ONENAND_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_onenand_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_ONENAND + s3c_device_onenand.name = name; +#endif +} + +static inline void s3c64xx_onenand1_setname(char *name) +{ +#ifdef CONFIG_S3C64XX_DEV_ONENAND1 + s3c64xx_device_onenand1.name = name; +#endif +} + +#endif /* __ASM_ARCH_ONENAND_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h new file mode 100644 index 000000000000..930ea8b88ed3 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-onenand.h @@ -0,0 +1,63 @@ +/* + * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h + * + * Copyright (C) 2008-2010 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __SAMSUNG_ONENAND_H__ +#define __SAMSUNG_ONENAND_H__ + +#include <mach/hardware.h> + +/* + * OneNAND Controller + */ +#define MEM_CFG_OFFSET 0x0000 +#define BURST_LEN_OFFSET 0x0010 +#define MEM_RESET_OFFSET 0x0020 +#define INT_ERR_STAT_OFFSET 0x0030 +#define INT_ERR_MASK_OFFSET 0x0040 +#define INT_ERR_ACK_OFFSET 0x0050 +#define ECC_ERR_STAT_OFFSET 0x0060 +#define MANUFACT_ID_OFFSET 0x0070 +#define DEVICE_ID_OFFSET 0x0080 +#define DATA_BUF_SIZE_OFFSET 0x0090 +#define BOOT_BUF_SIZE_OFFSET 0x00A0 +#define BUF_AMOUNT_OFFSET 0x00B0 +#define TECH_OFFSET 0x00C0 +#define FBA_WIDTH_OFFSET 0x00D0 +#define FPA_WIDTH_OFFSET 0x00E0 +#define FSA_WIDTH_OFFSET 0x00F0 +#define TRANS_SPARE_OFFSET 0x0140 +#define DBS_DFS_WIDTH_OFFSET 0x0160 +#define INT_PIN_ENABLE_OFFSET 0x01A0 +#define ACC_CLOCK_OFFSET 0x01C0 +#define FLASH_VER_ID_OFFSET 0x01F0 +#define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ + +#define ONENAND_MEM_RESET_HOT 0x3 +#define ONENAND_MEM_RESET_COLD 0x2 +#define ONENAND_MEM_RESET_WARM 0x1 + +#define CACHE_OP_ERR (1 << 13) +#define RST_CMP (1 << 12) +#define RDY_ACT (1 << 11) +#define INT_ACT (1 << 10) +#define UNSUP_CMD (1 << 9) +#define LOCKED_BLK (1 << 8) +#define BLK_RW_CMP (1 << 7) +#define ERS_CMP (1 << 6) +#define PGM_CMP (1 << 5) +#define LOAD_CMP (1 << 4) +#define ERS_FAIL (1 << 3) +#define PGM_FAIL (1 << 2) +#define INT_TO (1 << 1) +#define LD_FAIL_ECC_ERR (1 << 0) + +#define TSRF (1 << 0) + +#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index d5837cf8e402..65c190d142dd 100644 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h @@ -20,6 +20,10 @@ #define S3C2410_RTCCON_CLKSEL (1<<1) #define S3C2410_RTCCON_CNTSEL (1<<2) #define S3C2410_RTCCON_CLKRST (1<<3) +#define S3C64XX_RTCCON_TICEN (1<<8) + +#define S3C64XX_RTCCON_TICMSK (0xF<<7) +#define S3C64XX_RTCCON_TICSHT (7) #define S3C2410_TICNT S3C2410_RTCREG(0x44) #define S3C2410_TICNT_ENABLE (1<<7) diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index d17724149315..e5aba8f95b79 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -63,5 +63,9 @@ struct s3c64xx_spi_info { * has some chips attached to it. */ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); #endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 7d07cd7aa4f2..13f9fb20900a 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -75,6 +75,9 @@ extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); +extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); /* S3C6400 SDHCI setup */ @@ -218,4 +221,56 @@ static inline void s5pc100_default_sdhci1(void) { } static inline void s5pc100_default_sdhci2(void) { } #endif /* CONFIG_S5PC100_SETUP_SDHCI */ + +/* S5PC110 SDHCI setup */ +#ifdef CONFIG_S5PV210_SETUP_SDHCI +extern char *s5pv210_hsmmc_clksrcs[4]; + +extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +#ifdef CONFIG_S3C_DEV_HSMMC +static inline void s5pv210_default_sdhci0(void) +{ + s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +} +#else +static inline void s5pc100_default_sdhci0(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC */ + +#ifdef CONFIG_S3C_DEV_HSMMC1 +static inline void s5pv210_default_sdhci1(void) +{ + s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +} +#else +static inline void s5pv210_default_sdhci1(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC1 */ + +#ifdef CONFIG_S3C_DEV_HSMMC2 +static inline void s5pv210_default_sdhci2(void) +{ + s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +} +#else +static inline void s5pv210_default_sdhci2(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC2 */ + +#else +static inline void s5pv210_default_sdhci0(void) { } +static inline void s5pv210_default_sdhci1(void) { } +static inline void s5pv210_default_sdhci2(void) { } +#endif /* CONFIG_S5PC100_SETUP_SDHCI */ + + + + #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/wakeup-mask.h b/arch/arm/plat-samsung/include/plat/wakeup-mask.h new file mode 100644 index 000000000000..43e4acd2e1c6 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/wakeup-mask.h @@ -0,0 +1,44 @@ +/* arch/arm/plat-samsung/include/plat/wakeup-mask.h + * + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * Support for wakeup mask interrupts on newer SoCs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#ifndef __PLAT_WAKEUP_MASK_H +#define __PLAT_WAKEUP_MASK_H __file__ + +/* if no irq yet defined, but still want to mask */ +#define NO_WAKEUP_IRQ (0x90000000) + +/** + * struct samsung_wakeup_mask - wakeup mask information + * @irq: The interrupt associated with this wakeup. + * @bit: The bit, as a (1 << bitno) controlling this source. + */ +struct samsung_wakeup_mask { + unsigned int irq; + u32 bit; +}; + +/** + * samsung_sync_wakemask - sync wakeup mask information for pm + * @reg: The register that is used. + * @masks: The list of masks to use. + * @nr_masks: The number of entries pointed to buy @masks. + * + * Synchronise the wakeup mask information at suspend time from the list + * of interrupts and control bits in @masks. We do this at suspend time + * as overriding the relevant irq chips is harder and the register is only + * required to be correct before we enter sleep. + */ +extern void samsung_sync_wakemask(void __iomem *reg, + struct samsung_wakeup_mask *masks, + int nr_masks); + +#endif /* __PLAT_WAKEUP_MASK_H */ diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index d50ab9d2af53..7df03f87fbfa 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -331,8 +331,10 @@ void s3c_pm_save_gpios(void) for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { ourchip = s3c_gpiolib_getchip(gpio_nr); - if (!ourchip) + if (!ourchip) { + gpio_nr++; continue; + } s3c_pm_save_gpio(ourchip); @@ -369,8 +371,10 @@ void s3c_pm_restore_gpios(void) for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { ourchip = s3c_gpiolib_getchip(gpio_nr); - if (!ourchip) + if (!ourchip) { + gpio_nr++; continue; + } s3c_pm_resume_gpio(ourchip); diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c new file mode 100644 index 000000000000..2e09b6ad84ca --- /dev/null +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -0,0 +1,47 @@ +/* arch/arm/plat-samsung/wakeup-mask.c + * + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * Support for wakeup mask interrupts on newer SoCs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/sysdev.h> +#include <linux/types.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <plat/wakeup-mask.h> +#include <plat/pm.h> + +void samsung_sync_wakemask(void __iomem *reg, + struct samsung_wakeup_mask *mask, int nr_mask) +{ + struct irq_desc *desc; + u32 val; + + val = __raw_readl(reg); + + for (; nr_mask > 0; nr_mask--, mask++) { + if (mask->irq == NO_WAKEUP_IRQ) { + val |= mask->bit; + continue; + } + + desc = irq_to_desc(mask->irq); + + /* bit of a liberty to read this directly from irq_desc. */ + if (desc->wake_depth > 0) + val &= ~mask->bit; + else + val |= mask->bit; + } + + printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); + __raw_writel(val, reg); +} diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 66dc2d03b7fc..d66cead97d28 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -277,7 +277,7 @@ ENTRY(vfp_put_double) #ifdef CONFIG_VFPv3 @ d16 - d31 registers .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 -1: mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr +1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr mov pc, lr .org 1b + 8 .endr diff --git a/arch/avr32/include/asm/scatterlist.h b/arch/avr32/include/asm/scatterlist.h index 377320e3bd17..06394e5ead6c 100644 --- a/arch/avr32/include/asm/scatterlist.h +++ b/arch/avr32/include/asm/scatterlist.h @@ -1,25 +1,7 @@ #ifndef __ASM_AVR32_SCATTERLIST_H #define __ASM_AVR32_SCATTERLIST_H -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0xffffffff) diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c078849df7f9..f66294b4f9d2 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -348,7 +348,7 @@ config MEM_MT48LC16M16A2TG_75 config MEM_MT48LC32M8A2_75 bool - depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) + depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) default y config MEM_MT48LC8M32B2B5_7 @@ -361,11 +361,6 @@ config MEM_MT48LC32M16A2TG_75 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) default y -config MEM_MT48LC32M8A2_75 - bool - depends on (BFIN518F_EZBRD) - default y - config MEM_MT48H32M16LFCJ_75 bool depends on (BFIN526_EZBRD) @@ -791,6 +786,34 @@ config MEMCPY_L1 If enabled, the memcpy function is linked into L1 instruction memory. (less latency) +config STRCMP_L1 + bool "locate strcmp function in L1 Memory" + default y + help + If enabled, the strcmp function is linked + into L1 instruction memory (less latency). + +config STRNCMP_L1 + bool "locate strncmp function in L1 Memory" + default y + help + If enabled, the strncmp function is linked + into L1 instruction memory (less latency). + +config STRCPY_L1 + bool "locate strcpy function in L1 Memory" + default y + help + If enabled, the strcpy function is linked + into L1 instruction memory (less latency). + +config STRNCPY_L1 + bool "locate strncpy function in L1 Memory" + default y + help + If enabled, the strncpy function is linked + into L1 instruction memory (less latency). + config SYS_BFIN_SPINLOCK_L1 bool "Locate sys_bfin_spinlock function in L1 Memory" default y @@ -1187,32 +1210,6 @@ config PM_BFIN_SLEEP If unsure, select "Sleep Deeper". endchoice -config PM_WAKEUP_BY_GPIO - bool "Allow Wakeup from Standby by GPIO" - depends on PM && !BF54x - -config PM_WAKEUP_GPIO_NUMBER - int "GPIO number" - range 0 47 - depends on PM_WAKEUP_BY_GPIO - default 2 - -choice - prompt "GPIO Polarity" - depends on PM_WAKEUP_BY_GPIO - default PM_WAKEUP_GPIO_POLAR_H -config PM_WAKEUP_GPIO_POLAR_H - bool "Active High" -config PM_WAKEUP_GPIO_POLAR_L - bool "Active Low" -config PM_WAKEUP_GPIO_POLAR_EDGE_F - bool "Falling EDGE" -config PM_WAKEUP_GPIO_POLAR_EDGE_R - bool "Rising EDGE" -config PM_WAKEUP_GPIO_POLAR_EDGE_B - bool "Both EDGE" -endchoice - comment "Possible Suspend Mem / Hibernate Wake-Up Sources" depends on PM diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index aec89a5280b2..d1825cb24768 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug @@ -238,7 +238,7 @@ config EARLY_PRINTK config NMI_WATCHDOG bool "Enable NMI watchdog to help debugging lockup on SMP" default n - depends on (SMP && !BFIN_SCRATCH_REG_RETN) + depends on SMP help If any CPU in the system does not execute the period local timer interrupt for more than 5 seconds, then the NMI handler dumps debug @@ -264,4 +264,13 @@ config BFIN_ISRAM_SELF_TEST help Run some self tests of the isram driver code at boot. +config BFIN_PSEUDODBG_INSNS + bool "Support pseudo debug instructions" + default n + help + This option allows the kernel to emulate some pseudo instructions which + allow simulator test cases to be run under Linux with no changes. + + Most people should say N here. + endmenu diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index e6485c305ea6..121cc04d877d 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h @@ -39,9 +39,15 @@ extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); struct pt_regs; +#if defined(CONFIG_DEBUG_VERBOSE) extern void dump_bfin_process(struct pt_regs *regs); extern void dump_bfin_mem(struct pt_regs *regs); extern void dump_bfin_trace_buffer(void); +#else +#define dump_bfin_process(regs) +#define dump_bfin_mem(regs) +#define dump_bfin_trace_buffer() +#endif /* init functions only */ extern int init_arch_irq(void); diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h index 75f6dc336d46..8d9b1eba89c4 100644 --- a/arch/blackfin/include/asm/bug.h +++ b/arch/blackfin/include/asm/bug.h @@ -9,7 +9,12 @@ #ifdef CONFIG_BUG -#define BFIN_BUG_OPCODE 0xefcd +/* + * This can be any undefined 16-bit opcode, meaning + * ((opcode & 0xc000) != 0xc000) + * Anything from 0x0001 to 0x000A (inclusive) will work + */ +#define BFIN_BUG_OPCODE 0x0001 #ifdef CONFIG_DEBUG_BUGVERBOSE diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 8542bc31f63c..93f6c634fdf4 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -15,6 +15,8 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define SMP_CACHE_BYTES L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + #ifdef CONFIG_SMP #define __cacheline_aligned #else diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 91bd2d7b9d55..01b19d0cf509 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -167,23 +167,23 @@ int bfin_special_gpio_request(unsigned gpio, const char *label); #endif #ifdef CONFIG_PM +int bfin_pm_standby_ctrl(unsigned ctrl); -unsigned int bfin_pm_standby_setup(void); -void bfin_pm_standby_restore(void); +static inline int bfin_pm_standby_setup(void) +{ + return bfin_pm_standby_ctrl(1); +} + +static inline void bfin_pm_standby_restore(void) +{ + bfin_pm_standby_ctrl(0); +} void bfin_gpio_pm_hibernate_restore(void); void bfin_gpio_pm_hibernate_suspend(void); #ifndef CONFIG_BF54x -#define PM_WAKE_RISING 0x1 -#define PM_WAKE_FALLING 0x2 -#define PM_WAKE_HIGH 0x4 -#define PM_WAKE_LOW 0x8 -#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) -#define PM_WAKE_IGNORE 0xF0 - -int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); -void gpio_pm_wakeup_free(unsigned gpio); +int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); struct gpio_port_s { unsigned short data; diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h index 821c699c2238..dcca3e6d6e80 100644 --- a/arch/blackfin/include/asm/pgtable.h +++ b/arch/blackfin/include/asm/pgtable.h @@ -80,7 +80,8 @@ PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED); * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. */ -#define ZERO_PAGE(vaddr) (virt_to_page(0)) +#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) +extern char empty_zero_page[]; extern unsigned int kobjsize(const void *objp); diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h new file mode 100644 index 000000000000..b00adfa08169 --- /dev/null +++ b/arch/blackfin/include/asm/pseudo_instructions.h @@ -0,0 +1,18 @@ +/* + * header file for pseudo instructions + * + * Copyright 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_PSEUDO_ +#define _BLACKFIN_PSEUDO_ + +#include <linux/types.h> +#include <asm/ptrace.h> + +extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode); +extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode); + +#endif diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h index 04f448711cd0..64d41d34ab0b 100644 --- a/arch/blackfin/include/asm/scatterlist.h +++ b/arch/blackfin/include/asm/scatterlist.h @@ -1,27 +1,7 @@ #ifndef _BLACKFIN_SCATTERLIST_H #define _BLACKFIN_SCATTERLIST_H -#include <linux/mm.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0xffffffff) diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h index d7f0ccb418c3..423c099aa988 100644 --- a/arch/blackfin/include/asm/string.h +++ b/arch/blackfin/include/asm/string.h @@ -12,121 +12,16 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ #define __HAVE_ARCH_STRCPY -extern inline char *strcpy(char *dest, const char *src) -{ - char *xdest = dest; - char temp = 0; - - __asm__ __volatile__ ( - "1:" - "%2 = B [%1++] (Z);" - "B [%0++] = %2;" - "CC = %2;" - "if cc jump 1b (bp);" - : "+&a" (dest), "+&a" (src), "=&d" (temp) - : - : "memory", "CC"); - - return xdest; -} +extern char *strcpy(char *dest, const char *src); #define __HAVE_ARCH_STRNCPY -extern inline char *strncpy(char *dest, const char *src, size_t n) -{ - char *xdest = dest; - char temp = 0; - - if (n == 0) - return xdest; - - __asm__ __volatile__ ( - "1:" - "%3 = B [%1++] (Z);" - "B [%0++] = %3;" - "CC = %3;" - "if ! cc jump 2f;" - "%2 += -1;" - "CC = %2 == 0;" - "if ! cc jump 1b (bp);" - "jump 4f;" - "2:" - /* if src is shorter than n, we need to null pad bytes now */ - "%3 = 0;" - "3:" - "%2 += -1;" - "CC = %2 == 0;" - "if cc jump 4f;" - "B [%0++] = %3;" - "jump 3b;" - "4:" - : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp) - : - : "memory", "CC"); - - return xdest; -} +extern char *strncpy(char *dest, const char *src, size_t n); #define __HAVE_ARCH_STRCMP -extern inline int strcmp(const char *cs, const char *ct) -{ - /* need to use int's here so the char's in the assembly don't get - * sign extended incorrectly when we don't want them to be - */ - int __res1, __res2; - - __asm__ __volatile__ ( - "1:" - "%2 = B[%0++] (Z);" /* get *cs */ - "%3 = B[%1++] (Z);" /* get *ct */ - "CC = %2 == %3;" /* compare a byte */ - "if ! cc jump 2f;" /* not equal, break out */ - "CC = %2;" /* at end of cs? */ - "if cc jump 1b (bp);" /* no, keep going */ - "jump.s 3f;" /* strings are equal */ - "2:" - "%2 = %2 - %3;" /* *cs - *ct */ - "3:" - : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2) - : - : "memory", "CC"); - - return __res1; -} +extern int strcmp(const char *cs, const char *ct); #define __HAVE_ARCH_STRNCMP -extern inline int strncmp(const char *cs, const char *ct, size_t count) -{ - /* need to use int's here so the char's in the assembly don't get - * sign extended incorrectly when we don't want them to be - */ - int __res1, __res2; - - if (!count) - return 0; - - __asm__ __volatile__ ( - "1:" - "%3 = B[%0++] (Z);" /* get *cs */ - "%4 = B[%1++] (Z);" /* get *ct */ - "CC = %3 == %4;" /* compare a byte */ - "if ! cc jump 3f;" /* not equal, break out */ - "CC = %3;" /* at end of cs? */ - "if ! cc jump 4f;" /* yes, all done */ - "%2 += -1;" /* no, adjust count */ - "CC = %2 == 0;" - "if ! cc jump 1b;" /* more to do, keep going */ - "2:" - "%3 = 0;" /* strings are equal */ - "jump.s 4f;" - "3:" - "%3 = %3 - %4;" /* *cs - *ct */ - "4:" - : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2) - : - : "memory", "CC"); - - return __res1; -} +extern int strncmp(const char *cs, const char *ct, size_t count); #define __HAVE_ARCH_MEMSET extern void *memset(void *s, int c, size_t count); diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h index f1a06c006ed0..7c368682c0a3 100644 --- a/arch/blackfin/include/asm/tlbflush.h +++ b/arch/blackfin/include/asm/tlbflush.h @@ -1 +1,2 @@ #include <asm-generic/tlbflush.h> +#define flush_tlb_kernel_range(s, e) do { } while (0) diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h index dc0aa55ae773..33589a29b8d8 100644 --- a/arch/blackfin/include/asm/trace.h +++ b/arch/blackfin/include/asm/trace.h @@ -23,6 +23,13 @@ #ifndef __ASSEMBLY__ extern unsigned long trace_buff_offset; extern unsigned long software_trace_buff[]; +#if defined(CONFIG_DEBUG_VERBOSE) +extern void decode_address(char *buf, unsigned long address); +extern bool get_instruction(unsigned int *val, unsigned short *address); +#else +static inline void decode_address(char *buf, unsigned long address) { } +static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; } +#endif /* Trace Macros for C files */ diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 346a421f1562..30d0d1f01dc7 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -7,7 +7,8 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ - fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o + fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o \ + exception.o dumpstack.o ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) obj-y += time-ts.o @@ -29,6 +30,8 @@ obj-$(CONFIG_NMI_WATCHDOG) += nmi.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o obj-$(CONFIG_STACKTRACE) += stacktrace.o +obj-$(CONFIG_DEBUG_VERBOSE) += trace.o +obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o # the kgdb test puts code into L2 and without linker # relaxation, we need to force long calls to/from it diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index e35e20f00d9b..42833ee2b308 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -475,9 +475,7 @@ GET_GPIO_P(maskb) #ifdef CONFIG_PM - static unsigned short wakeup_map[GPIO_BANK_NUM]; -static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS]; static const unsigned int sic_iwr_irqs[] = { #if defined(BF533_FAMILY) @@ -514,112 +512,26 @@ static const unsigned int sic_iwr_irqs[] = { ************************************************************* * MODIFICATION HISTORY : **************************************************************/ -int gpio_pm_wakeup_request(unsigned gpio, unsigned char type) -{ - unsigned long flags; - - if ((check_gpio(gpio) < 0) || !type) - return -EINVAL; - - local_irq_save_hw(flags); - wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); - wakeup_flags_map[gpio] = type; - local_irq_restore_hw(flags); - - return 0; -} -EXPORT_SYMBOL(gpio_pm_wakeup_request); - -void gpio_pm_wakeup_free(unsigned gpio) +int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl) { unsigned long flags; if (check_gpio(gpio) < 0) - return; + return -EINVAL; local_irq_save_hw(flags); - - wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(gpio_pm_wakeup_free); - -static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type) -{ - port_setup(gpio, GPIO_USAGE); - set_gpio_dir(gpio, 0); - set_gpio_inen(gpio, 1); - - if (type & (PM_WAKE_RISING | PM_WAKE_FALLING)) - set_gpio_edge(gpio, 1); - else - set_gpio_edge(gpio, 0); - - if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES)) - set_gpio_both(gpio, 1); + if (ctrl) + wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); else - set_gpio_both(gpio, 0); - - if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW))) - set_gpio_polar(gpio, 1); - else - set_gpio_polar(gpio, 0); + wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - SSYNC(); - - return 0; -} - -u32 bfin_pm_standby_setup(void) -{ - u16 bank, mask, i, gpio; - - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { - mask = wakeup_map[gpio_bank(i)]; - bank = gpio_bank(i); - - gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb; - gpio_array[bank]->maskb = 0; - - if (mask) { -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) - gpio_bank_saved[bank].fer = *port_fer[bank]; -#endif - gpio_bank_saved[bank].inen = gpio_array[bank]->inen; - gpio_bank_saved[bank].polar = gpio_array[bank]->polar; - gpio_bank_saved[bank].dir = gpio_array[bank]->dir; - gpio_bank_saved[bank].edge = gpio_array[bank]->edge; - gpio_bank_saved[bank].both = gpio_array[bank]->both; - gpio_bank_saved[bank].reserved = - reserved_gpio_map[bank]; - - gpio = i; - - while (mask) { - if ((mask & 1) && (wakeup_flags_map[gpio] != - PM_WAKE_IGNORE)) { - reserved_gpio_map[gpio_bank(gpio)] |= - gpio_bit(gpio); - bfin_gpio_wakeup_type(gpio, - wakeup_flags_map[gpio]); - set_gpio_data(gpio, 0); /*Clear*/ - } - gpio++; - mask >>= 1; - } - - bfin_internal_set_wake(sic_iwr_irqs[bank], 1); - gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)]; - } - } - - AWA_DUMMY_READ(maskb_set); + set_gpio_maskb(gpio, ctrl); + local_irq_restore_hw(flags); return 0; } -void bfin_pm_standby_restore(void) +int bfin_pm_standby_ctrl(unsigned ctrl) { u16 bank, mask, i; @@ -627,24 +539,10 @@ void bfin_pm_standby_restore(void) mask = wakeup_map[gpio_bank(i)]; bank = gpio_bank(i); - if (mask) { -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) - *port_fer[bank] = gpio_bank_saved[bank].fer; -#endif - gpio_array[bank]->inen = gpio_bank_saved[bank].inen; - gpio_array[bank]->dir = gpio_bank_saved[bank].dir; - gpio_array[bank]->polar = gpio_bank_saved[bank].polar; - gpio_array[bank]->edge = gpio_bank_saved[bank].edge; - gpio_array[bank]->both = gpio_bank_saved[bank].both; - - reserved_gpio_map[bank] = - gpio_bank_saved[bank].reserved; - bfin_internal_set_wake(sic_iwr_irqs[bank], 0); - } - - gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb; + if (mask) + bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl); } - AWA_DUMMY_READ(maskb); + return 0; } void bfin_gpio_pm_hibernate_suspend(void) @@ -708,16 +606,11 @@ void bfin_gpio_pm_hibernate_restore(void) #else /* CONFIG_BF54x */ #ifdef CONFIG_PM -u32 bfin_pm_standby_setup(void) +int bfin_pm_standby_ctrl(unsigned ctrl) { return 0; } -void bfin_pm_standby_restore(void) -{ - -} - void bfin_gpio_pm_hibernate_suspend(void) { int i, bank; diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index ed8392c117ea..2c264b51566a 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c @@ -33,6 +33,18 @@ EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(memchr); /* + * Because string functions are both inline and exported functions and + * folder arch/blackfin/lib is configured as a library path in Makefile, + * symbols exported in folder lib is not linked into built-in.o but + * inlined only. In order to export string symbols to kernel module + * properly, they should be exported here. + */ +EXPORT_SYMBOL(strcpy); +EXPORT_SYMBOL(strncpy); +EXPORT_SYMBOL(strcmp); +EXPORT_SYMBOL(strncmp); + +/* * libgcc functions - functions that are used internally by the * compiler... (prototypes are not correct though, but that * doesn't really matter since they're not versioned). diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c new file mode 100644 index 000000000000..5cfbaa298211 --- /dev/null +++ b/arch/blackfin/kernel/dumpstack.c @@ -0,0 +1,174 @@ +/* Provide basic stack dumping functions + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <linux/kernel.h> +#include <linux/thread_info.h> +#include <linux/mm.h> +#include <linux/uaccess.h> +#include <linux/module.h> +#include <asm/trace.h> + +/* + * Checks to see if the address pointed to is either a + * 16-bit CALL instruction, or a 32-bit CALL instruction + */ +static bool is_bfin_call(unsigned short *addr) +{ + unsigned int opcode; + + if (!get_instruction(&opcode, addr)) + return false; + + if ((opcode >= 0x0060 && opcode <= 0x0067) || + (opcode >= 0x0070 && opcode <= 0x0077) || + (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF)) + return true; + + return false; + +} + +void show_stack(struct task_struct *task, unsigned long *stack) +{ +#ifdef CONFIG_PRINTK + unsigned int *addr, *endstack, *fp = 0, *frame; + unsigned short *ins_addr; + char buf[150]; + unsigned int i, j, ret_addr, frame_no = 0; + + /* + * If we have been passed a specific stack, use that one otherwise + * if we have been passed a task structure, use that, otherwise + * use the stack of where the variable "stack" exists + */ + + if (stack == NULL) { + if (task) { + /* We know this is a kernel stack, so this is the start/end */ + stack = (unsigned long *)task->thread.ksp; + endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE); + } else { + /* print out the existing stack info */ + stack = (unsigned long *)&stack; + endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); + } + } else + endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); + + printk(KERN_NOTICE "Stack info:\n"); + decode_address(buf, (unsigned int)stack); + printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); + + if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) { + printk(KERN_NOTICE "Invalid stack pointer\n"); + return; + } + + /* First thing is to look for a frame pointer */ + for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) { + if (*addr & 0x1) + continue; + ins_addr = (unsigned short *)*addr; + ins_addr--; + if (is_bfin_call(ins_addr)) + fp = addr - 1; + + if (fp) { + /* Let's check to see if it is a frame pointer */ + while (fp >= (addr - 1) && fp < endstack + && fp && ((unsigned int) fp & 0x3) == 0) + fp = (unsigned int *)*fp; + if (fp == 0 || fp == endstack) { + fp = addr - 1; + break; + } + fp = 0; + } + } + if (fp) { + frame = fp; + printk(KERN_NOTICE " FP: (0x%p)\n", fp); + } else + frame = 0; + + /* + * Now that we think we know where things are, we + * walk the stack again, this time printing things out + * incase there is no frame pointer, we still look for + * valid return addresses + */ + + /* First time print out data, next time, print out symbols */ + for (j = 0; j <= 1; j++) { + if (j) + printk(KERN_NOTICE "Return addresses in stack:\n"); + else + printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack); + + fp = frame; + frame_no = 0; + + for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0; + addr < endstack; addr++, i++) { + + ret_addr = 0; + if (!j && i % 8 == 0) + printk(KERN_NOTICE "%p:", addr); + + /* if it is an odd address, or zero, just skip it */ + if (*addr & 0x1 || !*addr) + goto print; + + ins_addr = (unsigned short *)*addr; + + /* Go back one instruction, and see if it is a CALL */ + ins_addr--; + ret_addr = is_bfin_call(ins_addr); + print: + if (!j && stack == (unsigned long *)addr) + printk("[%08x]", *addr); + else if (ret_addr) + if (j) { + decode_address(buf, (unsigned int)*addr); + if (frame == addr) { + printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf); + continue; + } + printk(KERN_NOTICE " address : %s\n", buf); + } else + printk("<%08x>", *addr); + else if (fp == addr) { + if (j) + frame = addr+1; + else + printk("(%08x)", *addr); + + fp = (unsigned int *)*addr; + frame_no++; + + } else if (!j) + printk(" %08x ", *addr); + } + if (!j) + printk("\n"); + } +#endif +} +EXPORT_SYMBOL(show_stack); + +void dump_stack(void) +{ + unsigned long stack; +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + int tflags; +#endif + trace_buffer_save(tflags); + dump_bfin_trace_buffer(); + show_stack(current, &stack); + trace_buffer_restore(tflags); +} +EXPORT_SYMBOL(dump_stack); diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c new file mode 100644 index 000000000000..9208b5fd5186 --- /dev/null +++ b/arch/blackfin/kernel/exception.c @@ -0,0 +1,45 @@ +/* Basic functions for adding/removing custom exception handlers + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <linux/module.h> +#include <asm/irq_handler.h> + +int bfin_request_exception(unsigned int exception, void (*handler)(void)) +{ + void (*curr_handler)(void); + + if (exception > 0x3F) + return -EINVAL; + + curr_handler = ex_table[exception]; + + if (curr_handler != ex_replaceable) + return -EBUSY; + + ex_table[exception] = handler; + + return 0; +} +EXPORT_SYMBOL(bfin_request_exception); + +int bfin_free_exception(unsigned int exception, void (*handler)(void)) +{ + void (*curr_handler)(void); + + if (exception > 0x3F) + return -EINVAL; + + curr_handler = ex_table[exception]; + + if (curr_handler != handler) + return -EBUSY; + + ex_table[exception] = ex_replaceable; + + return 0; +} +EXPORT_SYMBOL(bfin_free_exception); diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index 7367aea4ae59..08bc44ea6883 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -66,7 +66,7 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) gdb_regs[BFIN_RETN] = regs->retn; gdb_regs[BFIN_RETE] = regs->rete; gdb_regs[BFIN_PC] = regs->pc; - gdb_regs[BFIN_CC] = 0; + gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1; gdb_regs[BFIN_EXTRA1] = 0; gdb_regs[BFIN_EXTRA2] = 0; gdb_regs[BFIN_EXTRA3] = 0; diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c new file mode 100644 index 000000000000..db85bc94334e --- /dev/null +++ b/arch/blackfin/kernel/pseudodbg.c @@ -0,0 +1,191 @@ +/* The fake debug assert instructions + * + * Copyright 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/ptrace.h> + +const char * const greg_names[] = { + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", + "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", + "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", + "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS", + "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", + "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2", + "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", +}; + +static const char *get_allreg_name(int grp, int reg) +{ + return greg_names[(grp << 3) | reg]; +} + +/* + * Unfortunately, the pt_regs structure is not laid out the same way as the + * hardware register file, so we need to do some fix ups. + * + * CYCLES is not stored in the pt_regs structure - so, we just read it from + * the hardware. + * + * Don't support: + * - All reserved registers + * - All in group 7 are (supervisors only) + */ + +static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg) +{ + long *val = &fp->r0; + unsigned long tmp; + + /* Only do Dregs and Pregs for now */ + if (grp == 5 || + (grp == 4 && (reg == 4 || reg == 5)) || + (grp == 7)) + return false; + + if (grp == 0 || (grp == 1 && reg < 6)) + val -= (reg + 8 * grp); + else if (grp == 1 && reg == 6) + val = &fp->usp; + else if (grp == 1 && reg == 7) + val = &fp->fp; + else if (grp == 2) { + val = &fp->i0; + val -= reg; + } else if (grp == 3 && reg >= 4) { + val = &fp->l0; + val -= (reg - 4); + } else if (grp == 3 && reg < 4) { + val = &fp->b0; + val -= reg; + } else if (grp == 4 && reg < 4) { + val = &fp->a0x; + val -= reg; + } else if (grp == 4 && reg == 6) + val = &fp->astat; + else if (grp == 4 && reg == 7) + val = &fp->rets; + else if (grp == 6 && reg < 6) { + val = &fp->lc0; + val -= reg; + } else if (grp == 6 && reg == 6) { + __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp)); + val = &tmp; + } else if (grp == 6 && reg == 7) { + __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp)); + val = &tmp; + } + + *value = *val; + return true; + +} + +#define PseudoDbg_Assert_opcode 0xf0000000 +#define PseudoDbg_Assert_expected_bits 0 +#define PseudoDbg_Assert_expected_mask 0xffff +#define PseudoDbg_Assert_regtest_bits 16 +#define PseudoDbg_Assert_regtest_mask 0x7 +#define PseudoDbg_Assert_grp_bits 19 +#define PseudoDbg_Assert_grp_mask 0x7 +#define PseudoDbg_Assert_dbgop_bits 22 +#define PseudoDbg_Assert_dbgop_mask 0x3 +#define PseudoDbg_Assert_dontcare_bits 24 +#define PseudoDbg_Assert_dontcare_mask 0x7 +#define PseudoDbg_Assert_code_bits 27 +#define PseudoDbg_Assert_code_mask 0x1f + +/* + * DBGA - debug assert + */ +bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode) +{ + int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); + int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask); + int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask); + int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask); + long value; + + if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode) + return false; + + if (!fix_up_reg(fp, &value, grp, regtest)) + return false; + + if (dbgop == 0 || dbgop == 2) { + /* DBGA ( regs_lo , uimm16 ) */ + /* DBGAL ( regs , uimm16 ) */ + if (expected != (value & 0xFFFF)) { + pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n", + get_allreg_name(grp, regtest), + expected, (unsigned int)(value & 0xFFFF)); + return false; + } + + } else if (dbgop == 1 || dbgop == 3) { + /* DBGA ( regs_hi , uimm16 ) */ + /* DBGAH ( regs , uimm16 ) */ + if (expected != ((value >> 16) & 0xFFFF)) { + pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n", + get_allreg_name(grp, regtest), + expected, (unsigned int)((value >> 16) & 0xFFFF)); + return false; + } + } + + fp->pc += 4; + return true; +} + +#define PseudoDbg_opcode 0xf8000000 +#define PseudoDbg_reg_bits 0 +#define PseudoDbg_reg_mask 0x7 +#define PseudoDbg_grp_bits 3 +#define PseudoDbg_grp_mask 0x7 +#define PseudoDbg_fn_bits 6 +#define PseudoDbg_fn_mask 0x3 +#define PseudoDbg_code_bits 8 +#define PseudoDbg_code_mask 0xff + +/* + * DBG - debug (dump a register value out) + */ +bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode) +{ + int grp, fn, reg; + long value, value1; + + if ((opcode & 0xFF000000) != PseudoDbg_opcode) + return false; + + opcode >>= 16; + grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask); + fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); + reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); + + if (fn == 3 && (reg == 0 || reg == 1)) { + if (!fix_up_reg(fp, &value, 4, 2 * reg)) + return false; + if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1)) + return false; + + pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1); + fp->pc += 2; + return true; + + } else if (fn == 0) { + if (!fix_up_reg(fp, &value, grp, reg)) + return false; + + pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value); + fp->pc += 2; + return true; + } + + return false; +} diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 43eb969405d1..6ec77685df52 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -292,28 +292,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) break; } -#ifdef CONFIG_BINFMT_ELF_FDPIC - case PTRACE_GETFDPIC: { - unsigned long tmp = 0; - - switch (addr) { - case_PTRACE_GETFDPIC_EXEC: - case PTRACE_GETFDPIC_EXEC: - tmp = child->mm->context.exec_fdpic_loadmap; - break; - case_PTRACE_GETFDPIC_INTERP: - case PTRACE_GETFDPIC_INTERP: - tmp = child->mm->context.interp_fdpic_loadmap; - break; - default: - break; - } - - ret = put_user(tmp, datap); - break; - } -#endif - /* when I and D space are separate, this will have to be fixed. */ case PTRACE_POKEDATA: pr_debug("ptrace: PTRACE_PEEKDATA\n"); @@ -357,8 +335,14 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) case PTRACE_PEEKUSR: switch (addr) { #ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */ - case PT_FDPIC_EXEC: goto case_PTRACE_GETFDPIC_EXEC; - case PT_FDPIC_INTERP: goto case_PTRACE_GETFDPIC_INTERP; + case PT_FDPIC_EXEC: + request = PTRACE_GETFDPIC; + addr = PTRACE_GETFDPIC_EXEC; + goto case_default; + case PT_FDPIC_INTERP: + request = PTRACE_GETFDPIC; + addr = PTRACE_GETFDPIC_INTERP; + goto case_default; #endif default: ret = get_reg(child, addr, datap); @@ -385,6 +369,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) 0, sizeof(struct pt_regs), (const void __user *)data); + case_default: default: ret = ptrace_request(child, request, addr, data); break; diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 8e2efceb364b..d37a397f43f5 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Analog Devices Inc. + * Copyright 2004-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -925,7 +925,7 @@ void __init setup_arch(char **cmdline_p) else if (_bfin_swrst & RESET_SOFTWARE) printk(KERN_NOTICE "Reset caused by Software reset\n"); - printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); + printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n"); if (bfin_compiled_revid() == 0xffff) printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); else if (bfin_compiled_revid() == -1) diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index 2e7f8e10bf87..bdc1e2f0da32 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c @@ -47,3 +47,26 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, } EXPORT_SYMBOL(get_fb_unmapped_area); #endif + +/* Needed for legacy userspace atomic emulation */ +static DEFINE_SPINLOCK(bfin_spinlock_lock); + +#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1 +__attribute__((l1_text)) +#endif +asmlinkage int sys_bfin_spinlock(int *p) +{ + int ret, tmp = 0; + + spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */ + ret = get_user(tmp, p); + if (likely(ret == 0)) { + if (unlikely(tmp)) + ret = 1; + else + put_user(1, p); + } + spin_unlock(&bfin_spinlock_lock); + + return ret; +} diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c new file mode 100644 index 000000000000..59fcdf6b0138 --- /dev/null +++ b/arch/blackfin/kernel/trace.c @@ -0,0 +1,981 @@ +/* provide some functions which dump the trace buffer, in a nice way for people + * to read it, and understand what is going on + * + * Copyright 2004-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <linux/kernel.h> +#include <linux/hardirq.h> +#include <linux/thread_info.h> +#include <linux/mm.h> +#include <linux/uaccess.h> +#include <linux/module.h> +#include <linux/kallsyms.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <asm/dma.h> +#include <asm/trace.h> +#include <asm/fixed_code.h> +#include <asm/traps.h> +#include <asm/irq_handler.h> + +void decode_address(char *buf, unsigned long address) +{ + struct task_struct *p; + struct mm_struct *mm; + unsigned long flags, offset; + unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); + struct rb_node *n; + +#ifdef CONFIG_KALLSYMS + unsigned long symsize; + const char *symname; + char *modname; + char *delim = ":"; + char namebuf[128]; +#endif + + buf += sprintf(buf, "<0x%08lx> ", address); + +#ifdef CONFIG_KALLSYMS + /* look up the address and see if we are in kernel space */ + symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); + + if (symname) { + /* yeah! kernel space! */ + if (!modname) + modname = delim = ""; + sprintf(buf, "{ %s%s%s%s + 0x%lx }", + delim, modname, delim, symname, + (unsigned long)offset); + return; + } +#endif + + if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { + /* Problem in fixed code section? */ + strcat(buf, "/* Maybe fixed code section */"); + return; + + } else if (address < CONFIG_BOOT_LOAD) { + /* Problem somewhere before the kernel start address */ + strcat(buf, "/* Maybe null pointer? */"); + return; + + } else if (address >= COREMMR_BASE) { + strcat(buf, "/* core mmrs */"); + return; + + } else if (address >= SYSMMR_BASE) { + strcat(buf, "/* system mmrs */"); + return; + + } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) { + strcat(buf, "/* on-chip L1 ROM */"); + return; + + } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) { + strcat(buf, "/* on-chip scratchpad */"); + return; + + } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) { + strcat(buf, "/* unconnected memory */"); + return; + + } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) { + strcat(buf, "/* reserved memory */"); + return; + + } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) { + strcat(buf, "/* on-chip Data Bank A */"); + return; + + } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) { + strcat(buf, "/* on-chip Data Bank B */"); + return; + } + + /* + * Don't walk any of the vmas if we are oopsing, it has been known + * to cause problems - corrupt vmas (kernel crashes) cause double faults + */ + if (oops_in_progress) { + strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); + return; + } + + /* looks like we're off in user-land, so let's walk all the + * mappings of all our processes and see if we can't be a whee + * bit more specific + */ + write_lock_irqsave(&tasklist_lock, flags); + for_each_process(p) { + mm = (in_atomic ? p->mm : get_task_mm(p)); + if (!mm) + continue; + + if (!down_read_trylock(&mm->mmap_sem)) { + if (!in_atomic) + mmput(mm); + continue; + } + + for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) { + struct vm_area_struct *vma; + + vma = rb_entry(n, struct vm_area_struct, vm_rb); + + if (address >= vma->vm_start && address < vma->vm_end) { + char _tmpbuf[256]; + char *name = p->comm; + struct file *file = vma->vm_file; + + if (file) { + char *d_name = d_path(&file->f_path, _tmpbuf, + sizeof(_tmpbuf)); + if (!IS_ERR(d_name)) + name = d_name; + } + + /* FLAT does not have its text aligned to the start of + * the map while FDPIC ELF does ... + */ + + /* before we can check flat/fdpic, we need to + * make sure current is valid + */ + if ((unsigned long)current >= FIXED_CODE_START && + !((unsigned long)current & 0x3)) { + if (current->mm && + (address > current->mm->start_code) && + (address < current->mm->end_code)) + offset = address - current->mm->start_code; + else + offset = (address - vma->vm_start) + + (vma->vm_pgoff << PAGE_SHIFT); + + sprintf(buf, "[ %s + 0x%lx ]", name, offset); + } else + sprintf(buf, "[ %s vma:0x%lx-0x%lx]", + name, vma->vm_start, vma->vm_end); + + up_read(&mm->mmap_sem); + if (!in_atomic) + mmput(mm); + + if (buf[0] == '\0') + sprintf(buf, "[ %s ] dynamic memory", name); + + goto done; + } + } + + up_read(&mm->mmap_sem); + if (!in_atomic) + mmput(mm); + } + + /* + * we were unable to find this address anywhere, + * or some MMs were skipped because they were in use. + */ + sprintf(buf, "/* kernel dynamic memory */"); + +done: + write_unlock_irqrestore(&tasklist_lock, flags); +} + +#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1) + +/* + * Similar to get_user, do some address checking, then dereference + * Return true on success, false on bad address + */ +bool get_mem16(unsigned short *val, unsigned short *address) +{ + unsigned long addr = (unsigned long)address; + + /* Check for odd addresses */ + if (addr & 0x1) + return false; + + switch (bfin_mem_access_type(addr, 2)) { + case BFIN_MEM_ACCESS_CORE: + case BFIN_MEM_ACCESS_CORE_ONLY: + *val = *address; + return true; + case BFIN_MEM_ACCESS_DMA: + dma_memcpy(val, address, 2); + return true; + case BFIN_MEM_ACCESS_ITEST: + isram_memcpy(val, address, 2); + return true; + default: /* invalid access */ + return false; + } +} + +bool get_instruction(unsigned int *val, unsigned short *address) +{ + unsigned long addr = (unsigned long)address; + unsigned short opcode0, opcode1; + + /* Check for odd addresses */ + if (addr & 0x1) + return false; + + /* MMR region will never have instructions */ + if (addr >= SYSMMR_BASE) + return false; + + /* Scratchpad will never have instructions */ + if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH) + return false; + + /* Data banks will never have instructions */ + if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START) + return false; + + if (!get_mem16(&opcode0, address)) + return false; + + /* was this a 32-bit instruction? If so, get the next 16 bits */ + if ((opcode0 & 0xc000) == 0xc000) { + if (!get_mem16(&opcode1, address + 1)) + return false; + *val = (opcode0 << 16) + opcode1; + } else + *val = opcode0; + + return true; +} + +#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON) +/* + * decode the instruction if we are printing out the trace, as it + * makes things easier to follow, without running it through objdump + * Decode the change of flow, and the common load/store instructions + * which are the main cause for faults, and discontinuities in the trace + * buffer. + */ + +#define ProgCtrl_opcode 0x0000 +#define ProgCtrl_poprnd_bits 0 +#define ProgCtrl_poprnd_mask 0xf +#define ProgCtrl_prgfunc_bits 4 +#define ProgCtrl_prgfunc_mask 0xf +#define ProgCtrl_code_bits 8 +#define ProgCtrl_code_mask 0xff + +static void decode_ProgCtrl_0(unsigned int opcode) +{ + int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); + int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); + + if (prgfunc == 0 && poprnd == 0) + pr_cont("NOP"); + else if (prgfunc == 1 && poprnd == 0) + pr_cont("RTS"); + else if (prgfunc == 1 && poprnd == 1) + pr_cont("RTI"); + else if (prgfunc == 1 && poprnd == 2) + pr_cont("RTX"); + else if (prgfunc == 1 && poprnd == 3) + pr_cont("RTN"); + else if (prgfunc == 1 && poprnd == 4) + pr_cont("RTE"); + else if (prgfunc == 2 && poprnd == 0) + pr_cont("IDLE"); + else if (prgfunc == 2 && poprnd == 3) + pr_cont("CSYNC"); + else if (prgfunc == 2 && poprnd == 4) + pr_cont("SSYNC"); + else if (prgfunc == 2 && poprnd == 5) + pr_cont("EMUEXCPT"); + else if (prgfunc == 3) + pr_cont("CLI R%i", poprnd); + else if (prgfunc == 4) + pr_cont("STI R%i", poprnd); + else if (prgfunc == 5) + pr_cont("JUMP (P%i)", poprnd); + else if (prgfunc == 6) + pr_cont("CALL (P%i)", poprnd); + else if (prgfunc == 7) + pr_cont("CALL (PC + P%i)", poprnd); + else if (prgfunc == 8) + pr_cont("JUMP (PC + P%i", poprnd); + else if (prgfunc == 9) + pr_cont("RAISE %i", poprnd); + else if (prgfunc == 10) + pr_cont("EXCPT %i", poprnd); + else + pr_cont("0x%04x", opcode); + +} + +#define BRCC_opcode 0x1000 +#define BRCC_offset_bits 0 +#define BRCC_offset_mask 0x3ff +#define BRCC_B_bits 10 +#define BRCC_B_mask 0x1 +#define BRCC_T_bits 11 +#define BRCC_T_mask 0x1 +#define BRCC_code_bits 12 +#define BRCC_code_mask 0xf + +static void decode_BRCC_0(unsigned int opcode) +{ + int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask); + int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask); + + pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : ""); +} + +#define CALLa_opcode 0xe2000000 +#define CALLa_addr_bits 0 +#define CALLa_addr_mask 0xffffff +#define CALLa_S_bits 24 +#define CALLa_S_mask 0x1 +#define CALLa_code_bits 25 +#define CALLa_code_mask 0x7f + +static void decode_CALLa_0(unsigned int opcode) +{ + int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask); + + if (S) + pr_cont("CALL pcrel"); + else + pr_cont("JUMP.L"); +} + +#define LoopSetup_opcode 0xe0800000 +#define LoopSetup_eoffset_bits 0 +#define LoopSetup_eoffset_mask 0x3ff +#define LoopSetup_dontcare_bits 10 +#define LoopSetup_dontcare_mask 0x3 +#define LoopSetup_reg_bits 12 +#define LoopSetup_reg_mask 0xf +#define LoopSetup_soffset_bits 16 +#define LoopSetup_soffset_mask 0xf +#define LoopSetup_c_bits 20 +#define LoopSetup_c_mask 0x1 +#define LoopSetup_rop_bits 21 +#define LoopSetup_rop_mask 0x3 +#define LoopSetup_code_bits 23 +#define LoopSetup_code_mask 0x1ff + +static void decode_LoopSetup_0(unsigned int opcode) +{ + int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask); + int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask); + int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask); + + pr_cont("LSETUP <> LC%i", c); + if ((rop & 1) == 1) + pr_cont("= P%i", reg); + if ((rop & 2) == 2) + pr_cont(" >> 0x1"); +} + +#define DspLDST_opcode 0x9c00 +#define DspLDST_reg_bits 0 +#define DspLDST_reg_mask 0x7 +#define DspLDST_i_bits 3 +#define DspLDST_i_mask 0x3 +#define DspLDST_m_bits 5 +#define DspLDST_m_mask 0x3 +#define DspLDST_aop_bits 7 +#define DspLDST_aop_mask 0x3 +#define DspLDST_W_bits 9 +#define DspLDST_W_mask 0x1 +#define DspLDST_code_bits 10 +#define DspLDST_code_mask 0x3f + +static void decode_dspLDST_0(unsigned int opcode) +{ + int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask); + int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask); + int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask); + int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask); + int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask); + + if (W == 0) { + pr_cont("R%i", reg); + switch (m) { + case 0: + pr_cont(" = "); + break; + case 1: + pr_cont(".L = "); + break; + case 2: + pr_cont(".W = "); + break; + } + } + + pr_cont("[ I%i", i); + + switch (aop) { + case 0: + pr_cont("++ ]"); + break; + case 1: + pr_cont("-- ]"); + break; + } + + if (W == 1) { + pr_cont(" = R%i", reg); + switch (m) { + case 1: + pr_cont(".L = "); + break; + case 2: + pr_cont(".W = "); + break; + } + } +} + +#define LDST_opcode 0x9000 +#define LDST_reg_bits 0 +#define LDST_reg_mask 0x7 +#define LDST_ptr_bits 3 +#define LDST_ptr_mask 0x7 +#define LDST_Z_bits 6 +#define LDST_Z_mask 0x1 +#define LDST_aop_bits 7 +#define LDST_aop_mask 0x3 +#define LDST_W_bits 9 +#define LDST_W_mask 0x1 +#define LDST_sz_bits 10 +#define LDST_sz_mask 0x3 +#define LDST_code_bits 12 +#define LDST_code_mask 0xf + +static void decode_LDST_0(unsigned int opcode) +{ + int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask); + int W = ((opcode >> LDST_W_bits) & LDST_W_mask); + int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask); + int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask); + int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask); + int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask); + + if (W == 0) + pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg); + + switch (sz) { + case 1: + pr_cont("W"); + break; + case 2: + pr_cont("B"); + break; + } + + pr_cont("[P%i", ptr); + + switch (aop) { + case 0: + pr_cont("++"); + break; + case 1: + pr_cont("--"); + break; + } + pr_cont("]"); + + if (W == 1) + pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg); + + if (sz) { + if (Z) + pr_cont(" (X)"); + else + pr_cont(" (Z)"); + } +} + +#define LDSTii_opcode 0xa000 +#define LDSTii_reg_bit 0 +#define LDSTii_reg_mask 0x7 +#define LDSTii_ptr_bit 3 +#define LDSTii_ptr_mask 0x7 +#define LDSTii_offset_bit 6 +#define LDSTii_offset_mask 0xf +#define LDSTii_op_bit 10 +#define LDSTii_op_mask 0x3 +#define LDSTii_W_bit 12 +#define LDSTii_W_mask 0x1 +#define LDSTii_code_bit 13 +#define LDSTii_code_mask 0x7 + +static void decode_LDSTii_0(unsigned int opcode) +{ + int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask); + int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask); + int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask); + int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask); + int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask); + + if (W == 0) { + pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg, + op == 1 || op == 2 ? "" : "W", ptr, offset); + if (op == 2) + pr_cont("(Z)"); + if (op == 3) + pr_cont("(X)"); + } else { + pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr, + offset, op == 3 ? "P" : "R", reg); + } +} + +#define LDSTidxI_opcode 0xe4000000 +#define LDSTidxI_offset_bits 0 +#define LDSTidxI_offset_mask 0xffff +#define LDSTidxI_reg_bits 16 +#define LDSTidxI_reg_mask 0x7 +#define LDSTidxI_ptr_bits 19 +#define LDSTidxI_ptr_mask 0x7 +#define LDSTidxI_sz_bits 22 +#define LDSTidxI_sz_mask 0x3 +#define LDSTidxI_Z_bits 24 +#define LDSTidxI_Z_mask 0x1 +#define LDSTidxI_W_bits 25 +#define LDSTidxI_W_mask 0x1 +#define LDSTidxI_code_bits 26 +#define LDSTidxI_code_mask 0x3f + +static void decode_LDSTidxI_0(unsigned int opcode) +{ + int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask); + int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask); + int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask); + int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask); + int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask); + int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); + + if (W == 0) + pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg); + + if (sz == 1) + pr_cont("W"); + if (sz == 2) + pr_cont("B"); + + pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "", + (offset & 0x1f) << 2); + + if (W == 0 && sz != 0) { + if (Z) + pr_cont("(X)"); + else + pr_cont("(Z)"); + } + + if (W == 1) + pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg); + +} + +static void decode_opcode(unsigned int opcode) +{ +#ifdef CONFIG_BUG + if (opcode == BFIN_BUG_OPCODE) + pr_cont("BUG"); + else +#endif + if ((opcode & 0xffffff00) == ProgCtrl_opcode) + decode_ProgCtrl_0(opcode); + else if ((opcode & 0xfffff000) == BRCC_opcode) + decode_BRCC_0(opcode); + else if ((opcode & 0xfffff000) == 0x2000) + pr_cont("JUMP.S"); + else if ((opcode & 0xfe000000) == CALLa_opcode) + decode_CALLa_0(opcode); + else if ((opcode & 0xff8000C0) == LoopSetup_opcode) + decode_LoopSetup_0(opcode); + else if ((opcode & 0xfffffc00) == DspLDST_opcode) + decode_dspLDST_0(opcode); + else if ((opcode & 0xfffff000) == LDST_opcode) + decode_LDST_0(opcode); + else if ((opcode & 0xffffe000) == LDSTii_opcode) + decode_LDSTii_0(opcode); + else if ((opcode & 0xfc000000) == LDSTidxI_opcode) + decode_LDSTidxI_0(opcode); + else if (opcode & 0xffff0000) + pr_cont("0x%08x", opcode); + else + pr_cont("0x%04x", opcode); +} + +#define BIT_MULTI_INS 0x08000000 +static void decode_instruction(unsigned short *address) +{ + unsigned int opcode; + + if (!get_instruction(&opcode, address)) + return; + + decode_opcode(opcode); + + /* If things are a 32-bit instruction, it has the possibility of being + * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions) + * This test collidates with the unlink instruction, so disallow that + */ + if ((opcode & 0xc0000000) == 0xc0000000 && + (opcode & BIT_MULTI_INS) && + (opcode & 0xe8000000) != 0xe8000000) { + pr_cont(" || "); + if (!get_instruction(&opcode, address + 2)) + return; + decode_opcode(opcode); + pr_cont(" || "); + if (!get_instruction(&opcode, address + 3)) + return; + decode_opcode(opcode); + } +} +#endif + +void dump_bfin_trace_buffer(void) +{ +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + int tflags, i = 0, fault = 0; + char buf[150]; + unsigned short *addr; + unsigned int cpu = raw_smp_processor_id(); +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND + int j, index; +#endif + + trace_buffer_save(tflags); + + pr_notice("Hardware Trace:\n"); + +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND + pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n"); +#endif + + if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { + for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) { + addr = (unsigned short *)bfin_read_TBUF(); + decode_address(buf, (unsigned long)addr); + pr_notice("%4i Target : %s\n", i, buf); + /* Normally, the faulting instruction doesn't go into + * the trace buffer, (since it doesn't commit), so + * we print out the fault address here + */ + if (!fault && addr == ((unsigned short *)evt_ivhw)) { + addr = (unsigned short *)bfin_read_TBUF(); + decode_address(buf, (unsigned long)addr); + pr_notice(" FAULT : %s ", buf); + decode_instruction(addr); + pr_cont("\n"); + fault = 1; + continue; + } + if (!fault && addr == (unsigned short *)trap && + (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) { + decode_address(buf, cpu_pda[cpu].icplb_fault_addr); + pr_notice(" FAULT : %s ", buf); + decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr); + pr_cont("\n"); + fault = 1; + } + addr = (unsigned short *)bfin_read_TBUF(); + decode_address(buf, (unsigned long)addr); + pr_notice(" Source : %s ", buf); + decode_instruction(addr); + pr_cont("\n"); + } + } + +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND + if (trace_buff_offset) + index = trace_buff_offset / 4; + else + index = EXPAND_LEN; + + j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128; + while (j) { + decode_address(buf, software_trace_buff[index]); + pr_notice("%4i Target : %s\n", i, buf); + index -= 1; + if (index < 0) + index = EXPAND_LEN; + decode_address(buf, software_trace_buff[index]); + pr_notice(" Source : %s ", buf); + decode_instruction((unsigned short *)software_trace_buff[index]); + pr_cont("\n"); + index -= 1; + if (index < 0) + index = EXPAND_LEN; + j--; + i++; + } +#endif + + trace_buffer_restore(tflags); +#endif +} +EXPORT_SYMBOL(dump_bfin_trace_buffer); + +void dump_bfin_process(struct pt_regs *fp) +{ + /* We should be able to look at fp->ipend, but we don't push it on the + * stack all the time, so do this until we fix that */ + unsigned int context = bfin_read_IPEND(); + + if (oops_in_progress) + pr_emerg("Kernel OOPS in progress\n"); + + if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) + pr_notice("HW Error context\n"); + else if (context & 0x0020) + pr_notice("Deferred Exception context\n"); + else if (context & 0x3FC0) + pr_notice("Interrupt context\n"); + else if (context & 0x4000) + pr_notice("Deferred Interrupt context\n"); + else if (context & 0x8000) + pr_notice("Kernel process context\n"); + + /* Because we are crashing, and pointers could be bad, we check things + * pretty closely before we use them + */ + if ((unsigned long)current >= FIXED_CODE_START && + !((unsigned long)current & 0x3) && current->pid) { + pr_notice("CURRENT PROCESS:\n"); + if (current->comm >= (char *)FIXED_CODE_START) + pr_notice("COMM=%s PID=%d", + current->comm, current->pid); + else + pr_notice("COMM= invalid"); + + pr_cont(" CPU=%d\n", current_thread_info()->cpu); + if (!((unsigned long)current->mm & 0x3) && + (unsigned long)current->mm >= FIXED_CODE_START) { + pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n", + (void *)current->mm->start_code, + (void *)current->mm->end_code, + (void *)current->mm->start_data, + (void *)current->mm->end_data); + pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n", + (void *)current->mm->end_data, + (void *)current->mm->brk, + (void *)current->mm->start_stack); + } else + pr_notice("invalid mm\n"); + } else + pr_notice("No Valid process in current context\n"); +} + +void dump_bfin_mem(struct pt_regs *fp) +{ + unsigned short *addr, *erraddr, val = 0, err = 0; + char sti = 0, buf[6]; + + erraddr = (void *)fp->pc; + + pr_notice("return address: [0x%p]; contents of:", erraddr); + + for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; + addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; + addr++) { + if (!((unsigned long)addr & 0xF)) + pr_notice("0x%p: ", addr); + + if (!get_mem16(&val, addr)) { + val = 0; + sprintf(buf, "????"); + } else + sprintf(buf, "%04x", val); + + if (addr == erraddr) { + pr_cont("[%s]", buf); + err = val; + } else + pr_cont(" %s ", buf); + + /* Do any previous instructions turn on interrupts? */ + if (addr <= erraddr && /* in the past */ + ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */ + val == 0x017b)) /* [SP++] = RETI */ + sti = 1; + } + + pr_cont("\n"); + + /* Hardware error interrupts can be deferred */ + if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && + oops_in_progress)){ + pr_notice("Looks like this was a deferred error - sorry\n"); +#ifndef CONFIG_DEBUG_HWERR + pr_notice("The remaining message may be meaningless\n"); + pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n"); +#else + /* If we are handling only one peripheral interrupt + * and current mm and pid are valid, and the last error + * was in that user space process's text area + * print it out - because that is where the problem exists + */ + if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) && + (current->pid && current->mm)) { + /* And the last RETI points to the current userspace context */ + if ((fp + 1)->pc >= current->mm->start_code && + (fp + 1)->pc <= current->mm->end_code) { + pr_notice("It might be better to look around here :\n"); + pr_notice("-------------------------------------------\n"); + show_regs(fp + 1); + pr_notice("-------------------------------------------\n"); + } + } +#endif + } +} + +void show_regs(struct pt_regs *fp) +{ + char buf[150]; + struct irqaction *action; + unsigned int i; + unsigned long flags = 0; + unsigned int cpu = raw_smp_processor_id(); + unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); + + pr_notice("\n"); + if (CPUID != bfin_cpuid()) + pr_notice("Compiled for cpu family 0x%04x (Rev %d), " + "but running on:0x%04x (Rev %d)\n", + CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid()); + + pr_notice("ADSP-%s-0.%d", + CPU, bfin_compiled_revid()); + + if (bfin_compiled_revid() != bfin_revid()) + pr_cont("(Detected 0.%d)", bfin_revid()); + + pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n", + get_cclk()/1000000, get_sclk()/1000000, +#ifdef CONFIG_MPU + "mpu on" +#else + "mpu off" +#endif + ); + + pr_notice("%s", linux_banner); + + pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted()); + pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n", + (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg); + if (fp->ipend & EVT_IRPTEN) + pr_notice(" Global Interrupts Disabled (IPEND[4])\n"); + if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 | + EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR))) + pr_notice(" Peripheral interrupts masked off\n"); + if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14))) + pr_notice(" Kernel interrupts masked off\n"); + if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { + pr_notice(" HWERRCAUSE: 0x%lx\n", + (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); +#ifdef EBIU_ERRMST + /* If the error was from the EBIU, print it out */ + if (bfin_read_EBIU_ERRMST() & CORE_ERROR) { + pr_notice(" EBIU Error Reason : 0x%04x\n", + bfin_read_EBIU_ERRMST()); + pr_notice(" EBIU Error Address : 0x%08x\n", + bfin_read_EBIU_ERRADD()); + } +#endif + } + pr_notice(" EXCAUSE : 0x%lx\n", + fp->seqstat & SEQSTAT_EXCAUSE); + for (i = 2; i <= 15 ; i++) { + if (fp->ipend & (1 << i)) { + if (i != 4) { + decode_address(buf, bfin_read32(EVT0 + 4*i)); + pr_notice(" physical IVG%i asserted : %s\n", i, buf); + } else + pr_notice(" interrupts disabled\n"); + } + } + + /* if no interrupts are going off, don't print this out */ + if (fp->ipend & ~0x3F) { + for (i = 0; i < (NR_IRQS - 1); i++) { + if (!in_atomic) + raw_spin_lock_irqsave(&irq_desc[i].lock, flags); + + action = irq_desc[i].action; + if (!action) + goto unlock; + + decode_address(buf, (unsigned int)action->handler); + pr_notice(" logical irq %3d mapped : %s", i, buf); + for (action = action->next; action; action = action->next) { + decode_address(buf, (unsigned int)action->handler); + pr_cont(", %s", buf); + } + pr_cont("\n"); +unlock: + if (!in_atomic) + raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + } + } + + decode_address(buf, fp->rete); + pr_notice(" RETE: %s\n", buf); + decode_address(buf, fp->retn); + pr_notice(" RETN: %s\n", buf); + decode_address(buf, fp->retx); + pr_notice(" RETX: %s\n", buf); + decode_address(buf, fp->rets); + pr_notice(" RETS: %s\n", buf); + decode_address(buf, fp->pc); + pr_notice(" PC : %s\n", buf); + + if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && + (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { + decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); + pr_notice("DCPLB_FAULT_ADDR: %s\n", buf); + decode_address(buf, cpu_pda[cpu].icplb_fault_addr); + pr_notice("ICPLB_FAULT_ADDR: %s\n", buf); + } + + pr_notice("PROCESSOR STATE:\n"); + pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", + fp->r0, fp->r1, fp->r2, fp->r3); + pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", + fp->r4, fp->r5, fp->r6, fp->r7); + pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", + fp->p0, fp->p1, fp->p2, fp->p3); + pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", + fp->p4, fp->p5, fp->fp, (long)fp); + pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n", + fp->lb0, fp->lt0, fp->lc0); + pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n", + fp->lb1, fp->lt1, fp->lc1); + pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", + fp->b0, fp->l0, fp->m0, fp->i0); + pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", + fp->b1, fp->l1, fp->m1, fp->i1); + pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", + fp->b2, fp->l2, fp->m2, fp->i2); + pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", + fp->b3, fp->l3, fp->m3, fp->i3); + pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", + fp->a0w, fp->a0x, fp->a1w, fp->a1x); + + pr_notice("USP : %08lx ASTAT: %08lx\n", + rdusp(), fp->astat); + + pr_notice("\n"); +} diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index ba70c4bc2699..59c1df75e4de 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -1,25 +1,22 @@ /* - * Copyright 2004-2009 Analog Devices Inc. + * Main exception handling logic. + * + * Copyright 2004-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ #include <linux/bug.h> #include <linux/uaccess.h> -#include <linux/interrupt.h> #include <linux/module.h> -#include <linux/kallsyms.h> -#include <linux/fs.h> -#include <linux/rbtree.h> #include <asm/traps.h> -#include <asm/cacheflush.h> #include <asm/cplb.h> -#include <asm/dma.h> #include <asm/blackfin.h> #include <asm/irq_handler.h> #include <linux/irq.h> #include <asm/trace.h> #include <asm/fixed_code.h> +#include <asm/pseudo_instructions.h> #ifdef CONFIG_KGDB # include <linux/kgdb.h> @@ -62,194 +59,6 @@ void __init trap_init(void) CSYNC(); } -static void decode_address(char *buf, unsigned long address) -{ -#ifdef CONFIG_DEBUG_VERBOSE - struct task_struct *p; - struct mm_struct *mm; - unsigned long flags, offset; - unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); - struct rb_node *n; - -#ifdef CONFIG_KALLSYMS - unsigned long symsize; - const char *symname; - char *modname; - char *delim = ":"; - char namebuf[128]; -#endif - - buf += sprintf(buf, "<0x%08lx> ", address); - -#ifdef CONFIG_KALLSYMS - /* look up the address and see if we are in kernel space */ - symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); - - if (symname) { - /* yeah! kernel space! */ - if (!modname) - modname = delim = ""; - sprintf(buf, "{ %s%s%s%s + 0x%lx }", - delim, modname, delim, symname, - (unsigned long)offset); - return; - } -#endif - - if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { - /* Problem in fixed code section? */ - strcat(buf, "/* Maybe fixed code section */"); - return; - - } else if (address < CONFIG_BOOT_LOAD) { - /* Problem somewhere before the kernel start address */ - strcat(buf, "/* Maybe null pointer? */"); - return; - - } else if (address >= COREMMR_BASE) { - strcat(buf, "/* core mmrs */"); - return; - - } else if (address >= SYSMMR_BASE) { - strcat(buf, "/* system mmrs */"); - return; - - } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) { - strcat(buf, "/* on-chip L1 ROM */"); - return; - } - - /* - * Don't walk any of the vmas if we are oopsing, it has been known - * to cause problems - corrupt vmas (kernel crashes) cause double faults - */ - if (oops_in_progress) { - strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); - return; - } - - /* looks like we're off in user-land, so let's walk all the - * mappings of all our processes and see if we can't be a whee - * bit more specific - */ - write_lock_irqsave(&tasklist_lock, flags); - for_each_process(p) { - mm = (in_atomic ? p->mm : get_task_mm(p)); - if (!mm) - continue; - - if (!down_read_trylock(&mm->mmap_sem)) { - if (!in_atomic) - mmput(mm); - continue; - } - - for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) { - struct vm_area_struct *vma; - - vma = rb_entry(n, struct vm_area_struct, vm_rb); - - if (address >= vma->vm_start && address < vma->vm_end) { - char _tmpbuf[256]; - char *name = p->comm; - struct file *file = vma->vm_file; - - if (file) { - char *d_name = d_path(&file->f_path, _tmpbuf, - sizeof(_tmpbuf)); - if (!IS_ERR(d_name)) - name = d_name; - } - - /* FLAT does not have its text aligned to the start of - * the map while FDPIC ELF does ... - */ - - /* before we can check flat/fdpic, we need to - * make sure current is valid - */ - if ((unsigned long)current >= FIXED_CODE_START && - !((unsigned long)current & 0x3)) { - if (current->mm && - (address > current->mm->start_code) && - (address < current->mm->end_code)) - offset = address - current->mm->start_code; - else - offset = (address - vma->vm_start) + - (vma->vm_pgoff << PAGE_SHIFT); - - sprintf(buf, "[ %s + 0x%lx ]", name, offset); - } else - sprintf(buf, "[ %s vma:0x%lx-0x%lx]", - name, vma->vm_start, vma->vm_end); - - up_read(&mm->mmap_sem); - if (!in_atomic) - mmput(mm); - - if (buf[0] == '\0') - sprintf(buf, "[ %s ] dynamic memory", name); - - goto done; - } - } - - up_read(&mm->mmap_sem); - if (!in_atomic) - mmput(mm); - } - - /* - * we were unable to find this address anywhere, - * or some MMs were skipped because they were in use. - */ - sprintf(buf, "/* kernel dynamic memory */"); - -done: - write_unlock_irqrestore(&tasklist_lock, flags); -#else - sprintf(buf, " "); -#endif -} - -asmlinkage void double_fault_c(struct pt_regs *fp) -{ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int j; - trace_buffer_save(j); -#endif - - console_verbose(); - oops_in_progress = 1; -#ifdef CONFIG_DEBUG_VERBOSE - printk(KERN_EMERG "Double Fault\n"); -#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT - if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { - unsigned int cpu = raw_smp_processor_id(); - char buf[150]; - decode_address(buf, cpu_pda[cpu].retx_doublefault); - printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", - (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf); - decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); - decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); - - decode_address(buf, fp->retx); - printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf); - } else -#endif - { - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - dump_bfin_trace_buffer(); - } -#endif - panic("Double Fault - unrecoverable event"); - -} - static int kernel_mode_regs(struct pt_regs *regs) { return regs->ipend & 0xffc0; @@ -260,6 +69,9 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON int j; #endif +#ifdef CONFIG_BFIN_PSEUDODBG_INSNS + int opcode; +#endif unsigned int cpu = raw_smp_processor_id(); const char *strerror = NULL; int sig = 0; @@ -392,6 +204,19 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) } } #endif +#ifdef CONFIG_BFIN_PSEUDODBG_INSNS + /* + * Support for the fake instructions, if the instruction fails, + * then just execute a illegal opcode failure (like normal). + * Don't support these instructions inside the kernel + */ + if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) { + if (execute_pseudodbg_assert(fp, opcode)) + goto traps_done; + if (execute_pseudodbg(fp, opcode)) + goto traps_done; + } +#endif info.si_code = ILL_ILLOPC; sig = SIGILL; strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE); @@ -672,659 +497,44 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) trace_buffer_restore(j); } -/* Typical exception handling routines */ - -#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1) - -/* - * Similar to get_user, do some address checking, then dereference - * Return true on success, false on bad address - */ -static bool get_instruction(unsigned short *val, unsigned short *address) -{ - unsigned long addr = (unsigned long)address; - - /* Check for odd addresses */ - if (addr & 0x1) - return false; - - /* MMR region will never have instructions */ - if (addr >= SYSMMR_BASE) - return false; - - switch (bfin_mem_access_type(addr, 2)) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - *val = *address; - return true; - case BFIN_MEM_ACCESS_DMA: - dma_memcpy(val, address, 2); - return true; - case BFIN_MEM_ACCESS_ITEST: - isram_memcpy(val, address, 2); - return true; - default: /* invalid access */ - return false; - } -} - -/* - * decode the instruction if we are printing out the trace, as it - * makes things easier to follow, without running it through objdump - * These are the normal instructions which cause change of flow, which - * would be at the source of the trace buffer - */ -#if defined(CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_BFIN_HWTRACE_ON) -static void decode_instruction(unsigned short *address) -{ - unsigned short opcode; - - if (get_instruction(&opcode, address)) { - if (opcode == 0x0010) - verbose_printk("RTS"); - else if (opcode == 0x0011) - verbose_printk("RTI"); - else if (opcode == 0x0012) - verbose_printk("RTX"); - else if (opcode == 0x0013) - verbose_printk("RTN"); - else if (opcode == 0x0014) - verbose_printk("RTE"); - else if (opcode == 0x0025) - verbose_printk("EMUEXCPT"); - else if (opcode >= 0x0040 && opcode <= 0x0047) - verbose_printk("STI R%i", opcode & 7); - else if (opcode >= 0x0050 && opcode <= 0x0057) - verbose_printk("JUMP (P%i)", opcode & 7); - else if (opcode >= 0x0060 && opcode <= 0x0067) - verbose_printk("CALL (P%i)", opcode & 7); - else if (opcode >= 0x0070 && opcode <= 0x0077) - verbose_printk("CALL (PC+P%i)", opcode & 7); - else if (opcode >= 0x0080 && opcode <= 0x0087) - verbose_printk("JUMP (PC+P%i)", opcode & 7); - else if (opcode >= 0x0090 && opcode <= 0x009F) - verbose_printk("RAISE 0x%x", opcode & 0xF); - else if (opcode >= 0x00A0 && opcode <= 0x00AF) - verbose_printk("EXCPT 0x%x", opcode & 0xF); - else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF)) - verbose_printk("IF !CC JUMP"); - else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff)) - verbose_printk("IF CC JUMP"); - else if (opcode >= 0x2000 && opcode <= 0x2fff) - verbose_printk("JUMP.S"); - else if (opcode >= 0xe080 && opcode <= 0xe0ff) - verbose_printk("LSETUP"); - else if (opcode >= 0xe200 && opcode <= 0xe2ff) - verbose_printk("JUMP.L"); - else if (opcode >= 0xe300 && opcode <= 0xe3ff) - verbose_printk("CALL pcrel"); - else - verbose_printk("0x%04x", opcode); - } - -} -#endif - -void dump_bfin_trace_buffer(void) -{ -#ifdef CONFIG_DEBUG_VERBOSE -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int tflags, i = 0; - char buf[150]; - unsigned short *addr; -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - int j, index; -#endif - - trace_buffer_save(tflags); - - printk(KERN_NOTICE "Hardware Trace:\n"); - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - printk(KERN_NOTICE "WARNING: Expanded trace turned on - can not trace exceptions\n"); -#endif - - if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { - for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) { - decode_address(buf, (unsigned long)bfin_read_TBUF()); - printk(KERN_NOTICE "%4i Target : %s\n", i, buf); - addr = (unsigned short *)bfin_read_TBUF(); - decode_address(buf, (unsigned long)addr); - printk(KERN_NOTICE " Source : %s ", buf); - decode_instruction(addr); - printk("\n"); - } - } - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - if (trace_buff_offset) - index = trace_buff_offset / 4; - else - index = EXPAND_LEN; - - j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128; - while (j) { - decode_address(buf, software_trace_buff[index]); - printk(KERN_NOTICE "%4i Target : %s\n", i, buf); - index -= 1; - if (index < 0 ) - index = EXPAND_LEN; - decode_address(buf, software_trace_buff[index]); - printk(KERN_NOTICE " Source : %s ", buf); - decode_instruction((unsigned short *)software_trace_buff[index]); - printk("\n"); - index -= 1; - if (index < 0) - index = EXPAND_LEN; - j--; - i++; - } -#endif - - trace_buffer_restore(tflags); -#endif -#endif -} -EXPORT_SYMBOL(dump_bfin_trace_buffer); - -#ifdef CONFIG_BUG -int is_valid_bugaddr(unsigned long addr) -{ - unsigned short opcode; - - if (!get_instruction(&opcode, (unsigned short *)addr)) - return 0; - - return opcode == BFIN_BUG_OPCODE; -} -#endif - -/* - * Checks to see if the address pointed to is either a - * 16-bit CALL instruction, or a 32-bit CALL instruction - */ -static bool is_bfin_call(unsigned short *addr) -{ - unsigned short opcode = 0, *ins_addr; - ins_addr = (unsigned short *)addr; - - if (!get_instruction(&opcode, ins_addr)) - return false; - - if ((opcode >= 0x0060 && opcode <= 0x0067) || - (opcode >= 0x0070 && opcode <= 0x0077)) - return true; - - ins_addr--; - if (!get_instruction(&opcode, ins_addr)) - return false; - - if (opcode >= 0xE300 && opcode <= 0xE3FF) - return true; - - return false; - -} - -void show_stack(struct task_struct *task, unsigned long *stack) -{ -#ifdef CONFIG_PRINTK - unsigned int *addr, *endstack, *fp = 0, *frame; - unsigned short *ins_addr; - char buf[150]; - unsigned int i, j, ret_addr, frame_no = 0; - - /* - * If we have been passed a specific stack, use that one otherwise - * if we have been passed a task structure, use that, otherwise - * use the stack of where the variable "stack" exists - */ - - if (stack == NULL) { - if (task) { - /* We know this is a kernel stack, so this is the start/end */ - stack = (unsigned long *)task->thread.ksp; - endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE); - } else { - /* print out the existing stack info */ - stack = (unsigned long *)&stack; - endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); - } - } else - endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); - - printk(KERN_NOTICE "Stack info:\n"); - decode_address(buf, (unsigned int)stack); - printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); - - if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) { - printk(KERN_NOTICE "Invalid stack pointer\n"); - return; - } - - /* First thing is to look for a frame pointer */ - for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) { - if (*addr & 0x1) - continue; - ins_addr = (unsigned short *)*addr; - ins_addr--; - if (is_bfin_call(ins_addr)) - fp = addr - 1; - - if (fp) { - /* Let's check to see if it is a frame pointer */ - while (fp >= (addr - 1) && fp < endstack - && fp && ((unsigned int) fp & 0x3) == 0) - fp = (unsigned int *)*fp; - if (fp == 0 || fp == endstack) { - fp = addr - 1; - break; - } - fp = 0; - } - } - if (fp) { - frame = fp; - printk(KERN_NOTICE " FP: (0x%p)\n", fp); - } else - frame = 0; - - /* - * Now that we think we know where things are, we - * walk the stack again, this time printing things out - * incase there is no frame pointer, we still look for - * valid return addresses - */ - - /* First time print out data, next time, print out symbols */ - for (j = 0; j <= 1; j++) { - if (j) - printk(KERN_NOTICE "Return addresses in stack:\n"); - else - printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack); - - fp = frame; - frame_no = 0; - - for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0; - addr < endstack; addr++, i++) { - - ret_addr = 0; - if (!j && i % 8 == 0) - printk(KERN_NOTICE "%p:",addr); - - /* if it is an odd address, or zero, just skip it */ - if (*addr & 0x1 || !*addr) - goto print; - - ins_addr = (unsigned short *)*addr; - - /* Go back one instruction, and see if it is a CALL */ - ins_addr--; - ret_addr = is_bfin_call(ins_addr); - print: - if (!j && stack == (unsigned long *)addr) - printk("[%08x]", *addr); - else if (ret_addr) - if (j) { - decode_address(buf, (unsigned int)*addr); - if (frame == addr) { - printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf); - continue; - } - printk(KERN_NOTICE " address : %s\n", buf); - } else - printk("<%08x>", *addr); - else if (fp == addr) { - if (j) - frame = addr+1; - else - printk("(%08x)", *addr); - - fp = (unsigned int *)*addr; - frame_no++; - - } else if (!j) - printk(" %08x ", *addr); - } - if (!j) - printk("\n"); - } -#endif -} -EXPORT_SYMBOL(show_stack); - -void dump_stack(void) +asmlinkage void double_fault_c(struct pt_regs *fp) { - unsigned long stack; #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int tflags; + int j; + trace_buffer_save(j); #endif - trace_buffer_save(tflags); - dump_bfin_trace_buffer(); - show_stack(current, &stack); - trace_buffer_restore(tflags); -} -EXPORT_SYMBOL(dump_stack); -void dump_bfin_process(struct pt_regs *fp) -{ + console_verbose(); + oops_in_progress = 1; #ifdef CONFIG_DEBUG_VERBOSE - /* We should be able to look at fp->ipend, but we don't push it on the - * stack all the time, so do this until we fix that */ - unsigned int context = bfin_read_IPEND(); - - if (oops_in_progress) - verbose_printk(KERN_EMERG "Kernel OOPS in progress\n"); - - if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) - verbose_printk(KERN_NOTICE "HW Error context\n"); - else if (context & 0x0020) - verbose_printk(KERN_NOTICE "Deferred Exception context\n"); - else if (context & 0x3FC0) - verbose_printk(KERN_NOTICE "Interrupt context\n"); - else if (context & 0x4000) - verbose_printk(KERN_NOTICE "Deferred Interrupt context\n"); - else if (context & 0x8000) - verbose_printk(KERN_NOTICE "Kernel process context\n"); - - /* Because we are crashing, and pointers could be bad, we check things - * pretty closely before we use them - */ - if ((unsigned long)current >= FIXED_CODE_START && - !((unsigned long)current & 0x3) && current->pid) { - verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n"); - if (current->comm >= (char *)FIXED_CODE_START) - verbose_printk(KERN_NOTICE "COMM=%s PID=%d", - current->comm, current->pid); - else - verbose_printk(KERN_NOTICE "COMM= invalid"); + printk(KERN_EMERG "Double Fault\n"); +#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT + if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { + unsigned int cpu = raw_smp_processor_id(); + char buf[150]; + decode_address(buf, cpu_pda[cpu].retx_doublefault); + printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", + (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf); + decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr); + printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); + decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr); + printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); - printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu); - if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) - verbose_printk(KERN_NOTICE - "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" - " BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n", - (void *)current->mm->start_code, - (void *)current->mm->end_code, - (void *)current->mm->start_data, - (void *)current->mm->end_data, - (void *)current->mm->end_data, - (void *)current->mm->brk, - (void *)current->mm->start_stack); - else - verbose_printk(KERN_NOTICE "invalid mm\n"); + decode_address(buf, fp->retx); + printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf); } else - verbose_printk(KERN_NOTICE - "No Valid process in current context\n"); -#endif -} - -void dump_bfin_mem(struct pt_regs *fp) -{ -#ifdef CONFIG_DEBUG_VERBOSE - unsigned short *addr, *erraddr, val = 0, err = 0; - char sti = 0, buf[6]; - - erraddr = (void *)fp->pc; - - verbose_printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr); - - for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; - addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; - addr++) { - if (!((unsigned long)addr & 0xF)) - verbose_printk(KERN_NOTICE "0x%p: ", addr); - - if (!get_instruction(&val, addr)) { - val = 0; - sprintf(buf, "????"); - } else - sprintf(buf, "%04x", val); - - if (addr == erraddr) { - verbose_printk("[%s]", buf); - err = val; - } else - verbose_printk(" %s ", buf); - - /* Do any previous instructions turn on interrupts? */ - if (addr <= erraddr && /* in the past */ - ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */ - val == 0x017b)) /* [SP++] = RETI */ - sti = 1; - } - - verbose_printk("\n"); - - /* Hardware error interrupts can be deferred */ - if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && - oops_in_progress)){ - verbose_printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n"); -#ifndef CONFIG_DEBUG_HWERR - verbose_printk(KERN_NOTICE -"The remaining message may be meaningless\n" -"You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n"); -#else - /* If we are handling only one peripheral interrupt - * and current mm and pid are valid, and the last error - * was in that user space process's text area - * print it out - because that is where the problem exists - */ - if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) && - (current->pid && current->mm)) { - /* And the last RETI points to the current userspace context */ - if ((fp + 1)->pc >= current->mm->start_code && - (fp + 1)->pc <= current->mm->end_code) { - verbose_printk(KERN_NOTICE "It might be better to look around here :\n"); - verbose_printk(KERN_NOTICE "-------------------------------------------\n"); - show_regs(fp + 1); - verbose_printk(KERN_NOTICE "-------------------------------------------\n"); - } - } -#endif - } -#endif -} - -void show_regs(struct pt_regs *fp) -{ -#ifdef CONFIG_DEBUG_VERBOSE - char buf [150]; - struct irqaction *action; - unsigned int i; - unsigned long flags = 0; - unsigned int cpu = raw_smp_processor_id(); - unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); - - verbose_printk(KERN_NOTICE "\n"); - if (CPUID != bfin_cpuid()) - verbose_printk(KERN_NOTICE "Compiled for cpu family 0x%04x (Rev %d), " - "but running on:0x%04x (Rev %d)\n", - CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid()); - - verbose_printk(KERN_NOTICE "ADSP-%s-0.%d", - CPU, bfin_compiled_revid()); - - if (bfin_compiled_revid() != bfin_revid()) - verbose_printk("(Detected 0.%d)", bfin_revid()); - - verbose_printk(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n", - get_cclk()/1000000, get_sclk()/1000000, -#ifdef CONFIG_MPU - "mpu on" -#else - "mpu off" -#endif - ); - - verbose_printk(KERN_NOTICE "%s", linux_banner); - - verbose_printk(KERN_NOTICE "\nSEQUENCER STATUS:\t\t%s\n", print_tainted()); - verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n", - (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg); - if (fp->ipend & EVT_IRPTEN) - verbose_printk(KERN_NOTICE " Global Interrupts Disabled (IPEND[4])\n"); - if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 | - EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR))) - verbose_printk(KERN_NOTICE " Peripheral interrupts masked off\n"); - if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14))) - verbose_printk(KERN_NOTICE " Kernel interrupts masked off\n"); - if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { - verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", - (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); -#ifdef EBIU_ERRMST - /* If the error was from the EBIU, print it out */ - if (bfin_read_EBIU_ERRMST() & CORE_ERROR) { - verbose_printk(KERN_NOTICE " EBIU Error Reason : 0x%04x\n", - bfin_read_EBIU_ERRMST()); - verbose_printk(KERN_NOTICE " EBIU Error Address : 0x%08x\n", - bfin_read_EBIU_ERRADD()); - } #endif + { + dump_bfin_process(fp); + dump_bfin_mem(fp); + show_regs(fp); + dump_bfin_trace_buffer(); } - verbose_printk(KERN_NOTICE " EXCAUSE : 0x%lx\n", - fp->seqstat & SEQSTAT_EXCAUSE); - for (i = 2; i <= 15 ; i++) { - if (fp->ipend & (1 << i)) { - if (i != 4) { - decode_address(buf, bfin_read32(EVT0 + 4*i)); - verbose_printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf); - } else - verbose_printk(KERN_NOTICE " interrupts disabled\n"); - } - } - - /* if no interrupts are going off, don't print this out */ - if (fp->ipend & ~0x3F) { - for (i = 0; i < (NR_IRQS - 1); i++) { - if (!in_atomic) - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - - action = irq_desc[i].action; - if (!action) - goto unlock; - - decode_address(buf, (unsigned int)action->handler); - verbose_printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf); - for (action = action->next; action; action = action->next) { - decode_address(buf, (unsigned int)action->handler); - verbose_printk(", %s", buf); - } - verbose_printk("\n"); -unlock: - if (!in_atomic) - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - } - - decode_address(buf, fp->rete); - verbose_printk(KERN_NOTICE " RETE: %s\n", buf); - decode_address(buf, fp->retn); - verbose_printk(KERN_NOTICE " RETN: %s\n", buf); - decode_address(buf, fp->retx); - verbose_printk(KERN_NOTICE " RETX: %s\n", buf); - decode_address(buf, fp->rets); - verbose_printk(KERN_NOTICE " RETS: %s\n", buf); - decode_address(buf, fp->pc); - verbose_printk(KERN_NOTICE " PC : %s\n", buf); - - if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && - (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { - decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); - verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); - decode_address(buf, cpu_pda[cpu].icplb_fault_addr); - verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf); - } - - verbose_printk(KERN_NOTICE "PROCESSOR STATE:\n"); - verbose_printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", - fp->r0, fp->r1, fp->r2, fp->r3); - verbose_printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", - fp->r4, fp->r5, fp->r6, fp->r7); - verbose_printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", - fp->p0, fp->p1, fp->p2, fp->p3); - verbose_printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", - fp->p4, fp->p5, fp->fp, (long)fp); - verbose_printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n", - fp->lb0, fp->lt0, fp->lc0); - verbose_printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n", - fp->lb1, fp->lt1, fp->lc1); - verbose_printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", - fp->b0, fp->l0, fp->m0, fp->i0); - verbose_printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", - fp->b1, fp->l1, fp->m1, fp->i1); - verbose_printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", - fp->b2, fp->l2, fp->m2, fp->i2); - verbose_printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", - fp->b3, fp->l3, fp->m3, fp->i3); - verbose_printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", - fp->a0w, fp->a0x, fp->a1w, fp->a1x); - - verbose_printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n", - rdusp(), fp->astat); - - verbose_printk(KERN_NOTICE "\n"); #endif -} - -#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1 -asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text)); -#endif - -static DEFINE_SPINLOCK(bfin_spinlock_lock); - -asmlinkage int sys_bfin_spinlock(int *p) -{ - int ret, tmp = 0; - - spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */ - ret = get_user(tmp, p); - if (likely(ret == 0)) { - if (unlikely(tmp)) - ret = 1; - else - put_user(1, p); - } - spin_unlock(&bfin_spinlock_lock); - return ret; -} - -int bfin_request_exception(unsigned int exception, void (*handler)(void)) -{ - void (*curr_handler)(void); - - if (exception > 0x3F) - return -EINVAL; - - curr_handler = ex_table[exception]; - - if (curr_handler != ex_replaceable) - return -EBUSY; - - ex_table[exception] = handler; + panic("Double Fault - unrecoverable event"); - return 0; } -EXPORT_SYMBOL(bfin_request_exception); - -int bfin_free_exception(unsigned int exception, void (*handler)(void)) -{ - void (*curr_handler)(void); - - if (exception > 0x3F) - return -EINVAL; - - curr_handler = ex_table[exception]; - if (curr_handler != handler) - return -EBUSY; - - ex_table[exception] = ex_replaceable; - - return 0; -} -EXPORT_SYMBOL(bfin_free_exception); void panic_cplb_error(int cplb_panic, struct pt_regs *fp) { @@ -1349,3 +559,23 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp) dump_stack(); panic("Unrecoverable event"); } + +#ifdef CONFIG_BUG +int is_valid_bugaddr(unsigned long addr) +{ + unsigned int opcode; + + if (!get_instruction(&opcode, (unsigned short *)addr)) + return 0; + + return opcode == BFIN_BUG_OPCODE; +} +#endif + +/* stub this out */ +#ifndef CONFIG_DEBUG_VERBOSE +void show_regs(struct pt_regs *fp) +{ + +} +#endif diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S index c30d99b10969..eab1bef3f5bf 100644 --- a/arch/blackfin/lib/memset.S +++ b/arch/blackfin/lib/memset.S @@ -20,6 +20,7 @@ * R1 = filler byte * R2 = count * Favours word aligned data. + * The strncpy assumes that I0 and I1 are not used in this function */ ENTRY(_memset) diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S new file mode 100644 index 000000000000..d7c1d158973b --- /dev/null +++ b/arch/blackfin/lib/strcmp.S @@ -0,0 +1,43 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the ADI BSD license or the GPL-2 (or later) + */ + +#include <linux/linkage.h> + +/* void *strcmp(char *s1, const char *s2); + * R0 = address (s1) + * R1 = address (s2) + * + * Returns an integer less than, equal to, or greater than zero if s1 + * (or the first n bytes thereof) is found, respectively, to be less + * than, to match, or be greater than s2. + */ + +#ifdef CONFIG_STRCMP_L1 +.section .l1.text +#else +.text +#endif + +.align 2 + +ENTRY(_strcmp) + P0 = R0 ; /* s1 */ + P1 = R1 ; /* s2 */ + +1: + R0 = B[P0++] (Z); /* get *s1 */ + R1 = B[P1++] (Z); /* get *s2 */ + CC = R0 == R1; /* compare a byte */ + if ! cc jump 2f; /* not equal, break out */ + CC = R0; /* at end of s1? */ + if cc jump 1b (bp); /* no, keep going */ + jump.s 3f; /* strings are equal */ +2: + R0 = R0 - R1; /* *s1 - *s2 */ +3: + RTS; + +ENDPROC(_strcmp) diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c deleted file mode 100644 index fde39a1950ce..000000000000 --- a/arch/blackfin/lib/strcmp.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Provide symbol in case str func is not inlined. - * - * Copyright (c) 2006-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define strcmp __inline_strcmp -#include <asm/string.h> -#undef strcmp - -#include <linux/module.h> - -int strcmp(const char *dest, const char *src) -{ - return __inline_strcmp(dest, src); -} -EXPORT_SYMBOL(strcmp); diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S new file mode 100644 index 000000000000..a6a0c6363806 --- /dev/null +++ b/arch/blackfin/lib/strcpy.S @@ -0,0 +1,35 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the ADI BSD license or the GPL-2 (or later) + */ + +#include <linux/linkage.h> + +/* void *strcpy(char *dest, const char *src); + * R0 = address (dest) + * R1 = address (src) + * + * Returns a pointer to the destination string dest + */ + +#ifdef CONFIG_STRCPY_L1 +.section .l1.text +#else +.text +#endif + +.align 2 + +ENTRY(_strcpy) + P0 = R0 ; /* dst*/ + P1 = R1 ; /* src*/ + +1: + R1 = B [P1++] (Z); + B [P0++] = R1; + CC = R1; + if cc jump 1b (bp); + RTS; + +ENDPROC(_strcpy) diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c deleted file mode 100644 index 2a8836b1f4d3..000000000000 --- a/arch/blackfin/lib/strcpy.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Provide symbol in case str func is not inlined. - * - * Copyright (c) 2006-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define strcpy __inline_strcpy -#include <asm/string.h> -#undef strcpy - -#include <linux/module.h> - -char *strcpy(char *dest, const char *src) -{ - return __inline_strcpy(dest, src); -} -EXPORT_SYMBOL(strcpy); diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S new file mode 100644 index 000000000000..6da37c34a847 --- /dev/null +++ b/arch/blackfin/lib/strncmp.S @@ -0,0 +1,52 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the ADI BSD license or the GPL-2 (or later) + */ + +#include <linux/linkage.h> + +/* void *strncpy(char *s1, const char *s2, size_t n); + * R0 = address (dest) + * R1 = address (src) + * R2 = size (n) + * Returns a pointer to the destination string dest + */ + +#ifdef CONFIG_STRNCMP_L1 +.section .l1.text +#else +.text +#endif + +.align 2 + +ENTRY(_strncmp) + CC = R2 == 0; + if CC JUMP 5f; + + P0 = R0 ; /* s1 */ + P1 = R1 ; /* s2 */ +1: + R0 = B[P0++] (Z); /* get *s1 */ + R1 = B[P1++] (Z); /* get *s2 */ + CC = R0 == R1; /* compare a byte */ + if ! cc jump 3f; /* not equal, break out */ + CC = R0; /* at end of s1? */ + if ! cc jump 4f; /* yes, all done */ + R2 += -1; /* no, adjust count */ + CC = R2 == 0; + if ! cc jump 1b (bp); /* more to do, keep going */ +2: + R0 = 0; /* strings are equal */ + jump.s 4f; +3: + R0 = R0 - R1; /* *s1 - *s2 */ +4: + RTS; + +5: + R0 = 0; + RTS; + +ENDPROC(_strncmp) diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c deleted file mode 100644 index 46518b1d2983..000000000000 --- a/arch/blackfin/lib/strncmp.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Provide symbol in case str func is not inlined. - * - * Copyright (c) 2006-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define strncmp __inline_strncmp -#include <asm/string.h> -#include <linux/module.h> -#undef strncmp - -int strncmp(const char *cs, const char *ct, size_t count) -{ - return __inline_strncmp(cs, ct, count); -} -EXPORT_SYMBOL(strncmp); diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S new file mode 100644 index 000000000000..f3931d50b4a7 --- /dev/null +++ b/arch/blackfin/lib/strncpy.S @@ -0,0 +1,85 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the ADI BSD license or the GPL-2 (or later) + */ + +#include <linux/linkage.h> +#include <asm/context.S> + +/* void *strncpy(char *dest, const char *src, size_t n); + * R0 = address (dest) + * R1 = address (src) + * R2 = size + * Returns a pointer (R0) to the destination string dest + * we do this by not changing R0 + */ + +#ifdef CONFIG_STRNCPY_L1 +.section .l1.text +#else +.text +#endif + +.align 2 + +ENTRY(_strncpy) + CC = R2 == 0; + if CC JUMP 4f; + + P2 = R2 ; /* size */ + P0 = R0 ; /* dst*/ + P1 = R1 ; /* src*/ + + LSETUP (1f, 2f) LC0 = P2; +1: + R1 = B [P1++] (Z); + B [P0++] = R1; + CC = R1 == 0; +2: + if CC jump 3f; + + RTS; + + /* if src is shorter than n, we need to null pad bytes in dest + * but, we can get here when the last byte is zero, and we don't + * want to copy an extra byte at the end, so we need to check + */ +3: + R2 = LC0; + CC = R2 + if ! CC jump 6f; + + /* if the required null padded portion is small, do it here, rather than + * handling the overhead of memset (which is OK when things are big). + */ + R3 = 0x20; + CC = R2 < R3; + IF CC jump 4f; + + R2 += -1; + + /* Set things up for memset + * R0 = address + * R1 = filler byte (this case it's zero, set above) + * R2 = count (set above) + */ + + I1 = R0; + R0 = RETS; + I0 = R0; + R0 = P0; + pseudo_long_call _memset, p0; + R0 = I0; + RETS = R0; + R0 = I1; + RTS; + +4: + LSETUP(5f, 5f) LC0; +5: + B [P0++] = R1; +6: + RTS; + +ENDPROC(_strncpy) diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c deleted file mode 100644 index ea1dc6bf2373..000000000000 --- a/arch/blackfin/lib/strncpy.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Provide symbol in case str func is not inlined. - * - * Copyright (c) 2006-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define strncpy __inline_strncpy -#include <asm/string.h> -#undef strncpy - -#include <linux/module.h> - -char *strncpy(char *dest, const char *src, size_t n) -{ - return __inline_strncpy(dest, src, n); -} -EXPORT_SYMBOL(strncpy); diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index ebe76d1e874a..f392af641657 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -98,6 +98,10 @@ static struct musb_hdrc_config musb_config = { .num_eps = 8, .dma_channels = 8, .gpio_vrsel = GPIO_PF11, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, }; static struct musb_hdrc_platform_data musb_plat = { diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 55069af4f67d..606eb36b9d6e 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -62,6 +62,10 @@ static struct musb_hdrc_config musb_config = { .num_eps = 8, .dma_channels = 8, .gpio_vrsel = GPIO_PG13, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, }; static struct musb_hdrc_platform_data musb_plat = { diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 923383386aa1..a05c967a24cf 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -102,6 +102,10 @@ static struct musb_hdrc_config musb_config = { .num_eps = 8, .dma_channels = 8, .gpio_vrsel = GPIO_PG13, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, }; static struct musb_hdrc_platform_data musb_plat = { diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index c489d602c590..05d45994480e 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -23,12 +23,13 @@ #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/reboot.h> +#include <asm/portmux.h> #include <linux/spi/ad7877.h> /* * Name the Board for the /proc/cpuinfo */ -char *bfin_board_name = "CamSig Minotaur BF537"; +const char bfin_board_name[] = "CamSig Minotaur BF537"; #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) static struct resource bfin_pcmcia_cf_resources[] = { diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 066d5c261f47..cf396ea40092 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1702,628 +1702,6 @@ #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ -/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ -/* CAN_CONTROL Masks */ -#define SRS 0x0001 /* Software Reset */ -#define DNM 0x0002 /* Device Net Mode */ -#define ABO 0x0004 /* Auto-Bus On Enable */ -#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ -#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ -#define SMR 0x0020 /* Sleep Mode Request */ -#define CSR 0x0040 /* CAN Suspend Mode Request */ -#define CCR 0x0080 /* CAN Configuration Mode Request */ - -/* CAN_STATUS Masks */ -#define WT 0x0001 /* TX Warning Flag */ -#define WR 0x0002 /* RX Warning Flag */ -#define EP 0x0004 /* Error Passive Mode */ -#define EBO 0x0008 /* Error Bus Off Mode */ -#define SMA 0x0020 /* Sleep Mode Acknowledge */ -#define CSA 0x0040 /* Suspend Mode Acknowledge */ -#define CCA 0x0080 /* Configuration Mode Acknowledge */ -#define MBPTR 0x1F00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode */ -#define REC 0x8000 /* Receive Mode */ - -/* CAN_CLOCK Masks */ -#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ - -/* CAN_TIMING Masks */ -#define TSEG1 0x000F /* Time Segment 1 */ -#define TSEG2 0x0070 /* Time Segment 2 */ -#define SAM 0x0080 /* Sampling */ -#define SJW 0x0300 /* Synchronization Jump Width */ - -/* CAN_DEBUG Masks */ -#define DEC 0x0001 /* Disable CAN Error Counters */ -#define DRI 0x0002 /* Disable CAN RX Input */ -#define DTO 0x0004 /* Disable CAN TX Output */ -#define DIL 0x0008 /* Disable CAN Internal Loop */ -#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ -#define MRB 0x0020 /* Mode Read Back Enable */ -#define CDE 0x8000 /* CAN Debug Enable */ - -/* CAN_CEC Masks */ -#define RXECNT 0x00FF /* Receive Error Counter */ -#define TXECNT 0xFF00 /* Transmit Error Counter */ - -/* CAN_INTR Masks */ -#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ -#define MBRIF MBRIRQ /* legacy */ -#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ -#define MBTIF MBTIRQ /* legacy */ -#define GIRQ 0x0004 /* Global Interrupt */ -#define SMACK 0x0008 /* Sleep Mode Acknowledge */ -#define CANTX 0x0040 /* CAN TX Bus Value */ -#define CANRX 0x0080 /* CAN RX Bus Value */ - -/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ -#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define IDE 0x2000 /* Identifier Extension */ -#define RTR 0x4000 /* Remote Frame Transmission Request */ -#define AME 0x8000 /* Acceptance Mask Enable */ - -/* CAN_MBxx_TIMESTAMP Masks */ -#define TSV 0xFFFF /* Timestamp */ - -/* CAN_MBxx_LENGTH Masks */ -#define DLC 0x000F /* Data Length Code */ - -/* CAN_AMxxH and CAN_AMxxL Masks */ -#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ -#define FMD 0x4000 /* Full Mask Data Field Enable */ -#define FDF 0x8000 /* Filter On Data Field Enable */ - -/* CAN_MC1 Masks */ -#define MC0 0x0001 /* Enable Mailbox 0 */ -#define MC1 0x0002 /* Enable Mailbox 1 */ -#define MC2 0x0004 /* Enable Mailbox 2 */ -#define MC3 0x0008 /* Enable Mailbox 3 */ -#define MC4 0x0010 /* Enable Mailbox 4 */ -#define MC5 0x0020 /* Enable Mailbox 5 */ -#define MC6 0x0040 /* Enable Mailbox 6 */ -#define MC7 0x0080 /* Enable Mailbox 7 */ -#define MC8 0x0100 /* Enable Mailbox 8 */ -#define MC9 0x0200 /* Enable Mailbox 9 */ -#define MC10 0x0400 /* Enable Mailbox 10 */ -#define MC11 0x0800 /* Enable Mailbox 11 */ -#define MC12 0x1000 /* Enable Mailbox 12 */ -#define MC13 0x2000 /* Enable Mailbox 13 */ -#define MC14 0x4000 /* Enable Mailbox 14 */ -#define MC15 0x8000 /* Enable Mailbox 15 */ - -/* CAN_MC2 Masks */ -#define MC16 0x0001 /* Enable Mailbox 16 */ -#define MC17 0x0002 /* Enable Mailbox 17 */ -#define MC18 0x0004 /* Enable Mailbox 18 */ -#define MC19 0x0008 /* Enable Mailbox 19 */ -#define MC20 0x0010 /* Enable Mailbox 20 */ -#define MC21 0x0020 /* Enable Mailbox 21 */ -#define MC22 0x0040 /* Enable Mailbox 22 */ -#define MC23 0x0080 /* Enable Mailbox 23 */ -#define MC24 0x0100 /* Enable Mailbox 24 */ -#define MC25 0x0200 /* Enable Mailbox 25 */ -#define MC26 0x0400 /* Enable Mailbox 26 */ -#define MC27 0x0800 /* Enable Mailbox 27 */ -#define MC28 0x1000 /* Enable Mailbox 28 */ -#define MC29 0x2000 /* Enable Mailbox 29 */ -#define MC30 0x4000 /* Enable Mailbox 30 */ -#define MC31 0x8000 /* Enable Mailbox 31 */ - -/* CAN_MD1 Masks */ -#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ -#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ -#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ -#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ -#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ -#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ -#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ -#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ -#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ -#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ -#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ -#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ -#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ -#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ -#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ -#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ - -/* CAN_MD2 Masks */ -#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ -#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ -#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ -#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ -#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ -#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ -#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ -#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ -#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ -#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ -#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ -#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ -#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ -#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ -#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ -#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ - -/* CAN_RMP1 Masks */ -#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ -#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ -#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ -#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ -#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ -#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ -#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ -#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ -#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ -#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ -#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ -#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ -#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ -#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ -#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ -#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ - -/* CAN_RMP2 Masks */ -#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ -#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ -#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ -#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ -#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ -#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ -#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ -#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ -#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ -#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ -#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ -#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ -#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ -#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ -#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ -#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ - -/* CAN_RML1 Masks */ -#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ -#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ -#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ -#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ -#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ -#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ -#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ -#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ -#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ -#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ -#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ -#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ -#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ -#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ -#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ -#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ - -/* CAN_RML2 Masks */ -#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ -#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ -#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ -#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ -#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ -#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ -#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ -#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ -#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ -#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ -#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ -#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ -#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ -#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ -#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ -#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ - -/* CAN_OPSS1 Masks */ -#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ -#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ -#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ -#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ -#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ -#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ -#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ -#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ -#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ -#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ -#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ -#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ -#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ -#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ -#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ -#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ - -/* CAN_OPSS2 Masks */ -#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ -#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ -#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ -#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ -#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ -#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ -#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ -#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ -#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ -#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ -#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ -#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ -#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ -#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ -#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ -#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ - -/* CAN_TRR1 Masks */ -#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ -#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ -#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ -#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ -#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ -#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ -#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ -#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ -#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ -#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ -#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ -#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ -#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ -#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ -#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ -#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ - -/* CAN_TRR2 Masks */ -#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ -#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ -#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ -#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ -#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ -#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ -#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ -#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ -#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ -#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ -#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ -#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ -#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ -#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ -#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ -#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ - -/* CAN_TRS1 Masks */ -#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ -#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ -#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ -#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ -#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ -#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ -#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ -#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ -#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ -#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ -#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ -#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ -#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ -#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ -#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ -#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ - -/* CAN_TRS2 Masks */ -#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ -#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ -#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ -#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ -#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ -#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ -#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ -#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ -#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ -#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ -#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ -#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ -#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ -#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ -#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ -#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ - -/* CAN_AA1 Masks */ -#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ -#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ -#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ -#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ -#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ -#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ -#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ -#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ -#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ -#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ -#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ -#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ -#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ -#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ -#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ -#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ - -/* CAN_AA2 Masks */ -#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ -#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ -#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ -#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ -#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ -#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ -#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ -#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ -#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ -#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ -#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ -#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ -#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ -#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ -#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ -#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ - -/* CAN_TA1 Masks */ -#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ -#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ -#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ -#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ -#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ -#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ -#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ -#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ -#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ -#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ -#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ -#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ -#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ -#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ -#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ -#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ - -/* CAN_TA2 Masks */ -#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ -#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ -#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ -#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ -#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ -#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ -#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ -#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ -#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ -#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ -#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ -#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ -#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ -#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ -#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ -#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ - -/* CAN_MBTD Masks */ -#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ -#define TDA 0x0040 /* Temporary Disable Acknowledge */ -#define TDR 0x0080 /* Temporary Disable Request */ - -/* CAN_RFH1 Masks */ -#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ -#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ -#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ -#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ -#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ -#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ -#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ -#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ -#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ -#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ -#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ -#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ -#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ -#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ -#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ -#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ - -/* CAN_RFH2 Masks */ -#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ -#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ -#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ -#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ -#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ -#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ -#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ -#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ -#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ -#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ -#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ -#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ -#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ -#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ -#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ -#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ - -/* CAN_MBTIF1 Masks */ -#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ -#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ -#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ -#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ -#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ -#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ -#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ -#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ -#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ -#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ -#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ -#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ -#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ -#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ -#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ -#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ - -/* CAN_MBTIF2 Masks */ -#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ -#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ -#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ -#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ -#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ -#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ -#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ -#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ -#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ -#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ -#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ -#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ -#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ -#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ -#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ -#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ - -/* CAN_MBRIF1 Masks */ -#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ -#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ -#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ -#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ -#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ -#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ -#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ -#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ -#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ -#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ -#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ -#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ -#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ -#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ -#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ -#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ - -/* CAN_MBRIF2 Masks */ -#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ -#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ -#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ -#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ -#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ -#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ -#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ -#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ -#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ -#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ -#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ -#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ -#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ -#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ -#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ -#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ - -/* CAN_MBIM1 Masks */ -#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ -#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ -#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ -#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ -#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ -#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ -#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ -#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ -#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ -#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ -#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ -#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ -#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ -#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ -#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ -#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ - -/* CAN_MBIM2 Masks */ -#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ -#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ -#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ -#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ -#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ -#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ -#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ -#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ -#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ -#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ -#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ -#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ -#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ -#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ -#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ -#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ - -/* CAN_GIM Masks */ -#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ -#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ -#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ -#define BOIM 0x0008 /* Enable Bus Off Interrupt */ -#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ -#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ -#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ -#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ -#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ -#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ -#define ADIM 0x0400 /* Enable Access Denied Interrupt */ - -/* CAN_GIS Masks */ -#define EWTIS 0x0001 /* TX Error Count IRQ Status */ -#define EWRIS 0x0002 /* RX Error Count IRQ Status */ -#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ -#define BOIS 0x0008 /* Bus Off IRQ Status */ -#define WUIS 0x0010 /* Wake-Up IRQ Status */ -#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ -#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ -#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ -#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ -#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ -#define ADIS 0x0400 /* Access Denied IRQ Status */ - -/* CAN_GIF Masks */ -#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ -#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ -#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ -#define BOIF 0x0008 /* Bus Off IRQ Flag */ -#define WUIF 0x0010 /* Wake-Up IRQ Flag */ -#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ -#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ -#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ -#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ -#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ -#define ADIF 0x0400 /* Access Denied IRQ Flag */ - -/* CAN_UCCNF Masks */ -#define UCCNF 0x000F /* Universal Counter Mode */ -#define UC_STAMP 0x0001 /* Timestamp Mode */ -#define UC_WDOG 0x0002 /* Watchdog Mode */ -#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ -#define UC_ERROR 0x0006 /* CAN Error Frame Count */ -#define UC_OVER 0x0007 /* CAN Overload Frame Count */ -#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ -#define UC_AA 0x0009 /* TX Abort Count */ -#define UC_TA 0x000A /* TX Successful Count */ -#define UC_REJECT 0x000B /* RX Message Rejected Count */ -#define UC_RML 0x000C /* RX Message Lost Count */ -#define UC_RX 0x000D /* Total Successful RX Messages Count */ -#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ -#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ -#define UCRC 0x0020 /* Universal Counter Reload/Clear */ -#define UCCT 0x0040 /* Universal Counter CAN Trigger */ -#define UCE 0x0080 /* Universal Counter Enable */ - -/* CAN_ESR Masks */ -#define ACKE 0x0004 /* Acknowledge Error */ -#define SER 0x0008 /* Stuff Error */ -#define CRCE 0x0010 /* CRC Error */ -#define SA0 0x0020 /* Stuck At Dominant Error */ -#define BEF 0x0040 /* Bit Error Flag */ -#define FER 0x0080 /* Form Error Flag */ - -/* CAN_EWR Masks */ -#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ -#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ - /* ******************* PIN CONTROL REGISTER MASKS ************************/ /* PORT_MUX Masks */ #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h index 789a4f226f7b..1a6d617c5fcf 100644 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ b/arch/blackfin/mach-bf537/include/mach/irq.h @@ -74,7 +74,7 @@ #define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ #define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ -#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */ +#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */ #define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ #define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ #define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index fac563e6f62f..d7061d9f2a83 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -2418,625 +2418,4 @@ #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - -/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ -/* CAN_CONTROL Masks */ -#define SRS 0x0001 /* Software Reset */ -#define DNM 0x0002 /* Device Net Mode */ -#define ABO 0x0004 /* Auto-Bus On Enable */ -#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ -#define SMR 0x0020 /* Sleep Mode Request */ -#define CSR 0x0040 /* CAN Suspend Mode Request */ -#define CCR 0x0080 /* CAN Configuration Mode Request */ - -/* CAN_STATUS Masks */ -#define WT 0x0001 /* TX Warning Flag */ -#define WR 0x0002 /* RX Warning Flag */ -#define EP 0x0004 /* Error Passive Mode */ -#define EBO 0x0008 /* Error Bus Off Mode */ -#define CSA 0x0040 /* Suspend Mode Acknowledge */ -#define CCA 0x0080 /* Configuration Mode Acknowledge */ -#define MBPTR 0x1F00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode */ -#define REC 0x8000 /* Receive Mode */ - -/* CAN_CLOCK Masks */ -#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ - -/* CAN_TIMING Masks */ -#define TSEG1 0x000F /* Time Segment 1 */ -#define TSEG2 0x0070 /* Time Segment 2 */ -#define SAM 0x0080 /* Sampling */ -#define SJW 0x0300 /* Synchronization Jump Width */ - -/* CAN_DEBUG Masks */ -#define DEC 0x0001 /* Disable CAN Error Counters */ -#define DRI 0x0002 /* Disable CAN RX Input */ -#define DTO 0x0004 /* Disable CAN TX Output */ -#define DIL 0x0008 /* Disable CAN Internal Loop */ -#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ -#define MRB 0x0020 /* Mode Read Back Enable */ -#define CDE 0x8000 /* CAN Debug Enable */ - -/* CAN_CEC Masks */ -#define RXECNT 0x00FF /* Receive Error Counter */ -#define TXECNT 0xFF00 /* Transmit Error Counter */ - -/* CAN_INTR Masks */ -#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ -#define MBRIF MBRIRQ /* legacy */ -#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ -#define MBTIF MBTIRQ /* legacy */ -#define GIRQ 0x0004 /* Global Interrupt */ -#define SMACK 0x0008 /* Sleep Mode Acknowledge */ -#define CANTX 0x0040 /* CAN TX Bus Value */ -#define CANRX 0x0080 /* CAN RX Bus Value */ - -/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ -#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define IDE 0x2000 /* Identifier Extension */ -#define RTR 0x4000 /* Remote Frame Transmission Request */ -#define AME 0x8000 /* Acceptance Mask Enable */ - -/* CAN_MBxx_TIMESTAMP Masks */ -#define TSV 0xFFFF /* Timestamp */ - -/* CAN_MBxx_LENGTH Masks */ -#define DLC 0x000F /* Data Length Code */ - -/* CAN_AMxxH and CAN_AMxxL Masks */ -#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ -#define FMD 0x4000 /* Full Mask Data Field Enable */ -#define FDF 0x8000 /* Filter On Data Field Enable */ - -/* CAN_MC1 Masks */ -#define MC0 0x0001 /* Enable Mailbox 0 */ -#define MC1 0x0002 /* Enable Mailbox 1 */ -#define MC2 0x0004 /* Enable Mailbox 2 */ -#define MC3 0x0008 /* Enable Mailbox 3 */ -#define MC4 0x0010 /* Enable Mailbox 4 */ -#define MC5 0x0020 /* Enable Mailbox 5 */ -#define MC6 0x0040 /* Enable Mailbox 6 */ -#define MC7 0x0080 /* Enable Mailbox 7 */ -#define MC8 0x0100 /* Enable Mailbox 8 */ -#define MC9 0x0200 /* Enable Mailbox 9 */ -#define MC10 0x0400 /* Enable Mailbox 10 */ -#define MC11 0x0800 /* Enable Mailbox 11 */ -#define MC12 0x1000 /* Enable Mailbox 12 */ -#define MC13 0x2000 /* Enable Mailbox 13 */ -#define MC14 0x4000 /* Enable Mailbox 14 */ -#define MC15 0x8000 /* Enable Mailbox 15 */ - -/* CAN_MC2 Masks */ -#define MC16 0x0001 /* Enable Mailbox 16 */ -#define MC17 0x0002 /* Enable Mailbox 17 */ -#define MC18 0x0004 /* Enable Mailbox 18 */ -#define MC19 0x0008 /* Enable Mailbox 19 */ -#define MC20 0x0010 /* Enable Mailbox 20 */ -#define MC21 0x0020 /* Enable Mailbox 21 */ -#define MC22 0x0040 /* Enable Mailbox 22 */ -#define MC23 0x0080 /* Enable Mailbox 23 */ -#define MC24 0x0100 /* Enable Mailbox 24 */ -#define MC25 0x0200 /* Enable Mailbox 25 */ -#define MC26 0x0400 /* Enable Mailbox 26 */ -#define MC27 0x0800 /* Enable Mailbox 27 */ -#define MC28 0x1000 /* Enable Mailbox 28 */ -#define MC29 0x2000 /* Enable Mailbox 29 */ -#define MC30 0x4000 /* Enable Mailbox 30 */ -#define MC31 0x8000 /* Enable Mailbox 31 */ - -/* CAN_MD1 Masks */ -#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ -#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ -#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ -#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ -#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ -#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ -#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ -#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ -#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ -#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ -#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ -#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ -#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ -#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ -#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ -#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ - -/* CAN_MD2 Masks */ -#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ -#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ -#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ -#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ -#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ -#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ -#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ -#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ -#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ -#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ -#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ -#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ -#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ -#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ -#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ -#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ - -/* CAN_RMP1 Masks */ -#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ -#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ -#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ -#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ -#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ -#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ -#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ -#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ -#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ -#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ -#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ -#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ -#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ -#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ -#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ -#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ - -/* CAN_RMP2 Masks */ -#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ -#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ -#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ -#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ -#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ -#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ -#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ -#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ -#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ -#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ -#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ -#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ -#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ -#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ -#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ -#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ - -/* CAN_RML1 Masks */ -#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ -#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ -#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ -#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ -#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ -#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ -#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ -#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ -#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ -#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ -#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ -#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ -#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ -#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ -#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ -#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ - -/* CAN_RML2 Masks */ -#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ -#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ -#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ -#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ -#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ -#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ -#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ -#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ -#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ -#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ -#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ -#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ -#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ -#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ -#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ -#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ - -/* CAN_OPSS1 Masks */ -#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ -#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ -#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ -#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ -#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ -#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ -#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ -#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ -#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ -#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ -#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ -#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ -#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ -#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ -#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ -#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ - -/* CAN_OPSS2 Masks */ -#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ -#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ -#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ -#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ -#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ -#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ -#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ -#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ -#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ -#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ -#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ -#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ -#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ -#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ -#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ -#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ - -/* CAN_TRR1 Masks */ -#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ -#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ -#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ -#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ -#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ -#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ -#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ -#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ -#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ -#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ -#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ -#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ -#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ -#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ -#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ -#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ - -/* CAN_TRR2 Masks */ -#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ -#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ -#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ -#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ -#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ -#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ -#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ -#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ -#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ -#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ -#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ -#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ -#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ -#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ -#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ -#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ - -/* CAN_TRS1 Masks */ -#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ -#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ -#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ -#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ -#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ -#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ -#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ -#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ -#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ -#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ -#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ -#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ -#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ -#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ -#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ -#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ - -/* CAN_TRS2 Masks */ -#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ -#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ -#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ -#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ -#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ -#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ -#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ -#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ -#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ -#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ -#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ -#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ -#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ -#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ -#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ -#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ - -/* CAN_AA1 Masks */ -#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ -#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ -#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ -#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ -#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ -#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ -#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ -#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ -#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ -#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ -#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ -#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ -#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ -#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ -#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ -#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ - -/* CAN_AA2 Masks */ -#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ -#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ -#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ -#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ -#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ -#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ -#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ -#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ -#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ -#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ -#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ -#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ -#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ -#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ -#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ -#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ - -/* CAN_TA1 Masks */ -#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ -#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ -#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ -#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ -#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ -#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ -#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ -#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ -#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ -#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ -#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ -#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ -#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ -#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ -#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ -#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ - -/* CAN_TA2 Masks */ -#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ -#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ -#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ -#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ -#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ -#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ -#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ -#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ -#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ -#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ -#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ -#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ -#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ -#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ -#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ -#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ - -/* CAN_MBTD Masks */ -#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ -#define TDA 0x0040 /* Temporary Disable Acknowledge */ -#define TDR 0x0080 /* Temporary Disable Request */ - -/* CAN_RFH1 Masks */ -#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ -#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ -#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ -#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ -#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ -#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ -#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ -#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ -#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ -#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ -#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ -#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ -#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ -#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ -#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ -#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ - -/* CAN_RFH2 Masks */ -#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ -#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ -#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ -#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ -#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ -#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ -#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ -#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ -#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ -#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ -#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ -#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ -#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ -#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ -#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ -#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ - -/* CAN_MBTIF1 Masks */ -#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ -#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ -#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ -#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ -#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ -#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ -#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ -#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ -#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ -#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ -#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ -#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ -#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ -#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ -#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ -#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ - -/* CAN_MBTIF2 Masks */ -#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ -#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ -#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ -#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ -#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ -#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ -#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ -#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ -#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ -#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ -#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ -#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ -#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ -#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ -#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ -#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ - -/* CAN_MBRIF1 Masks */ -#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ -#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ -#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ -#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ -#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ -#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ -#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ -#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ -#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ -#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ -#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ -#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ -#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ -#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ -#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ -#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ - -/* CAN_MBRIF2 Masks */ -#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ -#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ -#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ -#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ -#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ -#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ -#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ -#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ -#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ -#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ -#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ -#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ -#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ -#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ -#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ -#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ - -/* CAN_MBIM1 Masks */ -#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ -#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ -#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ -#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ -#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ -#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ -#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ -#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ -#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ -#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ -#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ -#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ -#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ -#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ -#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ -#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ - -/* CAN_MBIM2 Masks */ -#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ -#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ -#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ -#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ -#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ -#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ -#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ -#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ -#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ -#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ -#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ -#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ -#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ -#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ -#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ -#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ - -/* CAN_GIM Masks */ -#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ -#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ -#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ -#define BOIM 0x0008 /* Enable Bus Off Interrupt */ -#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ -#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ -#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ -#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ -#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ -#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ -#define ADIM 0x0400 /* Enable Access Denied Interrupt */ - -/* CAN_GIS Masks */ -#define EWTIS 0x0001 /* TX Error Count IRQ Status */ -#define EWRIS 0x0002 /* RX Error Count IRQ Status */ -#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ -#define BOIS 0x0008 /* Bus Off IRQ Status */ -#define WUIS 0x0010 /* Wake-Up IRQ Status */ -#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ -#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ -#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ -#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ -#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ -#define ADIS 0x0400 /* Access Denied IRQ Status */ - -/* CAN_GIF Masks */ -#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ -#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ -#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ -#define BOIF 0x0008 /* Bus Off IRQ Flag */ -#define WUIF 0x0010 /* Wake-Up IRQ Flag */ -#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ -#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ -#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ -#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ -#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ -#define ADIF 0x0400 /* Access Denied IRQ Flag */ - -/* CAN_UCCNF Masks */ -#define UCCNF 0x000F /* Universal Counter Mode */ -#define UC_STAMP 0x0001 /* Timestamp Mode */ -#define UC_WDOG 0x0002 /* Watchdog Mode */ -#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ -#define UC_ERROR 0x0006 /* CAN Error Frame Count */ -#define UC_OVER 0x0007 /* CAN Overload Frame Count */ -#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ -#define UC_AA 0x0009 /* TX Abort Count */ -#define UC_TA 0x000A /* TX Successful Count */ -#define UC_REJECT 0x000B /* RX Message Rejected Count */ -#define UC_RML 0x000C /* RX Message Lost Count */ -#define UC_RX 0x000D /* Total Successful RX Messages Count */ -#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ -#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ -#define UCRC 0x0020 /* Universal Counter Reload/Clear */ -#define UCCT 0x0040 /* Universal Counter CAN Trigger */ -#define UCE 0x0080 /* Universal Counter Enable */ - -/* CAN_ESR Masks */ -#define ACKE 0x0004 /* Acknowledge Error */ -#define SER 0x0008 /* Stuff Error */ -#define CRCE 0x0010 /* CRC Error */ -#define SA0 0x0020 /* Stuck At Dominant Error */ -#define BEF 0x0040 /* Bit Error Flag */ -#define FER 0x0080 /* Form Error Flag */ - -/* CAN_EWR Masks */ -#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ -#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ - #endif /* _DEF_BF539_H */ diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index f60c333fec66..dbb6b1d83f6d 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -498,6 +498,10 @@ static struct musb_hdrc_config musb_config = { .num_eps = 8, .dma_channels = 8, .gpio_vrsel = GPIO_PH6, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, }; static struct musb_hdrc_platform_data musb_plat = { diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 06919db00a74..6fcfb9187c35 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -603,6 +603,10 @@ static struct musb_hdrc_config musb_config = { .num_eps = 8, .dma_channels = 8, .gpio_vrsel = GPIO_PE7, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, }; static struct musb_hdrc_platform_data musb_plat = { diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index ab04d137fd8b..0ed06c2366fe 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -2104,677 +2104,6 @@ #define ECCCNT 0x3ff /* Transfer Count */ -/* Bit masks for CAN0_CONTROL */ - -#define SRS 0x1 /* Software Reset */ -#define DNM 0x2 /* DeviceNet Mode */ -#define ABO 0x4 /* Auto Bus On */ -#define WBA 0x10 /* Wakeup On CAN Bus Activity */ -#define SMR 0x20 /* Sleep Mode Request */ -#define CSR 0x40 /* CAN Suspend Mode Request */ -#define CCR 0x80 /* CAN Configuration Mode Request */ - -/* Bit masks for CAN0_STATUS */ - -#define WT 0x1 /* CAN Transmit Warning Flag */ -#define WR 0x2 /* CAN Receive Warning Flag */ -#define EP 0x4 /* CAN Error Passive Mode */ -#define EBO 0x8 /* CAN Error Bus Off Mode */ -#define CSA 0x40 /* CAN Suspend Mode Acknowledge */ -#define CCA 0x80 /* CAN Configuration Mode Acknowledge */ -#define MBPTR 0x1f00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode Status */ -#define REC 0x8000 /* Receive Mode Status */ - -/* Bit masks for CAN0_DEBUG */ - -#define DEC 0x1 /* Disable Transmit/Receive Error Counters */ -#define DRI 0x2 /* Disable CANRX Input Pin */ -#define DTO 0x4 /* Disable CANTX Output Pin */ -#define DIL 0x8 /* Disable Internal Loop */ -#define MAA 0x10 /* Mode Auto-Acknowledge */ -#define MRB 0x20 /* Mode Read Back */ -#define CDE 0x8000 /* CAN Debug Mode Enable */ - -/* Bit masks for CAN0_CLOCK */ - -#define BRP 0x3ff /* CAN Bit Rate Prescaler */ - -/* Bit masks for CAN0_TIMING */ - -#define SJW 0x300 /* Synchronization Jump Width */ -#define SAM 0x80 /* Sampling */ -#define TSEG2 0x70 /* Time Segment 2 */ -#define TSEG1 0xf /* Time Segment 1 */ - -/* Bit masks for CAN0_INTR */ - -#define CANRX 0x80 /* Serial Input From Transceiver */ -#define CANTX 0x40 /* Serial Output To Transceiver */ -#define SMACK 0x8 /* Sleep Mode Acknowledge */ -#define GIRQ 0x4 /* Global Interrupt Request Status */ -#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ -#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ - -/* Bit masks for CAN0_GIM */ - -#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ -#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ -#define EPIM 0x4 /* Error Passive Interrupt Mask */ -#define BOIM 0x8 /* Bus Off Interrupt Mask */ -#define WUIM 0x10 /* Wakeup Interrupt Mask */ -#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ -#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ -#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ -#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ -#define ADIM 0x400 /* Access Denied Interrupt Mask */ - -/* Bit masks for CAN0_GIS */ - -#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ -#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ -#define EPIS 0x4 /* Error Passive Interrupt Status */ -#define BOIS 0x8 /* Bus Off Interrupt Status */ -#define WUIS 0x10 /* Wakeup Interrupt Status */ -#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ -#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ -#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ -#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ -#define ADIS 0x400 /* Access Denied Interrupt Status */ - -/* Bit masks for CAN0_GIF */ - -#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ -#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ -#define EPIF 0x4 /* Error Passive Interrupt Flag */ -#define BOIF 0x8 /* Bus Off Interrupt Flag */ -#define WUIF 0x10 /* Wakeup Interrupt Flag */ -#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ -#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ -#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ -#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ -#define ADIF 0x400 /* Access Denied Interrupt Flag */ - -/* Bit masks for CAN0_MBTD */ - -#define TDR 0x80 /* Temporary Disable Request */ -#define TDA 0x40 /* Temporary Disable Acknowledge */ -#define TDPTR 0x1f /* Temporary Disable Pointer */ - -/* Bit masks for CAN0_UCCNF */ - -#define UCCNF 0xf /* Universal Counter Configuration */ -#define UCRC 0x20 /* Universal Counter Reload/Clear */ -#define UCCT 0x40 /* Universal Counter CAN Trigger */ -#define UCE 0x80 /* Universal Counter Enable */ - -/* Bit masks for CAN0_CEC */ - -#define RXECNT 0xff /* Receive Error Counter */ -#define TXECNT 0xff00 /* Transmit Error Counter */ - -/* Bit masks for CAN0_ESR */ - -#define FER 0x80 /* Form Error */ -#define BEF 0x40 /* Bit Error Flag */ -#define SA0 0x20 /* Stuck At Dominant */ -#define CRCE 0x10 /* CRC Error */ -#define SER 0x8 /* Stuff Bit Error */ -#define ACKE 0x4 /* Acknowledge Error */ - -/* Bit masks for CAN0_EWR */ - -#define EWLTEC 0xff00 /* Transmit Error Warning Limit */ -#define EWLREC 0xff /* Receive Error Warning Limit */ - -/* Bit masks for CAN0_AMxx_H */ - -#define FDF 0x8000 /* Filter On Data Field */ -#define FMD 0x4000 /* Full Mask Data */ -#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ -#define BASEID 0x1ffc /* Base Identifier */ -#define EXTID_HI 0x3 /* Extended Identifier High Bits */ - -/* Bit masks for CAN0_AMxx_L */ - -#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ -#define DFM 0xffff /* Data Field Mask */ - -/* Bit masks for CAN0_MBxx_ID1 */ - -#define AME 0x8000 /* Acceptance Mask Enable */ -#define RTR 0x4000 /* Remote Transmission Request */ -#define IDE 0x2000 /* Identifier Extension */ -#define BASEID 0x1ffc /* Base Identifier */ -#define EXTID_HI 0x3 /* Extended Identifier High Bits */ - -/* Bit masks for CAN0_MBxx_ID0 */ - -#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ -#define DFM 0xffff /* Data Field Mask */ - -/* Bit masks for CAN0_MBxx_TIMESTAMP */ - -#define TSV 0xffff /* Time Stamp Value */ - -/* Bit masks for CAN0_MBxx_LENGTH */ - -#define DLC 0xf /* Data Length Code */ - -/* Bit masks for CAN0_MBxx_DATA3 */ - -#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ -#define CAN_BYTE1 0xff /* Data Field Byte 1 */ - -/* Bit masks for CAN0_MBxx_DATA2 */ - -#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ -#define CAN_BYTE3 0xff /* Data Field Byte 3 */ - -/* Bit masks for CAN0_MBxx_DATA1 */ - -#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ -#define CAN_BYTE5 0xff /* Data Field Byte 5 */ - -/* Bit masks for CAN0_MBxx_DATA0 */ - -#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ -#define CAN_BYTE7 0xff /* Data Field Byte 7 */ - -/* Bit masks for CAN0_MC1 */ - -#define MC0 0x1 /* Mailbox 0 Enable */ -#define MC1 0x2 /* Mailbox 1 Enable */ -#define MC2 0x4 /* Mailbox 2 Enable */ -#define MC3 0x8 /* Mailbox 3 Enable */ -#define MC4 0x10 /* Mailbox 4 Enable */ -#define MC5 0x20 /* Mailbox 5 Enable */ -#define MC6 0x40 /* Mailbox 6 Enable */ -#define MC7 0x80 /* Mailbox 7 Enable */ -#define MC8 0x100 /* Mailbox 8 Enable */ -#define MC9 0x200 /* Mailbox 9 Enable */ -#define MC10 0x400 /* Mailbox 10 Enable */ -#define MC11 0x800 /* Mailbox 11 Enable */ -#define MC12 0x1000 /* Mailbox 12 Enable */ -#define MC13 0x2000 /* Mailbox 13 Enable */ -#define MC14 0x4000 /* Mailbox 14 Enable */ -#define MC15 0x8000 /* Mailbox 15 Enable */ - -/* Bit masks for CAN0_MC2 */ - -#define MC16 0x1 /* Mailbox 16 Enable */ -#define MC17 0x2 /* Mailbox 17 Enable */ -#define MC18 0x4 /* Mailbox 18 Enable */ -#define MC19 0x8 /* Mailbox 19 Enable */ -#define MC20 0x10 /* Mailbox 20 Enable */ -#define MC21 0x20 /* Mailbox 21 Enable */ -#define MC22 0x40 /* Mailbox 22 Enable */ -#define MC23 0x80 /* Mailbox 23 Enable */ -#define MC24 0x100 /* Mailbox 24 Enable */ -#define MC25 0x200 /* Mailbox 25 Enable */ -#define MC26 0x400 /* Mailbox 26 Enable */ -#define MC27 0x800 /* Mailbox 27 Enable */ -#define MC28 0x1000 /* Mailbox 28 Enable */ -#define MC29 0x2000 /* Mailbox 29 Enable */ -#define MC30 0x4000 /* Mailbox 30 Enable */ -#define MC31 0x8000 /* Mailbox 31 Enable */ - -/* Bit masks for CAN0_MD1 */ - -#define MD0 0x1 /* Mailbox 0 Receive Enable */ -#define MD1 0x2 /* Mailbox 1 Receive Enable */ -#define MD2 0x4 /* Mailbox 2 Receive Enable */ -#define MD3 0x8 /* Mailbox 3 Receive Enable */ -#define MD4 0x10 /* Mailbox 4 Receive Enable */ -#define MD5 0x20 /* Mailbox 5 Receive Enable */ -#define MD6 0x40 /* Mailbox 6 Receive Enable */ -#define MD7 0x80 /* Mailbox 7 Receive Enable */ -#define MD8 0x100 /* Mailbox 8 Receive Enable */ -#define MD9 0x200 /* Mailbox 9 Receive Enable */ -#define MD10 0x400 /* Mailbox 10 Receive Enable */ -#define MD11 0x800 /* Mailbox 11 Receive Enable */ -#define MD12 0x1000 /* Mailbox 12 Receive Enable */ -#define MD13 0x2000 /* Mailbox 13 Receive Enable */ -#define MD14 0x4000 /* Mailbox 14 Receive Enable */ -#define MD15 0x8000 /* Mailbox 15 Receive Enable */ - -/* Bit masks for CAN0_MD2 */ - -#define MD16 0x1 /* Mailbox 16 Receive Enable */ -#define MD17 0x2 /* Mailbox 17 Receive Enable */ -#define MD18 0x4 /* Mailbox 18 Receive Enable */ -#define MD19 0x8 /* Mailbox 19 Receive Enable */ -#define MD20 0x10 /* Mailbox 20 Receive Enable */ -#define MD21 0x20 /* Mailbox 21 Receive Enable */ -#define MD22 0x40 /* Mailbox 22 Receive Enable */ -#define MD23 0x80 /* Mailbox 23 Receive Enable */ -#define MD24 0x100 /* Mailbox 24 Receive Enable */ -#define MD25 0x200 /* Mailbox 25 Receive Enable */ -#define MD26 0x400 /* Mailbox 26 Receive Enable */ -#define MD27 0x800 /* Mailbox 27 Receive Enable */ -#define MD28 0x1000 /* Mailbox 28 Receive Enable */ -#define MD29 0x2000 /* Mailbox 29 Receive Enable */ -#define MD30 0x4000 /* Mailbox 30 Receive Enable */ -#define MD31 0x8000 /* Mailbox 31 Receive Enable */ - -/* Bit masks for CAN0_RMP1 */ - -#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ -#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ -#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ -#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ -#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ -#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ -#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ -#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ -#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ -#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ -#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ -#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ -#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ -#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ -#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ -#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ - -/* Bit masks for CAN0_RMP2 */ - -#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ -#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ -#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ -#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ -#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ -#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ -#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ -#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ -#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ -#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ -#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ -#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ -#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ -#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ -#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ -#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ - -/* Bit masks for CAN0_RML1 */ - -#define RML0 0x1 /* Mailbox 0 Receive Message Lost */ -#define RML1 0x2 /* Mailbox 1 Receive Message Lost */ -#define RML2 0x4 /* Mailbox 2 Receive Message Lost */ -#define RML3 0x8 /* Mailbox 3 Receive Message Lost */ -#define RML4 0x10 /* Mailbox 4 Receive Message Lost */ -#define RML5 0x20 /* Mailbox 5 Receive Message Lost */ -#define RML6 0x40 /* Mailbox 6 Receive Message Lost */ -#define RML7 0x80 /* Mailbox 7 Receive Message Lost */ -#define RML8 0x100 /* Mailbox 8 Receive Message Lost */ -#define RML9 0x200 /* Mailbox 9 Receive Message Lost */ -#define RML10 0x400 /* Mailbox 10 Receive Message Lost */ -#define RML11 0x800 /* Mailbox 11 Receive Message Lost */ -#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ -#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ -#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ -#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ - -/* Bit masks for CAN0_RML2 */ - -#define RML16 0x1 /* Mailbox 16 Receive Message Lost */ -#define RML17 0x2 /* Mailbox 17 Receive Message Lost */ -#define RML18 0x4 /* Mailbox 18 Receive Message Lost */ -#define RML19 0x8 /* Mailbox 19 Receive Message Lost */ -#define RML20 0x10 /* Mailbox 20 Receive Message Lost */ -#define RML21 0x20 /* Mailbox 21 Receive Message Lost */ -#define RML22 0x40 /* Mailbox 22 Receive Message Lost */ -#define RML23 0x80 /* Mailbox 23 Receive Message Lost */ -#define RML24 0x100 /* Mailbox 24 Receive Message Lost */ -#define RML25 0x200 /* Mailbox 25 Receive Message Lost */ -#define RML26 0x400 /* Mailbox 26 Receive Message Lost */ -#define RML27 0x800 /* Mailbox 27 Receive Message Lost */ -#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ -#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ -#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ -#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ - -/* Bit masks for CAN0_OPSS1 */ - -#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ - -/* Bit masks for CAN0_OPSS2 */ - -#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ - -/* Bit masks for CAN0_TRS1 */ - -#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ -#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ -#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ -#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ -#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ -#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ -#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ -#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ -#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ -#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ -#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ -#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ -#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ -#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ -#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ -#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ - -/* Bit masks for CAN0_TRS2 */ - -#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ -#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ -#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ -#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ -#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ -#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ -#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ -#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ -#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ -#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ -#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ -#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ -#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ -#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ -#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ -#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ - -/* Bit masks for CAN0_TRR1 */ - -#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ -#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ -#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ -#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ -#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ -#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ -#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ -#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ -#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ -#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ -#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ -#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ -#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ -#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ -#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ -#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ - -/* Bit masks for CAN0_TRR2 */ - -#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ -#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ -#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ -#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ -#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ -#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ -#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ -#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ -#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ -#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ -#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ -#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ -#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ -#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ -#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ -#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ - -/* Bit masks for CAN0_AA1 */ - -#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ -#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ -#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ -#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ -#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ -#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ -#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ -#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ -#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ -#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ -#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ -#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ -#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ -#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ -#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ -#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ - -/* Bit masks for CAN0_AA2 */ - -#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ -#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ -#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ -#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ -#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ -#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ -#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ -#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ -#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ -#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ -#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ -#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ -#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ -#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ -#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ -#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ - -/* Bit masks for CAN0_TA1 */ - -#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ -#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ -#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ -#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ -#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ -#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ -#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ -#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ -#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ -#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ -#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ -#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ -#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ -#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ -#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ -#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ - -/* Bit masks for CAN0_TA2 */ - -#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ -#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ -#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ -#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ -#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ -#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ -#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ -#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ -#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ -#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ -#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ -#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ -#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ -#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ -#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ -#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ - -/* Bit masks for CAN0_RFH1 */ - -#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ -#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ -#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ -#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ -#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ -#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ -#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ -#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ -#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ -#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ -#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ -#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ -#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ -#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ -#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ -#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ - -/* Bit masks for CAN0_RFH2 */ - -#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ -#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ -#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ -#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ -#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ -#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ -#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ -#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ -#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ -#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ -#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ -#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ -#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ -#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ -#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ -#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ - -/* Bit masks for CAN0_MBIM1 */ - -#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ -#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ -#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ -#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ -#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ -#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ -#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ -#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ -#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ -#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ -#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ -#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ -#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ -#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ -#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ -#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ - -/* Bit masks for CAN0_MBIM2 */ - -#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ -#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ -#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ -#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ -#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ -#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ -#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ -#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ -#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ -#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ -#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ -#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ -#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ -#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ -#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ -#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ - -/* Bit masks for CAN0_MBTIF1 */ - -#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ -#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ -#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ -#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ -#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ -#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ -#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ -#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ -#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ -#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ -#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ -#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ -#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ -#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ -#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ -#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ - -/* Bit masks for CAN0_MBTIF2 */ - -#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ -#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ -#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ -#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ -#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ -#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ -#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ -#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ -#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ -#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ -#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ -#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ -#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ -#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ -#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ -#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ - -/* Bit masks for CAN0_MBRIF1 */ - -#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ -#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ -#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ -#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ -#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ -#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ -#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ -#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ -#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ -#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ -#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ -#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ -#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ -#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ -#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ -#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ - -/* Bit masks for CAN0_MBRIF2 */ - -#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ -#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ -#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ -#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ -#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ -#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ -#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ -#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ -#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ -#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ -#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ -#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ -#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ -#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ -#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ -#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ - /* Bit masks for EPPIx_STATUS */ #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 5163e2c383c5..bfcfa86db2b5 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -44,6 +44,7 @@ #include <linux/spi/flash.h> #include <linux/irq.h> #include <linux/interrupt.h> +#include <linux/jiffies.h> #include <linux/i2c-pca-platform.h> #include <linux/delay.h> #include <linux/io.h> @@ -112,7 +113,7 @@ static struct resource bfin_i2c_pca_resources[] = { struct i2c_pca9564_pf_platform_data pca9564_platform_data = { .gpio = -1, .i2c_clock_speed = 330000, - .timeout = 10000 + .timeout = HZ, }; /* PCA9564 I2C Bus driver */ diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 7ad8878bfa18..1c8c4c7245c3 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -92,26 +92,29 @@ static void __init search_IAR(void) { unsigned ivg, irq_pos = 0; for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { - int irqn; + int irqN; ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; - for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { - int iar_shift = (irqn & 7) * 4; - if (ivg == (0xf & -#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \ - || defined(CONFIG_BF539) || defined(CONFIG_BF51x) - bfin_read32((unsigned long *)SIC_IAR0 + - ((irqn % 32) >> 3) + ((irqn / 32) * - ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) { + for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { + int irqn; + u32 iar = bfin_read32((unsigned long *)SIC_IAR0 + +#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ + defined(CONFIG_BF538) || defined(CONFIG_BF539) + ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) #else - bfin_read32((unsigned long *)SIC_IAR0 + - (irqn >> 3)) >> iar_shift)) { + (irqN >> 3) #endif - ivg_table[irq_pos].irqno = IVG7 + irqn; - ivg_table[irq_pos].isrflag = 1 << (irqn % 32); - ivg7_13[ivg].istop++; - irq_pos++; + ); + + for (irqn = irqN; irqn < irqN + 4; ++irqn) { + int iar_shift = (irqn & 7) * 4; + if (ivg == (0xf & (iar >> iar_shift))) { + ivg_table[irq_pos].irqno = IVG7 + irqn; + ivg_table[irq_pos].isrflag = 1 << (irqn % 32); + ivg7_13[ivg].istop++; + irq_pos++; + } } } } @@ -662,14 +665,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) #ifdef CONFIG_PM int bfin_gpio_set_wake(unsigned int irq, unsigned int state) { - unsigned gpio = irq_to_gpio(irq); - - if (state) - gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE); - else - gpio_pm_wakeup_free(gpio); - - return 0; + return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state); } #endif diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index c1f1ccc846f0..ea7f95f6bb4c 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -20,35 +20,11 @@ #include <asm/dma.h> #include <asm/dpmc.h> -#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H -#define WAKEUP_TYPE PM_WAKE_HIGH -#endif - -#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L -#define WAKEUP_TYPE PM_WAKE_LOW -#endif - -#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F -#define WAKEUP_TYPE PM_WAKE_FALLING -#endif - -#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R -#define WAKEUP_TYPE PM_WAKE_RISING -#endif - -#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B -#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES -#endif - void bfin_pm_suspend_standby_enter(void) { unsigned long flags; -#ifdef CONFIG_PM_WAKEUP_BY_GPIO - gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); -#endif - local_irq_save_hw(flags); bfin_pm_standby_setup(); diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 7cecbaf0358a..a17107a700d5 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -170,8 +170,8 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance) kfree(msg); break; default: - printk(KERN_CRIT "CPU%u: Unknown IPI message \ - 0x%lx\n", cpu, msg->type); + printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n", + cpu, msg->type); kfree(msg); break; } diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 355b87aa6b93..bb4e8fff4b55 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -15,23 +15,11 @@ #include "blackfin_sram.h" /* - * BAD_PAGE is the page that is used for page faults when linux - * is out-of-memory. Older versions of linux just did a - * do_exit(), but using this instead means there is less risk - * for a process dying in kernel mode, possibly leaving a inode - * unused etc.. - * - * BAD_PAGETABLE is the accompanying page-table: it is initialized - * to point to BAD_PAGE entries. - * - * ZERO_PAGE is a special page that is used for zero-initialized - * data and COW. + * ZERO_PAGE is a special page that is used for zero-initialized data and COW. + * Let the bss do its zero-init magic so we don't have to do it ourselves. */ -static unsigned long empty_bad_page_table; - -static unsigned long empty_bad_page; - -static unsigned long empty_zero_page; +char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); +EXPORT_SYMBOL(empty_zero_page); #ifndef CONFIG_EXCEPTION_L1_SCRATCH #if defined CONFIG_SYSCALL_TAB_L1 @@ -52,40 +40,26 @@ EXPORT_SYMBOL(cpu_pda); void __init paging_init(void) { /* - * make sure start_mem is page aligned, otherwise bootmem and - * page_alloc get different views og the world + * make sure start_mem is page aligned, otherwise bootmem and + * page_alloc get different views of the world */ unsigned long end_mem = memory_end & PAGE_MASK; - pr_debug("start_mem is %#lx virtual_end is %#lx\n", PAGE_ALIGN(memory_start), end_mem); - - /* - * initialize the bad page table and bad page to point - * to a couple of allocated pages - */ - empty_bad_page_table = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); - empty_bad_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); - empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); - memset((void *)empty_zero_page, 0, PAGE_SIZE); + unsigned long zones_size[MAX_NR_ZONES] = { + [0] = 0, + [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT, + [ZONE_NORMAL] = 0, +#ifdef CONFIG_HIGHMEM + [ZONE_HIGHMEM] = 0, +#endif + }; - /* - * Set up SFC/DFC registers (user data space) - */ + /* Set up SFC/DFC registers (user data space) */ set_fs(KERNEL_DS); - pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", + pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", PAGE_ALIGN(memory_start), end_mem); - - { - unsigned long zones_size[MAX_NR_ZONES] = { 0, }; - - zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT; - zones_size[ZONE_NORMAL] = 0; -#ifdef CONFIG_HIGHMEM - zones_size[ZONE_HIGHMEM] = 0; -#endif - free_area_init(zones_size); - } + free_area_init(zones_size); } asmlinkage void __init init_pda(void) diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c index 39b058564f62..7e2e674ed444 100644 --- a/arch/blackfin/mm/isram-driver.c +++ b/arch/blackfin/mm/isram-driver.c @@ -43,13 +43,12 @@ static DEFINE_SPINLOCK(dtest_lock); /* Takes a void pointer */ #define IADDR2DTEST(x) \ ({ unsigned long __addr = (unsigned long)(x); \ - (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \ - (__addr & 0x8000) << 23 | /* Bank A/B */ \ - (__addr & 0x0800) << 15 | /* address bit 11 */ \ - (__addr & 0x3000) << 4 | /* address bits 13:12 */ \ - (__addr & 0x8000) << 8 | /* address bit 15 */ \ - (0x1000000) | /* instruction access = 1 */ \ - (0x4); /* data array = 1 */ \ + ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \ + (1 << 24) | /* instruction access = 1 */ \ + ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \ + ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \ + (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \ + (1 << 2); /* data array = 1 */ \ }) /* Takes a pointer, and returns the offset (in bits) which things should be shifted */ @@ -196,7 +195,7 @@ EXPORT_SYMBOL(isram_memcpy); #ifdef CONFIG_BFIN_ISRAM_SELF_TEST -#define TEST_LEN 0x100 +static int test_len = 0x20000; static __init void hex_dump(unsigned char *buf, int len) { @@ -212,15 +211,15 @@ static __init int isram_read_test(char *sdram, void *l1inst) pr_info("INFO: running isram_read tests\n"); /* setup some different data to play with */ - for (i = 0; i < TEST_LEN; ++i) - sdram[i] = i; - dma_memcpy(l1inst, sdram, TEST_LEN); + for (i = 0; i < test_len; ++i) + sdram[i] = i % 255; + dma_memcpy(l1inst, sdram, test_len); /* make sure we can read the L1 inst */ - for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { + for (i = 0; i < test_len; i += sizeof(uint64_t)) { data1 = isram_read(l1inst + i); memcpy(&data2, sdram + i, sizeof(data2)); - if (memcmp(&data1, &data2, sizeof(uint64_t))) { + if (data1 != data2) { pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n", l1inst + i, data1, data2); ++ret; @@ -238,25 +237,25 @@ static __init int isram_write_test(char *sdram, void *l1inst) pr_info("INFO: running isram_write tests\n"); /* setup some different data to play with */ - memset(sdram, 0, TEST_LEN * 2); - dma_memcpy(l1inst, sdram, TEST_LEN); - for (i = 0; i < TEST_LEN; ++i) - sdram[i] = i; + memset(sdram, 0, test_len * 2); + dma_memcpy(l1inst, sdram, test_len); + for (i = 0; i < test_len; ++i) + sdram[i] = i % 255; /* make sure we can write the L1 inst */ - for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { + for (i = 0; i < test_len; i += sizeof(uint64_t)) { memcpy(&data1, sdram + i, sizeof(data1)); isram_write(l1inst + i, data1); data2 = isram_read(l1inst + i); - if (memcmp(&data1, &data2, sizeof(uint64_t))) { + if (data1 != data2) { pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n", l1inst + i, data1, data2); ++ret; } } - dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN); - if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { + dma_memcpy(sdram + test_len, l1inst, test_len); + if (memcmp(sdram, sdram + test_len, test_len)) { pr_err("FAIL: isram_write() did not work properly\n"); ++ret; } @@ -268,12 +267,12 @@ static __init int _isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy, void *(*fmemcpy)(void *, const void *, size_t)) { - memset(sdram, pattern, TEST_LEN); - fmemcpy(l1inst, sdram, TEST_LEN); - fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN); - if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { + memset(sdram, pattern, test_len); + fmemcpy(l1inst, sdram, test_len); + fmemcpy(sdram + test_len, l1inst, test_len); + if (memcmp(sdram, sdram + test_len, test_len)) { pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n", - smemcpy, l1inst, sdram, TEST_LEN, pattern); + smemcpy, l1inst, sdram, test_len, pattern); return 1; } return 0; @@ -292,12 +291,13 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst) /* check read of small, unaligned, and hardware 64bit limits */ pr_info("INFO: running isram_memcpy (read) tests\n"); - for (i = 0; i < TEST_LEN; ++i) - sdram[i] = i; - dma_memcpy(l1inst, sdram, TEST_LEN); + /* setup some different data to play with */ + for (i = 0; i < test_len; ++i) + sdram[i] = i % 255; + dma_memcpy(l1inst, sdram, test_len); thisret = 0; - for (i = 0; i < TEST_LEN - 32; ++i) { + for (i = 0; i < test_len - 32; ++i) { unsigned char cmp[32]; for (j = 1; j <= 32; ++j) { memset(cmp, 0, sizeof(cmp)); @@ -310,7 +310,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst) pr_cont("\n"); if (++thisret > 20) { pr_err("FAIL: skipping remaining series\n"); - i = TEST_LEN; + i = test_len; break; } } @@ -321,11 +321,11 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst) /* check write of small, unaligned, and hardware 64bit limits */ pr_info("INFO: running isram_memcpy (write) tests\n"); - memset(sdram + TEST_LEN, 0, TEST_LEN); - dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN); + memset(sdram + test_len, 0, test_len); + dma_memcpy(l1inst, sdram + test_len, test_len); thisret = 0; - for (i = 0; i < TEST_LEN - 32; ++i) { + for (i = 0; i < test_len - 32; ++i) { unsigned char cmp[32]; for (j = 1; j <= 32; ++j) { isram_memcpy(l1inst + i, sdram + i, j); @@ -338,7 +338,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst) pr_cont("\n"); if (++thisret > 20) { pr_err("FAIL: skipping remaining series\n"); - i = TEST_LEN; + i = test_len; break; } } @@ -355,22 +355,30 @@ static __init int isram_test_init(void) char *sdram; void *l1inst; - sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL); - if (!sdram) { - pr_warning("SKIP: could not allocate sdram\n"); - return 0; + /* Try to test as much of L1SRAM as possible */ + while (test_len) { + test_len >>= 1; + l1inst = l1_inst_sram_alloc(test_len); + if (l1inst) + break; } - - l1inst = l1_inst_sram_alloc(TEST_LEN); if (!l1inst) { - kfree(sdram); pr_warning("SKIP: could not allocate L1 inst\n"); return 0; } + pr_info("INFO: testing %#x bytes (%p - %p)\n", + test_len, l1inst, l1inst + test_len); + + sdram = kmalloc(test_len * 2, GFP_KERNEL); + if (!sdram) { + sram_free(l1inst); + pr_warning("SKIP: could not allocate sdram\n"); + return 0; + } /* sanity check initial L1 inst state */ ret = 1; - pr_info("INFO: running initial dma_memcpy checks\n"); + pr_info("INFO: running initial dma_memcpy checks %p\n", sdram); if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy)) goto abort; if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy)) diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index 49b2ff2c8b74..627e04b5ba9a 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c @@ -256,7 +256,8 @@ static void *_sram_alloc(size_t size, struct sram_piece *pfree_head, plast->next = pslot->next; pavail = pslot; } else { - pavail = kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); + /* use atomic so our L1 allocator can be used atomically */ + pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC); if (!pavail) return NULL; diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c index 77630df94343..884275629ef7 100644 --- a/arch/cris/arch-v10/drivers/ds1302.c +++ b/arch/cris/arch-v10/drivers/ds1302.c @@ -19,6 +19,7 @@ #include <linux/module.h> #include <linux/miscdevice.h> #include <linux/delay.h> +#include <linux/smp_lock.h> #include <linux/bcd.h> #include <linux/capability.h> @@ -238,9 +239,7 @@ static unsigned char days_in_mo[] = /* ioctl that supports RTC_RD_TIME and RTC_SET_TIME (read and set time/date). */ -static int -rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static int rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { unsigned long flags; @@ -354,6 +353,17 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, } } +static long rtc_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret; + + lock_kernel(); + ret = rtc_ioctl(file, cmd, arg); + unlock_kernel(); + + return ret; +} + static void print_rtc_status(void) { @@ -375,8 +385,8 @@ print_rtc_status(void) /* The various file operations we support. */ static const struct file_operations rtc_fops = { - .owner = THIS_MODULE, - .ioctl = rtc_ioctl, + .owner = THIS_MODULE, + .unlocked_ioctl = rtc_unlocked_ioctl, }; /* Probe for the chip by writing something to its RAM and try reading it back. */ diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c index 1f2ae909d3e6..c3405507a3d1 100644 --- a/arch/cris/arch-v10/drivers/eeprom.c +++ b/arch/cris/arch-v10/drivers/eeprom.c @@ -73,8 +73,7 @@ struct eeprom_type int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */ /* this one is to keep the read/write operations atomic */ - wait_queue_head_t wait_q; - volatile int busy; + struct mutex lock; int retry_cnt_addr; /* Used to keep track of number of retries for adaptive timing adjustments */ int retry_cnt_read; @@ -115,8 +114,7 @@ const struct file_operations eeprom_fops = int __init eeprom_init(void) { - init_waitqueue_head(&eeprom.wait_q); - eeprom.busy = 0; + mutex_init(&eeprom.lock); #ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE #define EETEXT "Found" @@ -439,10 +437,7 @@ static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig) static int eeprom_read_buf(loff_t addr, char * buf, int count) { - struct file f; - - f.f_pos = addr; - return eeprom_read(&f, buf, count, &addr); + return eeprom_read(NULL, buf, count, &addr); } @@ -452,7 +447,7 @@ static int eeprom_read_buf(loff_t addr, char * buf, int count) static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off) { int read=0; - unsigned long p = file->f_pos; + unsigned long p = *off; unsigned char page; @@ -461,12 +456,9 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t return -EFAULT; } - wait_event_interruptible(eeprom.wait_q, !eeprom.busy); - if (signal_pending(current)) + if (mutex_lock_interruptible(&eeprom.lock)) return -EINTR; - eeprom.busy++; - page = (unsigned char) (p >> 8); if(!eeprom_address(p)) @@ -476,8 +468,7 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t i2c_stop(); /* don't forget to wake them up */ - eeprom.busy--; - wake_up_interruptible(&eeprom.wait_q); + mutex_unlock(&eeprom.lock); return -EFAULT; } @@ -501,11 +492,10 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t if(read > 0) { - file->f_pos += read; + *off += read; } - eeprom.busy--; - wake_up_interruptible(&eeprom.wait_q); + mutex_unlock(&eeprom.lock); return read; } @@ -513,11 +503,7 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t static int eeprom_write_buf(loff_t addr, const char * buf, int count) { - struct file f; - - f.f_pos = addr; - - return eeprom_write(&f, buf, count, &addr); + return eeprom_write(NULL, buf, count, &addr); } @@ -534,16 +520,14 @@ static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, return -EFAULT; } - wait_event_interruptible(eeprom.wait_q, !eeprom.busy); /* bail out if we get interrupted */ - if (signal_pending(current)) + if (mutex_lock_interruptible(&eeprom.lock)) return -EINTR; - eeprom.busy++; for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++) { restart = 0; written = 0; - p = file->f_pos; + p = *off; while( (written < count) && (p < eeprom.size)) @@ -556,8 +540,7 @@ static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, i2c_stop(); /* don't forget to wake them up */ - eeprom.busy--; - wake_up_interruptible(&eeprom.wait_q); + mutex_unlock(&eeprom.lock); return -EFAULT; } #ifdef EEPROM_ADAPTIVE_TIMING @@ -669,12 +652,11 @@ static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, } /* while */ } /* for */ - eeprom.busy--; - wake_up_interruptible(&eeprom.wait_q); - if (written == 0 && file->f_pos >= eeprom.size){ + mutex_unlock(&eeprom.lock); + if (written == 0 && p >= eeprom.size){ return -ENOSPC; } - file->f_pos += written; + *off = p; return written; } diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index 1e90c1a9c849..7dcb1f85f42b 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c @@ -27,6 +27,7 @@ #include <linux/delay.h> #include <linux/bcd.h> #include <linux/mutex.h> +#include <linux/smp_lock.h> #include <asm/uaccess.h> #include <asm/system.h> @@ -53,7 +54,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */ static const unsigned char days_in_month[] = { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; -int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long); +static long pcf8563_unlocked_ioctl(struct file *, unsigned int, unsigned long); /* Cache VL bit value read at driver init since writing the RTC_SECOND * register clears the VL status. @@ -62,7 +63,7 @@ static int voltage_low; static const struct file_operations pcf8563_fops = { .owner = THIS_MODULE, - .ioctl = pcf8563_ioctl, + .unlocked_ioctl = pcf8563_unlocked_ioctl, }; unsigned char @@ -212,8 +213,7 @@ pcf8563_exit(void) * ioctl calls for this driver. Why return -ENOTTY upon error? Because * POSIX says so! */ -int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) +static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { /* Some sanity checks. */ if (_IOC_TYPE(cmd) != RTC_MAGIC) @@ -339,6 +339,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } +static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int ret; + + lock_kernel(); + return pcf8563_ioctl(filp, cmd, arg); + unlock_kernel(); + + return ret; +} + static int __init pcf8563_register(void) { if (pcf8563_init() < 0) { diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c index 1a61efc13982..a0c0df8be9c8 100644 --- a/arch/cris/arch-v10/kernel/irq.c +++ b/arch/cris/arch-v10/kernel/irq.c @@ -17,8 +17,8 @@ #include <linux/kernel.h> #include <linux/init.h> -#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); -#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); +#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); +#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is * global just so that the kernel gdb can use it. @@ -116,12 +116,12 @@ static unsigned int startup_crisv10_irq(unsigned int irq) static void enable_crisv10_irq(unsigned int irq) { - unmask_irq(irq); + crisv10_unmask_irq(irq); } static void disable_crisv10_irq(unsigned int irq) { - mask_irq(irq); + crisv10_mask_irq(irq); } static void ack_crisv10_irq(unsigned int irq) diff --git a/arch/cris/arch-v10/lib/dmacopy.c b/arch/cris/arch-v10/lib/dmacopy.c index e5fb44f505c5..49f5b8ca5b47 100644 --- a/arch/cris/arch-v10/lib/dmacopy.c +++ b/arch/cris/arch-v10/lib/dmacopy.c @@ -1,5 +1,4 @@ -/* $Id: dmacopy.c,v 1.1 2001/12/17 13:59:27 bjornw Exp $ - * +/* * memcpy for large blocks, using memory-memory DMA channels 6 and 7 in Etrax */ @@ -13,11 +12,11 @@ void *dma_memcpy(void *pdst, unsigned int pn) { static etrax_dma_descr indma, outdma; - - D(printk("dma_memcpy %d bytes... ", pn)); + + D(printk(KERN_DEBUG "dma_memcpy %d bytes... ", pn)); #if 0 - *R_GEN_CONFIG = genconfig_shadow = + *R_GEN_CONFIG = genconfig_shadow = (genconfig_shadow & ~0x3c0000) | IO_STATE(R_GEN_CONFIG, dma6, intdma7) | IO_STATE(R_GEN_CONFIG, dma7, intdma6); @@ -32,11 +31,11 @@ void *dma_memcpy(void *pdst, *R_DMA_CH7_FIRST = &outdma; *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start); *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start); - - while(*R_DMA_CH7_CMD == 1) /* wait for completion */ ; - D(printk("done\n")); + while (*R_DMA_CH7_CMD == 1) + /* wait for completion */; + D(printk(KERN_DEBUG "done\n")); } diff --git a/arch/cris/arch-v10/lib/hw_settings.S b/arch/cris/arch-v10/lib/hw_settings.S index 56905aaa7b6e..c09f19f478a5 100644 --- a/arch/cris/arch-v10/lib/hw_settings.S +++ b/arch/cris/arch-v10/lib/hw_settings.S @@ -1,13 +1,11 @@ /* - * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $ - * * This table is used by some tools to extract hardware parameters. * The table should be included in the kernel and the decompressor. * Don't forget to update the tools if you change this table. * * Copyright (C) 2001 Axis Communications AB * - * Authors: Mikael Starvik (starvik@axis.com) + * Authors: Mikael Starvik (starvik@axis.com) */ #define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \ @@ -15,13 +13,13 @@ #define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA)) - + .ascii "HW_PARAM_MAGIC" ; Magic number .dword 0xc0004000 ; Kernel start address ; Debug port #ifdef CONFIG_ETRAX_DEBUG_PORT0 - .dword 0 + .dword 0 #elif defined(CONFIG_ETRAX_DEBUG_PORT1) .dword 1 #elif defined(CONFIG_ETRAX_DEBUG_PORT2) @@ -30,7 +28,7 @@ .dword 3 #else .dword 4 ; No debug -#endif +#endif ; SDRAM or EDO DRAM? #ifdef CONFIG_ETRAX_SDRAM @@ -39,7 +37,7 @@ .dword 0 #endif - ; Register values + ; Register values .dword R_WAITSTATES .dword CONFIG_ETRAX_DEF_R_WAITSTATES .dword R_BUS_CONFIG @@ -56,7 +54,7 @@ .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING #endif .dword R_PORT_PA_SET - .dword PA_SET_VALUE + .dword PA_SET_VALUE .dword R_PORT_PB_SET .dword PB_SET_VALUE .dword 0 ; No more register values diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig index b9e328e688be..a2dd740c5907 100644 --- a/arch/cris/arch-v32/drivers/Kconfig +++ b/arch/cris/arch-v32/drivers/Kconfig @@ -360,24 +360,10 @@ config ETRAX_SER4_DSR_BIT string "Ser 4 DSR bit (empty = not used)" depends on ETRAX_SERIAL_PORT4 -config ETRAX_SER3_CD_BIT +config ETRAX_SER4_CD_BIT string "Ser 4 CD bit (empty = not used)" depends on ETRAX_SERIAL_PORT4 -config ETRAX_RS485 - bool "RS-485 support" - depends on ETRAXFS_SERIAL - help - Enables support for RS-485 serial communication. For a primer on - RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>. - -config ETRAX_RS485_DISABLE_RECEIVER - bool "Disable serial receiver" - depends on ETRAX_RS485 - help - It is necessary to disable the serial receiver to avoid serial - loopback. Not all products are able to do this in software only. - config ETRAX_SYNCHRONOUS_SERIAL bool "Synchronous serial-port support" depends on ETRAX_ARCH_V32 diff --git a/arch/cris/arch-v32/drivers/i2c.c b/arch/cris/arch-v32/drivers/i2c.c index 506826399ae7..2fd6a740d895 100644 --- a/arch/cris/arch-v32/drivers/i2c.c +++ b/arch/cris/arch-v32/drivers/i2c.c @@ -649,10 +649,10 @@ i2c_release(struct inode *inode, struct file *filp) /* Main device API. ioctl's to write or read to/from i2c registers. */ -static int -i2c_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long +i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { + int ret; if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) { return -ENOTTY; } @@ -665,9 +665,13 @@ i2c_ioctl(struct inode *inode, struct file *file, I2C_ARGREG(arg), I2C_ARGVALUE(arg))); - return i2c_writereg(I2C_ARGSLAVE(arg), + lock_kernel(); + ret = i2c_writereg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg), I2C_ARGVALUE(arg)); + unlock_kernel(); + return ret; + case I2C_READREG: { unsigned char val; @@ -675,7 +679,9 @@ i2c_ioctl(struct inode *inode, struct file *file, D(printk("i2cr %d %d ", I2C_ARGSLAVE(arg), I2C_ARGREG(arg))); + lock_kernel(); val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg)); + unlock_kernel(); D(printk("= %d\n", val)); return val; } @@ -688,10 +694,10 @@ i2c_ioctl(struct inode *inode, struct file *file, } static const struct file_operations i2c_fops = { - .owner = THIS_MODULE, - .ioctl = i2c_ioctl, - .open = i2c_open, - .release = i2c_release, + .owner = THIS_MODULE, + .unlocked_ioctl = i2c_ioctl, + .open = i2c_open, + .release = i2c_release, }; static int __init i2c_init(void) diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c index f4478506e52c..bef6eb53b153 100644 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ b/arch/cris/arch-v32/drivers/pcf8563.c @@ -24,6 +24,7 @@ #include <linux/init.h> #include <linux/fs.h> #include <linux/ioctl.h> +#include <linux/smp_lock.h> #include <linux/delay.h> #include <linux/bcd.h> #include <linux/mutex.h> @@ -49,7 +50,7 @@ static DEFINE_MUTEX(rtc_lock); /* Protect state etc */ static const unsigned char days_in_month[] = { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; -int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long); +static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); /* Cache VL bit value read at driver init since writing the RTC_SECOND * register clears the VL status. @@ -57,8 +58,8 @@ int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long); static int voltage_low; static const struct file_operations pcf8563_fops = { - .owner = THIS_MODULE, - .ioctl = pcf8563_ioctl + .owner = THIS_MODULE, + .unlocked_ioctl = pcf8563_unlocked_ioctl, }; unsigned char @@ -208,8 +209,7 @@ pcf8563_exit(void) * ioctl calls for this driver. Why return -ENOTTY upon error? Because * POSIX says so! */ -int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) +static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { /* Some sanity checks. */ if (_IOC_TYPE(cmd) != RTC_MAGIC) @@ -335,6 +335,17 @@ int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } +static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int ret; + + lock_kernel(); + return pcf8563_ioctl(filp, cmd, arg); + unlock_kernel(); + + return ret; +} + static int __init pcf8563_register(void) { if (pcf8563_init() < 0) { diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c index 64933e2c0f5b..bde8d1a10cad 100644 --- a/arch/cris/arch-v32/kernel/crisksyms.c +++ b/arch/cris/arch-v32/kernel/crisksyms.c @@ -24,5 +24,5 @@ EXPORT_SYMBOL(crisv32_io_get_name); EXPORT_SYMBOL(crisv32_io_get); /* Functions masking/unmasking interrupts */ -EXPORT_SYMBOL(mask_irq); -EXPORT_SYMBOL(unmask_irq); +EXPORT_SYMBOL(crisv32_mask_irq); +EXPORT_SYMBOL(crisv32_unmask_irq); diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index b6241198fb98..0b1febe44aa3 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -280,8 +280,7 @@ out: return cpu; } -void -mask_irq(int irq) +void crisv32_mask_irq(int irq) { int cpu; @@ -289,8 +288,7 @@ mask_irq(int irq) block_irq(irq, cpu); } -void -unmask_irq(int irq) +void crisv32_unmask_irq(int irq) { unblock_irq(irq, irq_cpu(irq)); } @@ -298,23 +296,23 @@ unmask_irq(int irq) static unsigned int startup_crisv32_irq(unsigned int irq) { - unmask_irq(irq); + crisv32_unmask_irq(irq); return 0; } static void shutdown_crisv32_irq(unsigned int irq) { - mask_irq(irq); + crisv32_mask_irq(irq); } static void enable_crisv32_irq(unsigned int irq) { - unmask_irq(irq); + crisv32_unmask_irq(irq); } static void disable_crisv32_irq(unsigned int irq) { - mask_irq(irq); + crisv32_mask_irq(irq); } static void ack_crisv32_irq(unsigned int irq) diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c index 058adddf4e4b..84fed3b4b079 100644 --- a/arch/cris/arch-v32/kernel/smp.c +++ b/arch/cris/arch-v32/kernel/smp.c @@ -168,8 +168,8 @@ void __init smp_callin(void) /* Enable IRQ and idle */ REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask); - unmask_irq(IPI_INTR_VECT); - unmask_irq(TIMER0_INTR_VECT); + crisv32_unmask_irq(IPI_INTR_VECT); + crisv32_unmask_irq(TIMER0_INTR_VECT); preempt_disable(); notify_cpu_starting(cpu); local_irq_enable(); diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h index 6248004eca1c..7d345947b3ee 100644 --- a/arch/cris/include/arch-v10/arch/irq.h +++ b/arch/cris/include/arch-v10/arch/irq.h @@ -93,15 +93,16 @@ void set_break_vector(int n, irqvectptr addr); "push $r10\n\t" /* push orig_r10 */ \ "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ - /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ +/* BLOCK_IRQ and UNBLOCK_IRQ do the same as + * crisv10_mask_irq and crisv10_unmask_irq */ #define BLOCK_IRQ(mask,nr) \ "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000d8]\n\t" - + "move.d $r0,[0xb00000d8]\n\t" + #define UNBLOCK_IRQ(mask) \ "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000dc]\n\t" + "move.d $r0,[0xb00000dc]\n\t" #define IRQ_NAME2(nr) nr##_interrupt(void) #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h index 9e4c9fbdfddf..b31e9984f849 100644 --- a/arch/cris/include/arch-v32/arch/irq.h +++ b/arch/cris/include/arch-v32/arch/irq.h @@ -23,8 +23,8 @@ struct etrax_interrupt_vector { extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ -void mask_irq(int irq); -void unmask_irq(int irq); +void crisv32_mask_irq(int irq); +void crisv32_unmask_irq(int irq); void set_exception_vector(int n, irqvectptr addr); diff --git a/arch/cris/include/asm/param.h b/arch/cris/include/asm/param.h index 0e47994e40be..484fcf8667c0 100644 --- a/arch/cris/include/asm/param.h +++ b/arch/cris/include/asm/param.h @@ -2,22 +2,9 @@ #define _ASMCRIS_PARAM_H /* Currently we assume that HZ=100 is good for CRIS. */ -#ifdef __KERNEL__ -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif #define EXEC_PAGESIZE 8192 -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ +#include <asm-generic/param.h> -#endif +#endif /* _ASMCRIS_PARAM_H */ diff --git a/arch/cris/include/asm/scatterlist.h b/arch/cris/include/asm/scatterlist.h index faff53ad1f96..249a7842ff5f 100644 --- a/arch/cris/include/asm/scatterlist.h +++ b/arch/cris/include/asm/scatterlist.h @@ -1,22 +1,7 @@ #ifndef __ASM_CRIS_SCATTERLIST_H #define __ASM_CRIS_SCATTERLIST_H -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - char * address; /* Location data is to be transferred to */ - unsigned int length; - - /* The following is i386 highmem junk - not used by us */ - unsigned long page_link; - unsigned int offset;/* for highmem, page offset */ - -}; - -#define sg_dma_address(sg) ((sg)->address) -#define sg_dma_len(sg) ((sg)->length) -/* i386 junk */ +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0x1fffffff) diff --git a/arch/frv/include/asm/gdb-stub.h b/arch/frv/include/asm/gdb-stub.h index 2da716407ff2..e6bedd0cd9a5 100644 --- a/arch/frv/include/asm/gdb-stub.h +++ b/arch/frv/include/asm/gdb-stub.h @@ -12,6 +12,7 @@ #ifndef __ASM_GDB_STUB_H #define __ASM_GDB_STUB_H +#undef GDBSTUB_DEBUG_IO #undef GDBSTUB_DEBUG_PROTOCOL #include <asm/ptrace.h> @@ -108,6 +109,12 @@ extern void gdbstub_printk(const char *fmt, ...); extern void debug_to_serial(const char *p, int n); extern void console_set_baud(unsigned baud); +#ifdef GDBSTUB_DEBUG_IO +#define gdbstub_io(FMT,...) gdbstub_printk(FMT, ##__VA_ARGS__) +#else +#define gdbstub_io(FMT,...) ({ 0; }) +#endif + #ifdef GDBSTUB_DEBUG_PROTOCOL #define gdbstub_proto(FMT,...) gdbstub_printk(FMT,##__VA_ARGS__) #else diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h index 2947764fc0e0..ccae981876fa 100644 --- a/arch/frv/include/asm/mem-layout.h +++ b/arch/frv/include/asm/mem-layout.h @@ -35,8 +35,8 @@ * the slab must be aligned such that load- and store-double instructions don't * fault if used */ -#define ARCH_KMALLOC_MINALIGN 8 -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES /*****************************************************************************/ /* diff --git a/arch/frv/include/asm/scatterlist.h b/arch/frv/include/asm/scatterlist.h index 4bca8a28546c..1614bfd7e3a4 100644 --- a/arch/frv/include/asm/scatterlist.h +++ b/arch/frv/include/asm/scatterlist.h @@ -1,45 +1,7 @@ #ifndef _ASM_SCATTERLIST_H #define _ASM_SCATTERLIST_H -#include <asm/types.h> - -/* - * Drivers must set either ->address or (preferred) page and ->offset - * to indicate where data must be transferred to/from. - * - * Using page is recommended since it handles highmem data as well as - * low mem. ->address is restricted to data which has a virtual mapping, and - * it will go away in the future. Updating to page can be automated very - * easily -- something like - * - * sg->address = some_ptr; - * - * can be rewritten as - * - * sg_set_buf(sg, some_ptr, length); - * - * and that's it. There's no excuse for not highmem enabling YOUR driver. /jens - */ -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; /* for highmem, page offset */ - - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0xffffffffUL) diff --git a/arch/frv/kernel/break.S b/arch/frv/kernel/break.S index bd0bdf908d93..cbb6958a3147 100644 --- a/arch/frv/kernel/break.S +++ b/arch/frv/kernel/break.S @@ -21,7 +21,7 @@ # # the break handler has its own stack # - .section .bss.stack + .section .bss..stack .globl __break_user_context .balign THREAD_SIZE __break_stack: @@ -63,7 +63,7 @@ __break_trace_through_exceptions: # entry point for Break Exceptions/Interrupts # ############################################################################### - .section .text.break + .section .text..break .balign 4 .globl __entry_break __entry_break: diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S index 189397ec012a..63d579bf1c29 100644 --- a/arch/frv/kernel/entry.S +++ b/arch/frv/kernel/entry.S @@ -38,7 +38,7 @@ #define nr_syscalls ((syscall_table_size)/4) - .section .text.entry + .section .text..entry .balign 4 .macro LEDS val diff --git a/arch/frv/kernel/gdb-io.c b/arch/frv/kernel/gdb-io.c index c997bccb9221..2ca641d199f8 100644 --- a/arch/frv/kernel/gdb-io.c +++ b/arch/frv/kernel/gdb-io.c @@ -171,11 +171,11 @@ int gdbstub_rx_char(unsigned char *_ch, int nonblock) return -EINTR; } else if (st & (UART_LSR_FE|UART_LSR_OE|UART_LSR_PE)) { - gdbstub_proto("### GDB Rx Error (st=%02x) ###\n",st); + gdbstub_io("### GDB Rx Error (st=%02x) ###\n",st); return -EIO; } else { - gdbstub_proto("### GDB Rx %02x (st=%02x) ###\n",ch,st); + gdbstub_io("### GDB Rx %02x (st=%02x) ###\n",ch,st); *_ch = ch & 0x7f; return 0; } diff --git a/arch/frv/kernel/gdb-stub.c b/arch/frv/kernel/gdb-stub.c index 7ca8a6b19ac9..a4dba6b20bd0 100644 --- a/arch/frv/kernel/gdb-stub.c +++ b/arch/frv/kernel/gdb-stub.c @@ -1344,6 +1344,44 @@ void gdbstub_get_mmu_state(void) } /* end gdbstub_get_mmu_state() */ +/* + * handle general query commands of the form 'qXXXXX' + */ +static void gdbstub_handle_query(void) +{ + if (strcmp(input_buffer, "qAttached") == 0) { + /* return current thread ID */ + sprintf(output_buffer, "1"); + return; + } + + if (strcmp(input_buffer, "qC") == 0) { + /* return current thread ID */ + sprintf(output_buffer, "QC 0"); + return; + } + + if (strcmp(input_buffer, "qOffsets") == 0) { + /* return relocation offset of text and data segments */ + sprintf(output_buffer, "Text=0;Data=0;Bss=0"); + return; + } + + if (strcmp(input_buffer, "qSymbol::") == 0) { + sprintf(output_buffer, "OK"); + return; + } + + if (strcmp(input_buffer, "qSupported") == 0) { + /* query of supported features */ + sprintf(output_buffer, "PacketSize=%u;ReverseContinue-;ReverseStep-", + sizeof(input_buffer)); + return; + } + + gdbstub_strcpy(output_buffer,"E01"); +} + /*****************************************************************************/ /* * handle event interception and GDB remote protocol processing @@ -1751,6 +1789,12 @@ void gdbstub(int sigval) flush_cache = 1; break; + /* pNN: Read value of reg N and return it */ + case 'p': + /* return no value, indicating that we don't support + * this command and that gdb should use 'g' instead */ + break; + /* PNN,=RRRRRRRR: Write value R to reg N return OK */ case 'P': ptr = &input_buffer[1]; @@ -1840,6 +1884,10 @@ void gdbstub(int sigval) case 'k' : goto done; /* just continue */ + /* detach */ + case 'D': + gdbstub_strcpy(output_buffer, "OK"); + break; /* reset the whole machine (FIXME: system dependent) */ case 'r': @@ -1852,6 +1900,14 @@ void gdbstub(int sigval) __debug_status.dcr |= DCR_SE; goto done; + /* extended command */ + case 'v': + if (strcmp(input_buffer, "vCont?") == 0) { + output_buffer[0] = 0; + break; + } + goto unsupported_cmd; + /* set baud rate (bBB) */ case 'b': ptr = &input_buffer[1]; @@ -1923,8 +1979,19 @@ void gdbstub(int sigval) gdbstub_strcpy(output_buffer,"OK"); break; + /* Thread-setting packet */ + case 'H': + gdbstub_strcpy(output_buffer, "OK"); + break; + + case 'q': + gdbstub_handle_query(); + break; + default: + unsupported_cmd: gdbstub_proto("### GDB Unsupported Cmd '%s'\n",input_buffer); + gdbstub_strcpy(output_buffer,"E01"); break; } diff --git a/arch/frv/kernel/head.S b/arch/frv/kernel/head.S index b825ef3f2d54..e9a8cc63ac94 100644 --- a/arch/frv/kernel/head.S +++ b/arch/frv/kernel/head.S @@ -542,7 +542,7 @@ __head_end: .size _boot, .-_boot # provide a point for GDB to place a break - .section .text.start,"ax" + .section .text..start,"ax" .globl _start .balign 4 _start: diff --git a/arch/frv/kernel/ptrace.c b/arch/frv/kernel/ptrace.c index 60eeed3694c0..fac028936a04 100644 --- a/arch/frv/kernel/ptrace.c +++ b/arch/frv/kernel/ptrace.c @@ -344,26 +344,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) 0, sizeof(child->thread.user->f), (const void __user *)data); - case PTRACE_GETFDPIC: - tmp = 0; - switch (addr) { - case PTRACE_GETFDPIC_EXEC: - tmp = child->mm->context.exec_fdpic_loadmap; - break; - case PTRACE_GETFDPIC_INTERP: - tmp = child->mm->context.interp_fdpic_loadmap; - break; - default: - break; - } - - ret = 0; - if (put_user(tmp, (unsigned long *) data)) { - ret = -EFAULT; - break; - } - break; - default: ret = ptrace_request(child, request, addr, data); break; diff --git a/arch/frv/kernel/sysctl.c b/arch/frv/kernel/sysctl.c index 71abd1510a59..6c155d69da29 100644 --- a/arch/frv/kernel/sysctl.c +++ b/arch/frv/kernel/sysctl.c @@ -46,8 +46,9 @@ static void frv_change_dcache_mode(unsigned long newmode) /* * handle requests to dynamically switch the write caching mode delivered by /proc */ -static int procctl_frv_cachemode(ctl_table *table, int write, struct file *filp, - void __user *buffer, size_t *lenp, loff_t *ppos) +static int procctl_frv_cachemode(ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { unsigned long hsr0; char buff[8]; @@ -84,7 +85,7 @@ static int procctl_frv_cachemode(ctl_table *table, int write, struct file *filp, } /* read the state */ - if (filp->f_pos > 0) { + if (*ppos > 0) { *lenp = 0; return 0; } @@ -110,7 +111,7 @@ static int procctl_frv_cachemode(ctl_table *table, int write, struct file *filp, return -EFAULT; *lenp = len; - filp->f_pos = len; + *ppos = len; return 0; } /* end procctl_frv_cachemode() */ @@ -120,8 +121,9 @@ static int procctl_frv_cachemode(ctl_table *table, int write, struct file *filp, * permit the mm_struct the nominated process is using have its MMU context ID pinned */ #ifdef CONFIG_MMU -static int procctl_frv_pin_cxnr(ctl_table *table, int write, struct file *filp, - void __user *buffer, size_t *lenp, loff_t *ppos) +static int procctl_frv_pin_cxnr(ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { pid_t pid; char buff[16], *p; @@ -150,7 +152,7 @@ static int procctl_frv_pin_cxnr(ctl_table *table, int write, struct file *filp, } /* read the currently pinned CXN */ - if (filp->f_pos > 0) { + if (*ppos > 0) { *lenp = 0; return 0; } @@ -163,7 +165,7 @@ static int procctl_frv_pin_cxnr(ctl_table *table, int write, struct file *filp, return -EFAULT; *lenp = len; - filp->f_pos = len; + *ppos = len; return 0; } /* end procctl_frv_pin_cxnr() */ diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S index cbe811fccfcc..8b973f3cc90e 100644 --- a/arch/frv/kernel/vmlinux.lds.S +++ b/arch/frv/kernel/vmlinux.lds.S @@ -57,10 +57,10 @@ SECTIONS _text = .; _stext = .; .text : { - *(.text.start) - *(.text.entry) - *(.text.break) - *(.text.tlbmiss) + *(.text..start) + *(.text..entry) + *(.text..break) + *(.text..tlbmiss) TEXT_TEXT SCHED_TEXT LOCK_TEXT @@ -114,7 +114,7 @@ SECTIONS .sbss : { *(.sbss .sbss.*) } .bss : { *(.bss .bss.*) } - .bss.stack : { *(.bss) } + .bss..stack : { *(.bss) } __bss_stop = .; _end = . ; diff --git a/arch/frv/mm/fault.c b/arch/frv/mm/fault.c index 30f5d100a81c..a325d57a83d5 100644 --- a/arch/frv/mm/fault.c +++ b/arch/frv/mm/fault.c @@ -257,10 +257,10 @@ asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear */ out_of_memory: up_read(&mm->mmap_sem); - printk("VM: killing process %s\n", current->comm); - if (user_mode(__frame)) - do_group_exit(SIGKILL); - goto no_context; + if (!user_mode(__frame)) + goto no_context; + pagefault_out_of_memory(); + return; do_sigbus: up_read(&mm->mmap_sem); diff --git a/arch/frv/mm/tlb-miss.S b/arch/frv/mm/tlb-miss.S index 7f392bc651a3..f3ac019bb18b 100644 --- a/arch/frv/mm/tlb-miss.S +++ b/arch/frv/mm/tlb-miss.S @@ -15,7 +15,7 @@ #include <asm/pgtable.h> #include <asm/spr-regs.h> - .section .text.tlbmiss + .section .text..tlbmiss .balign 4 .globl __entry_insn_mmu_miss diff --git a/arch/h8300/boot/compressed/head.S b/arch/h8300/boot/compressed/head.S index 985a81a2435a..10e9a2d1cc6c 100644 --- a/arch/h8300/boot/compressed/head.S +++ b/arch/h8300/boot/compressed/head.S @@ -9,7 +9,7 @@ #define SRAM_START 0xff4000 - .section .text.startup + .section .text..startup .global startup startup: mov.l #SRAM_START+0x8000, sp diff --git a/arch/h8300/boot/compressed/vmlinux.lds b/arch/h8300/boot/compressed/vmlinux.lds index 65e2a0d1ae39..a0a3a0ed54ef 100644 --- a/arch/h8300/boot/compressed/vmlinux.lds +++ b/arch/h8300/boot/compressed/vmlinux.lds @@ -4,7 +4,7 @@ SECTIONS { __stext = . ; __text = .; - *(.text.startup) + *(.text..startup) *(.text) __etext = . ; } diff --git a/arch/h8300/include/asm/scatterlist.h b/arch/h8300/include/asm/scatterlist.h index d3ecdd87ac90..de08a4a2cc1c 100644 --- a/arch/h8300/include/asm/scatterlist.h +++ b/arch/h8300/include/asm/scatterlist.h @@ -1,17 +1,7 @@ #ifndef _H8300_SCATTERLIST_H #define _H8300_SCATTERLIST_H -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0xffffffff) diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 9676100b83ee..95610820041e 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -56,6 +56,9 @@ config MMU config NEED_DMA_MAP_STATE def_bool y +config NEED_SG_DMA_LENGTH + def_bool y + config SWIOTLB bool @@ -495,6 +498,14 @@ config HAVE_ARCH_NODEDATA_EXTENSION def_bool y depends on NUMA +config USE_PERCPU_NUMA_NODE_ID + def_bool y + depends on NUMA + +config HAVE_MEMORYLESS_NODES + def_bool y + depends on NUMA + config ARCH_PROC_KCORE_TEXT def_bool y depends on PROC_KCORE diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index 21adbd7f90f8..837dc82a013e 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -94,7 +94,6 @@ ia64_acpi_release_global_lock (unsigned int *lock) #define acpi_noirq 0 /* ACPI always enabled on IA64 */ #define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */ #define acpi_strict 1 /* no ACPI spec workarounds on IA64 */ -#define acpi_ht 0 /* no HT-only mode on IA64 */ #endif #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } diff --git a/arch/ia64/include/asm/asmmacro.h b/arch/ia64/include/asm/asmmacro.h index c1642fd64029..3ab6d75aa3db 100644 --- a/arch/ia64/include/asm/asmmacro.h +++ b/arch/ia64/include/asm/asmmacro.h @@ -70,12 +70,12 @@ name: * path (ivt.S - TLB miss processing) or in places where it might not be * safe to use a "tpa" instruction (mca_asm.S - error recovery). */ - .section ".data.patch.vtop", "a" // declare section & section attributes + .section ".data..patch.vtop", "a" // declare section & section attributes .previous #define LOAD_PHYSICAL(pr, reg, obj) \ [1:](pr)movl reg = obj; \ - .xdata4 ".data.patch.vtop", 1b-. + .xdata4 ".data..patch.vtop", 1b-. /* * For now, we always put in the McKinley E9 workaround. On CPUs that don't need it, @@ -84,11 +84,11 @@ name: #define DO_MCKINLEY_E9_WORKAROUND #ifdef DO_MCKINLEY_E9_WORKAROUND - .section ".data.patch.mckinley_e9", "a" + .section ".data..patch.mckinley_e9", "a" .previous /* workaround for Itanium 2 Errata 9: */ # define FSYS_RETURN \ - .xdata4 ".data.patch.mckinley_e9", 1f-.; \ + .xdata4 ".data..patch.mckinley_e9", 1f-.; \ 1:{ .mib; \ nop.m 0; \ mov r16=ar.pfs; \ @@ -107,11 +107,11 @@ name: * If physical stack register size is different from DEF_NUM_STACK_REG, * dynamically patch the kernel for correct size. */ - .section ".data.patch.phys_stack_reg", "a" + .section ".data..patch.phys_stack_reg", "a" .previous #define LOAD_PHYS_STACK_REG_SIZE(reg) \ [1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \ - .xdata4 ".data.patch.phys_stack_reg", 1b-. + .xdata4 ".data..patch.phys_stack_reg", 1b-. /* * Up until early 2004, use of .align within a function caused bad unwind info. diff --git a/arch/ia64/include/asm/cache.h b/arch/ia64/include/asm/cache.h index e7482bd628ff..988254a7d349 100644 --- a/arch/ia64/include/asm/cache.h +++ b/arch/ia64/include/asm/cache.h @@ -24,6 +24,6 @@ # define SMP_CACHE_BYTES (1 << 3) #endif -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #endif /* _ASM_IA64_CACHE_H */ diff --git a/arch/ia64/include/asm/percpu.h b/arch/ia64/include/asm/percpu.h index 1bd408265694..14aa1c58912b 100644 --- a/arch/ia64/include/asm/percpu.h +++ b/arch/ia64/include/asm/percpu.h @@ -31,7 +31,7 @@ extern void *per_cpu_init(void); #endif /* SMP */ -#define PER_CPU_BASE_SECTION ".data.percpu" +#define PER_CPU_BASE_SECTION ".data..percpu" /* * Be extremely careful when taking the address of this variable! Due to virtual diff --git a/arch/ia64/include/asm/scatterlist.h b/arch/ia64/include/asm/scatterlist.h index d8e98961dec7..f299a4fb25c8 100644 --- a/arch/ia64/include/asm/scatterlist.h +++ b/arch/ia64/include/asm/scatterlist.h @@ -1,6 +1,7 @@ #ifndef _ASM_IA64_SCATTERLIST_H #define _ASM_IA64_SCATTERLIST_H +#include <asm-generic/scatterlist.h> /* * It used to be that ISA_DMA_THRESHOLD had something to do with the * DMA-limits of ISA-devices. Nowadays, its only remaining use (apart @@ -10,7 +11,6 @@ * that's 4GB - 1. */ #define ISA_DMA_THRESHOLD 0xffffffff - -#include <asm-generic/scatterlist.h> +#define ARCH_HAS_SG_CHAIN #endif /* _ASM_IA64_SCATTERLIST_H */ diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h index d323071d0f91..09f646753d1a 100644 --- a/arch/ia64/include/asm/topology.h +++ b/arch/ia64/include/asm/topology.h @@ -26,11 +26,6 @@ #define RECLAIM_DISTANCE 15 /* - * Returns the number of the node containing CPU 'cpu' - */ -#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu]) - -/* * Returns a bitmask of CPUs on Node 'node'. */ #define cpumask_of_node(node) ((node) == -1 ? \ diff --git a/arch/ia64/kernel/Makefile.gate b/arch/ia64/kernel/Makefile.gate index ab9b03a9adcc..ceeffc509764 100644 --- a/arch/ia64/kernel/Makefile.gate +++ b/arch/ia64/kernel/Makefile.gate @@ -21,7 +21,7 @@ GATECFLAGS_gate-syms.o = -r $(obj)/gate-syms.o: $(obj)/gate.lds $(obj)/gate.o FORCE $(call if_changed,gate) -# gate-data.o contains the gate DSO image as data in section .data.gate. +# gate-data.o contains the gate DSO image as data in section .data..gate. # We must build gate.so before we can assemble it. # Note: kbuild does not track this dependency due to usage of .incbin $(obj)/gate-data.o: $(obj)/gate.so diff --git a/arch/ia64/kernel/gate-data.S b/arch/ia64/kernel/gate-data.S index 258c0a3238fb..b3ef1c72e132 100644 --- a/arch/ia64/kernel/gate-data.S +++ b/arch/ia64/kernel/gate-data.S @@ -1,3 +1,3 @@ - .section .data.gate, "aw" + .section .data..gate, "aw" .incbin "arch/ia64/kernel/gate.so" diff --git a/arch/ia64/kernel/gate.S b/arch/ia64/kernel/gate.S index cf5e0a105e16..245d3e1ec7e1 100644 --- a/arch/ia64/kernel/gate.S +++ b/arch/ia64/kernel/gate.S @@ -21,18 +21,18 @@ * to targets outside the shared object) and to avoid multi-phase kernel builds, we * simply create minimalistic "patch lists" in special ELF sections. */ - .section ".data.patch.fsyscall_table", "a" + .section ".data..patch.fsyscall_table", "a" .previous #define LOAD_FSYSCALL_TABLE(reg) \ [1:] movl reg=0; \ - .xdata4 ".data.patch.fsyscall_table", 1b-. + .xdata4 ".data..patch.fsyscall_table", 1b-. - .section ".data.patch.brl_fsys_bubble_down", "a" + .section ".data..patch.brl_fsys_bubble_down", "a" .previous #define BRL_COND_FSYS_BUBBLE_DOWN(pr) \ [1:](pr)brl.cond.sptk 0; \ ;; \ - .xdata4 ".data.patch.brl_fsys_bubble_down", 1b-. + .xdata4 ".data..patch.brl_fsys_bubble_down", 1b-. GLOBAL_ENTRY(__kernel_syscall_via_break) .prologue diff --git a/arch/ia64/kernel/gate.lds.S b/arch/ia64/kernel/gate.lds.S index 88c64ed47c36..d32b0855110a 100644 --- a/arch/ia64/kernel/gate.lds.S +++ b/arch/ia64/kernel/gate.lds.S @@ -33,21 +33,21 @@ SECTIONS */ . = GATE_ADDR + 0x600; - .data.patch : { + .data..patch : { __paravirt_start_gate_mckinley_e9_patchlist = .; - *(.data.patch.mckinley_e9) + *(.data..patch.mckinley_e9) __paravirt_end_gate_mckinley_e9_patchlist = .; __paravirt_start_gate_vtop_patchlist = .; - *(.data.patch.vtop) + *(.data..patch.vtop) __paravirt_end_gate_vtop_patchlist = .; __paravirt_start_gate_fsyscall_patchlist = .; - *(.data.patch.fsyscall_table) + *(.data..patch.fsyscall_table) __paravirt_end_gate_fsyscall_patchlist = .; __paravirt_start_gate_brl_fsys_bubble_down_patchlist = .; - *(.data.patch.brl_fsys_bubble_down) + *(.data..patch.brl_fsys_bubble_down) __paravirt_end_gate_brl_fsys_bubble_down_patchlist = .; } :readable diff --git a/arch/ia64/kernel/init_task.c b/arch/ia64/kernel/init_task.c index e253ab8fcbc8..f9efe9739d3f 100644 --- a/arch/ia64/kernel/init_task.c +++ b/arch/ia64/kernel/init_task.c @@ -23,7 +23,7 @@ static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); * Initial task structure. * * We need to make sure that this is properly aligned due to the way process stacks are - * handled. This is done by having a special ".data.init_task" section... + * handled. This is done by having a special ".data..init_task" section... */ #define init_thread_info init_task_mem.s.thread_info diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S index 179fd122e837..d93e396bf599 100644 --- a/arch/ia64/kernel/ivt.S +++ b/arch/ia64/kernel/ivt.S @@ -82,7 +82,7 @@ mov r19=n;; /* prepare to save predicates */ \ br.sptk.many dispatch_to_fault_handler - .section .text.ivt,"ax" + .section .text..ivt,"ax" .align 32768 // align on 32KB boundary .global ia64_ivt diff --git a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h index 292e214a3b84..d56753a11636 100644 --- a/arch/ia64/kernel/minstate.h +++ b/arch/ia64/kernel/minstate.h @@ -16,7 +16,7 @@ #define ACCOUNT_SYS_ENTER #endif -.section ".data.patch.rse", "a" +.section ".data..patch.rse", "a" .previous /* @@ -215,7 +215,7 @@ (pUStk) extr.u r17=r18,3,6; \ (pUStk) sub r16=r18,r22; \ [1:](pKStk) br.cond.sptk.many 1f; \ - .xdata4 ".data.patch.rse",1b-. \ + .xdata4 ".data..patch.rse",1b-. \ ;; \ cmp.ge p6,p7 = 33,r17; \ ;; \ diff --git a/arch/ia64/kernel/paravirtentry.S b/arch/ia64/kernel/paravirtentry.S index 6158560d7f17..92d880c4d3d1 100644 --- a/arch/ia64/kernel/paravirtentry.S +++ b/arch/ia64/kernel/paravirtentry.S @@ -28,7 +28,7 @@ #include "entry.h" #define DATA8(sym, init_value) \ - .pushsection .data.read_mostly ; \ + .pushsection .data..read_mostly ; \ .align 8 ; \ .global sym ; \ sym: ; \ diff --git a/arch/ia64/kernel/pci-swiotlb.c b/arch/ia64/kernel/pci-swiotlb.c index 3095654f9ab3..d9485d952ed0 100644 --- a/arch/ia64/kernel/pci-swiotlb.c +++ b/arch/ia64/kernel/pci-swiotlb.c @@ -31,8 +31,6 @@ struct dma_map_ops swiotlb_dma_ops = { .unmap_sg = swiotlb_unmap_sg_attrs, .sync_single_for_cpu = swiotlb_sync_single_for_cpu, .sync_single_for_device = swiotlb_sync_single_for_device, - .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu, - .sync_single_range_for_device = swiotlb_sync_single_range_for_device, .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, .sync_sg_for_device = swiotlb_sync_sg_for_device, .dma_supported = swiotlb_dma_supported, diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c index 0dec7f702448..7c7909f9bc93 100644 --- a/arch/ia64/kernel/ptrace.c +++ b/arch/ia64/kernel/ptrace.c @@ -638,7 +638,7 @@ ptrace_attach_sync_user_rbs (struct task_struct *child) */ read_lock(&tasklist_lock); - if (child->signal) { + if (child->sighand) { spin_lock_irq(&child->sighand->siglock); if (child->state == TASK_STOPPED && !test_and_set_tsk_thread_flag(child, TIF_RESTORE_RSE)) { @@ -662,7 +662,7 @@ ptrace_attach_sync_user_rbs (struct task_struct *child) * job control stop, so that SIGCONT can be used to wake it up. */ read_lock(&tasklist_lock); - if (child->signal) { + if (child->sighand) { spin_lock_irq(&child->sighand->siglock); if (child->state == TASK_TRACED && (child->signal->flags & SIGNAL_STOP_STOPPED)) { diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index e5230b2ff2c5..6a1380e90f87 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c @@ -390,6 +390,14 @@ smp_callin (void) fix_b0_for_bsp(); +#ifdef CONFIG_NUMA + /* + * numa_node_id() works after this. + */ + set_numa_node(cpu_to_node_map[cpuid]); + set_numa_mem(local_memory_node(cpu_to_node_map[cpuid])); +#endif + ipi_call_lock_irq(); spin_lock(&vector_lock); /* Setup the per cpu irq handling data structures */ @@ -632,6 +640,9 @@ void __devinit smp_prepare_boot_cpu(void) { cpu_set(smp_processor_id(), cpu_online_map); cpu_set(smp_processor_id(), cpu_callin_map); +#ifdef CONFIG_NUMA + set_numa_node(cpu_to_node_map[smp_processor_id()]); +#endif per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; paravirt_post_smp_prepare_boot_cpu(); } diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S index 1295ba327f6f..e07218a2577f 100644 --- a/arch/ia64/kernel/vmlinux.lds.S +++ b/arch/ia64/kernel/vmlinux.lds.S @@ -8,7 +8,7 @@ #define IVT_TEXT \ VMLINUX_SYMBOL(__start_ivt_text) = .; \ - *(.text.ivt) \ + *(.text..ivt) \ VMLINUX_SYMBOL(__end_ivt_text) = .; OUTPUT_FORMAT("elf64-ia64-little") @@ -54,8 +54,8 @@ SECTIONS .text2 : AT(ADDR(.text2) - LOAD_OFFSET) { *(.text2) } #ifdef CONFIG_SMP - .text.lock : AT(ADDR(.text.lock) - LOAD_OFFSET) - { *(.text.lock) } + .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET) + { *(.text..lock) } #endif _etext = .; @@ -75,10 +75,10 @@ SECTIONS __stop___mca_table = .; } - .data.patch.phys_stack_reg : AT(ADDR(.data.patch.phys_stack_reg) - LOAD_OFFSET) + .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET) { __start___phys_stack_reg_patchlist = .; - *(.data.patch.phys_stack_reg) + *(.data..patch.phys_stack_reg) __end___phys_stack_reg_patchlist = .; } @@ -110,24 +110,24 @@ SECTIONS INIT_TEXT_SECTION(PAGE_SIZE) INIT_DATA_SECTION(16) - .data.patch.vtop : AT(ADDR(.data.patch.vtop) - LOAD_OFFSET) + .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET) { __start___vtop_patchlist = .; - *(.data.patch.vtop) + *(.data..patch.vtop) __end___vtop_patchlist = .; } - .data.patch.rse : AT(ADDR(.data.patch.rse) - LOAD_OFFSET) + .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET) { __start___rse_patchlist = .; - *(.data.patch.rse) + *(.data..patch.rse) __end___rse_patchlist = .; } - .data.patch.mckinley_e9 : AT(ADDR(.data.patch.mckinley_e9) - LOAD_OFFSET) + .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET) { __start___mckinley_e9_bundles = .; - *(.data.patch.mckinley_e9) + *(.data..patch.mckinley_e9) __end___mckinley_e9_bundles = .; } @@ -175,17 +175,17 @@ SECTIONS . = ALIGN(PAGE_SIZE); __init_end = .; - .data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) + .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) { PAGE_ALIGNED_DATA(PAGE_SIZE) . = ALIGN(PAGE_SIZE); __start_gate_section = .; - *(.data.gate) + *(.data..gate) __stop_gate_section = .; #ifdef CONFIG_XEN . = ALIGN(PAGE_SIZE); __xen_start_gate_section = .; - *(.data.gate.xen) + *(.data..gate.xen) __xen_stop_gate_section = .; #endif } diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c index 29afd9a252ff..9b109f25e49c 100644 --- a/arch/ia64/kvm/kvm-ia64.c +++ b/arch/ia64/kvm/kvm-ia64.c @@ -144,6 +144,7 @@ int kvm_arch_hardware_enable(void *garbage) VP_INIT_ENV : VP_INIT_ENV_INITALIZE, __pa(kvm_vm_buffer), KVM_VM_BUFFER_BASE, &tmp_base); if (status != 0) { + spin_unlock(&vp_lock); printk(KERN_WARNING"kvm: Failed to Enable VT Support!!!!\n"); return -EINVAL; } @@ -979,11 +980,13 @@ long kvm_arch_vm_ioctl(struct file *filp, r = -EFAULT; if (copy_from_user(&irq_event, argp, sizeof irq_event)) goto out; + r = -ENXIO; if (irqchip_in_kernel(kvm)) { __s32 status; status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, irq_event.irq, irq_event.level); if (ioctl == KVM_IRQ_LINE_STATUS) { + r = -EFAULT; irq_event.status = status; if (copy_to_user(argp, &irq_event, sizeof irq_event)) @@ -1379,7 +1382,7 @@ static void kvm_release_vm_pages(struct kvm *kvm) int i, j; unsigned long base_gfn; - slots = rcu_dereference(kvm->memslots); + slots = kvm_memslots(kvm); for (i = 0; i < slots->nmemslots; i++) { memslot = &slots->memslots[i]; base_gfn = memslot->base_gfn; @@ -1535,8 +1538,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp, goto out; if (copy_to_user(user_stack, stack, - sizeof(struct kvm_ia64_vcpu_stack))) + sizeof(struct kvm_ia64_vcpu_stack))) { + r = -EFAULT; goto out; + } break; } diff --git a/arch/ia64/kvm/vmm.c b/arch/ia64/kvm/vmm.c index 7a62f75778c5..f0b9cac82414 100644 --- a/arch/ia64/kvm/vmm.c +++ b/arch/ia64/kvm/vmm.c @@ -51,7 +51,7 @@ static int __init kvm_vmm_init(void) vmm_fpswa_interface = fpswa_interface; /*Register vmm data to kvm side*/ - return kvm_init(&vmm_info, 1024, THIS_MODULE); + return kvm_init(&vmm_info, 1024, 0, THIS_MODULE); } static void __exit kvm_vmm_exit(void) diff --git a/arch/ia64/kvm/vmm_ivt.S b/arch/ia64/kvm/vmm_ivt.S index 40920c630649..24018484c6e9 100644 --- a/arch/ia64/kvm/vmm_ivt.S +++ b/arch/ia64/kvm/vmm_ivt.S @@ -104,7 +104,7 @@ GLOBAL_ENTRY(kvm_vmm_panic) br.call.sptk.many b6=vmm_panic_handler; END(kvm_vmm_panic) - .section .text.ivt,"ax" + .section .text..ivt,"ax" .align 32768 // align on 32KB boundary .global kvm_ia64_ivt diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 64aff520b899..aa2533ae7e9e 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -335,8 +335,11 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) } struct pci_bus * __devinit -pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) +pci_acpi_scan_root(struct acpi_pci_root *root) { + struct acpi_device *device = root->device; + int domain = root->segment; + int bus = root->secondary.start; struct pci_controller *controller; unsigned int windows = 0; struct pci_bus *pbus; diff --git a/arch/ia64/scripts/unwcheck.py b/arch/ia64/scripts/unwcheck.py index c27849889e19..2bfd941ff7c7 100644 --- a/arch/ia64/scripts/unwcheck.py +++ b/arch/ia64/scripts/unwcheck.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/python # # Usage: unwcheck.py FILE # diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c index f6c1c5fd075d..fa1eceed0d23 100644 --- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c +++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c @@ -30,7 +30,6 @@ #include <linux/miscdevice.h> #include <linux/utsname.h> #include <linux/cpumask.h> -#include <linux/smp_lock.h> #include <linux/nodemask.h> #include <linux/smp.h> #include <linux/mutex.h> @@ -682,8 +681,7 @@ static int sn_hwperf_map_err(int hwperf_err) /* * ioctl for "sn_hwperf" misc device */ -static int -sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, unsigned long arg) +static long sn_hwperf_ioctl(struct file *fp, u32 op, unsigned long arg) { struct sn_hwperf_ioctl_args a; struct cpuinfo_ia64 *cdata; @@ -699,8 +697,6 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, unsigned long arg) int i; int j; - unlock_kernel(); - /* only user requests are allowed here */ if ((op & SN_HWPERF_OP_MASK) < 10) { r = -EINVAL; @@ -859,12 +855,11 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, unsigned long arg) error: vfree(p); - lock_kernel(); return r; } static const struct file_operations sn_hwperf_fops = { - .ioctl = sn_hwperf_ioctl, + .unlocked_ioctl = sn_hwperf_ioctl, }; static struct miscdevice sn_hwperf_dev = { diff --git a/arch/ia64/xen/gate-data.S b/arch/ia64/xen/gate-data.S index 7d4830afc91d..6f95b6b32a4e 100644 --- a/arch/ia64/xen/gate-data.S +++ b/arch/ia64/xen/gate-data.S @@ -1,3 +1,3 @@ - .section .data.gate.xen, "aw" + .section .data..gate.xen, "aw" .incbin "arch/ia64/xen/gate.so" diff --git a/arch/ia64/xen/xensetup.S b/arch/ia64/xen/xensetup.S index aff8346ea193..b820ed02ab9f 100644 --- a/arch/ia64/xen/xensetup.S +++ b/arch/ia64/xen/xensetup.S @@ -14,7 +14,7 @@ #include <linux/init.h> #include <xen/interface/elfnote.h> - .section .data.read_mostly + .section .data..read_mostly .align 8 .global xen_domain_type xen_domain_type: diff --git a/arch/m32r/include/asm/scatterlist.h b/arch/m32r/include/asm/scatterlist.h index 1ed372c73d0b..aeeddd8dac17 100644 --- a/arch/m32r/include/asm/scatterlist.h +++ b/arch/m32r/include/asm/scatterlist.h @@ -1,20 +1,7 @@ #ifndef _ASM_M32R_SCATTERLIST_H #define _ASM_M32R_SCATTERLIST_H -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - char * address; /* Location data is to be transferred to, NULL for - * highmem page */ - unsigned long page_link; - unsigned int offset;/* for highmem, page offset */ - - dma_addr_t dma_address; - unsigned int length; -}; +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0x1fffffff) diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c index 28ee389e5f5a..b8ec002aef8e 100644 --- a/arch/m32r/mm/fault.c +++ b/arch/m32r/mm/fault.c @@ -188,7 +188,6 @@ good_area: if ((error_code & ACE_INSTRUCTION) && !(vma->vm_flags & VM_EXEC)) goto bad_area; -survive: /* * If for any reason at all we couldn't handle the fault, * make sure we exit gracefully rather than endlessly redo @@ -271,15 +270,10 @@ no_context: */ out_of_memory: up_read(&mm->mmap_sem); - if (is_global_init(tsk)) { - yield(); - down_read(&mm->mmap_sem); - goto survive; - } - printk("VM: killing process %s\n", tsk->comm); - if (error_code & ACE_USERMODE) - do_group_exit(SIGKILL); - goto no_context; + if (!(error_code & ACE_USERMODE)) + goto no_context; + pagefault_out_of_memory(); + return; do_sigbus: up_read(&mm->mmap_sem); diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index b5da298ba61d..2e3737b92ffc 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -7,6 +7,7 @@ config M68K default y select HAVE_AOUT select HAVE_IDE + select GENERIC_ATOMIC64 config MMU bool diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c index d2cc35d98532..b1577f741fa8 100644 --- a/arch/m68k/amiga/config.c +++ b/arch/m68k/amiga/config.c @@ -97,10 +97,6 @@ static void amiga_get_model(char *model); static void amiga_get_hardware_list(struct seq_file *m); /* amiga specific timer functions */ static unsigned long amiga_gettimeoffset(void); -static int a3000_hwclk(int, struct rtc_time *); -static int a2000_hwclk(int, struct rtc_time *); -static int amiga_set_clock_mmss(unsigned long); -static unsigned int amiga_get_ss(void); extern void amiga_mksound(unsigned int count, unsigned int ticks); static void amiga_reset(void); extern void amiga_init_sound(void); @@ -138,10 +134,6 @@ static struct { } }; -static struct resource rtc_resource = { - .start = 0x00dc0000, .end = 0x00dcffff -}; - static struct resource ram_resource[NUM_MEMINFO]; @@ -387,15 +379,6 @@ void __init config_amiga(void) mach_get_model = amiga_get_model; mach_get_hardware_list = amiga_get_hardware_list; mach_gettimeoffset = amiga_gettimeoffset; - if (AMIGAHW_PRESENT(A3000_CLK)) { - mach_hwclk = a3000_hwclk; - rtc_resource.name = "A3000 RTC"; - request_resource(&iomem_resource, &rtc_resource); - } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ { - mach_hwclk = a2000_hwclk; - rtc_resource.name = "A2000 RTC"; - request_resource(&iomem_resource, &rtc_resource); - } /* * default MAX_DMA=0xffffffff on all machines. If we don't do so, the SCSI @@ -404,8 +387,6 @@ void __init config_amiga(void) */ mach_max_dma_address = 0xffffffff; - mach_set_clock_mmss = amiga_set_clock_mmss; - mach_get_ss = amiga_get_ss; mach_reset = amiga_reset; #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) mach_beep = amiga_mksound; @@ -530,161 +511,6 @@ static unsigned long amiga_gettimeoffset(void) return ticks + offset; } -static int a3000_hwclk(int op, struct rtc_time *t) -{ - tod_3000.cntrl1 = TOD3000_CNTRL1_HOLD; - - if (!op) { /* read */ - t->tm_sec = tod_3000.second1 * 10 + tod_3000.second2; - t->tm_min = tod_3000.minute1 * 10 + tod_3000.minute2; - t->tm_hour = tod_3000.hour1 * 10 + tod_3000.hour2; - t->tm_mday = tod_3000.day1 * 10 + tod_3000.day2; - t->tm_wday = tod_3000.weekday; - t->tm_mon = tod_3000.month1 * 10 + tod_3000.month2 - 1; - t->tm_year = tod_3000.year1 * 10 + tod_3000.year2; - if (t->tm_year <= 69) - t->tm_year += 100; - } else { - tod_3000.second1 = t->tm_sec / 10; - tod_3000.second2 = t->tm_sec % 10; - tod_3000.minute1 = t->tm_min / 10; - tod_3000.minute2 = t->tm_min % 10; - tod_3000.hour1 = t->tm_hour / 10; - tod_3000.hour2 = t->tm_hour % 10; - tod_3000.day1 = t->tm_mday / 10; - tod_3000.day2 = t->tm_mday % 10; - if (t->tm_wday != -1) - tod_3000.weekday = t->tm_wday; - tod_3000.month1 = (t->tm_mon + 1) / 10; - tod_3000.month2 = (t->tm_mon + 1) % 10; - if (t->tm_year >= 100) - t->tm_year -= 100; - tod_3000.year1 = t->tm_year / 10; - tod_3000.year2 = t->tm_year % 10; - } - - tod_3000.cntrl1 = TOD3000_CNTRL1_FREE; - - return 0; -} - -static int a2000_hwclk(int op, struct rtc_time *t) -{ - int cnt = 5; - - tod_2000.cntrl1 = TOD2000_CNTRL1_HOLD; - - while ((tod_2000.cntrl1 & TOD2000_CNTRL1_BUSY) && cnt) { - tod_2000.cntrl1 &= ~TOD2000_CNTRL1_HOLD; - udelay(70); - tod_2000.cntrl1 |= TOD2000_CNTRL1_HOLD; - --cnt; - } - - if (!cnt) - printk(KERN_INFO "hwclk: timed out waiting for RTC (0x%x)\n", - tod_2000.cntrl1); - - if (!op) { /* read */ - t->tm_sec = tod_2000.second1 * 10 + tod_2000.second2; - t->tm_min = tod_2000.minute1 * 10 + tod_2000.minute2; - t->tm_hour = (tod_2000.hour1 & 3) * 10 + tod_2000.hour2; - t->tm_mday = tod_2000.day1 * 10 + tod_2000.day2; - t->tm_wday = tod_2000.weekday; - t->tm_mon = tod_2000.month1 * 10 + tod_2000.month2 - 1; - t->tm_year = tod_2000.year1 * 10 + tod_2000.year2; - if (t->tm_year <= 69) - t->tm_year += 100; - - if (!(tod_2000.cntrl3 & TOD2000_CNTRL3_24HMODE)) { - if (!(tod_2000.hour1 & TOD2000_HOUR1_PM) && t->tm_hour == 12) - t->tm_hour = 0; - else if ((tod_2000.hour1 & TOD2000_HOUR1_PM) && t->tm_hour != 12) - t->tm_hour += 12; - } - } else { - tod_2000.second1 = t->tm_sec / 10; - tod_2000.second2 = t->tm_sec % 10; - tod_2000.minute1 = t->tm_min / 10; - tod_2000.minute2 = t->tm_min % 10; - if (tod_2000.cntrl3 & TOD2000_CNTRL3_24HMODE) - tod_2000.hour1 = t->tm_hour / 10; - else if (t->tm_hour >= 12) - tod_2000.hour1 = TOD2000_HOUR1_PM + - (t->tm_hour - 12) / 10; - else - tod_2000.hour1 = t->tm_hour / 10; - tod_2000.hour2 = t->tm_hour % 10; - tod_2000.day1 = t->tm_mday / 10; - tod_2000.day2 = t->tm_mday % 10; - if (t->tm_wday != -1) - tod_2000.weekday = t->tm_wday; - tod_2000.month1 = (t->tm_mon + 1) / 10; - tod_2000.month2 = (t->tm_mon + 1) % 10; - if (t->tm_year >= 100) - t->tm_year -= 100; - tod_2000.year1 = t->tm_year / 10; - tod_2000.year2 = t->tm_year % 10; - } - - tod_2000.cntrl1 &= ~TOD2000_CNTRL1_HOLD; - - return 0; -} - -static int amiga_set_clock_mmss(unsigned long nowtime) -{ - short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; - - if (AMIGAHW_PRESENT(A3000_CLK)) { - tod_3000.cntrl1 = TOD3000_CNTRL1_HOLD; - - tod_3000.second1 = real_seconds / 10; - tod_3000.second2 = real_seconds % 10; - tod_3000.minute1 = real_minutes / 10; - tod_3000.minute2 = real_minutes % 10; - - tod_3000.cntrl1 = TOD3000_CNTRL1_FREE; - } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ { - int cnt = 5; - - tod_2000.cntrl1 |= TOD2000_CNTRL1_HOLD; - - while ((tod_2000.cntrl1 & TOD2000_CNTRL1_BUSY) && cnt) { - tod_2000.cntrl1 &= ~TOD2000_CNTRL1_HOLD; - udelay(70); - tod_2000.cntrl1 |= TOD2000_CNTRL1_HOLD; - --cnt; - } - - if (!cnt) - printk(KERN_INFO "set_clock_mmss: timed out waiting for RTC (0x%x)\n", tod_2000.cntrl1); - - tod_2000.second1 = real_seconds / 10; - tod_2000.second2 = real_seconds % 10; - tod_2000.minute1 = real_minutes / 10; - tod_2000.minute2 = real_minutes % 10; - - tod_2000.cntrl1 &= ~TOD2000_CNTRL1_HOLD; - } - - return 0; -} - -static unsigned int amiga_get_ss(void) -{ - unsigned int s; - - if (AMIGAHW_PRESENT(A3000_CLK)) { - tod_3000.cntrl1 = TOD3000_CNTRL1_HOLD; - s = tod_3000.second1 * 10 + tod_3000.second2; - tod_3000.cntrl1 = TOD3000_CNTRL1_FREE; - } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ { - s = tod_2000.second1 * 10 + tod_2000.second2; - } - return s; -} - static NORET_TYPE void amiga_reset(void) ATTRIB_NORET; diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c index 38f18bf14737..7fd8b41723ea 100644 --- a/arch/m68k/amiga/platform.c +++ b/arch/m68k/amiga/platform.c @@ -11,6 +11,7 @@ #include <linux/zorro.h> #include <asm/amigahw.h> +#include <asm/amigayle.h> #ifdef CONFIG_ZORRO @@ -55,11 +56,77 @@ static int __init amiga_init_bus(void) subsys_initcall(amiga_init_bus); -#endif /* CONFIG_ZORRO */ + +static int z_dev_present(zorro_id id) +{ + unsigned int i; + + for (i = 0; i < zorro_num_autocon; i++) + if (zorro_autocon[i].rom.er_Manufacturer == ZORRO_MANUF(id) && + zorro_autocon[i].rom.er_Product == ZORRO_PROD(id)) + return 1; + + return 0; +} + +#else /* !CONFIG_ZORRO */ + +static inline int z_dev_present(zorro_id id) { return 0; } + +#endif /* !CONFIG_ZORRO */ + + +static const struct resource a3000_scsi_resource __initconst = { + .start = 0xdd0000, + .end = 0xdd00ff, + .flags = IORESOURCE_MEM, +}; + + +static const struct resource a4000t_scsi_resource __initconst = { + .start = 0xdd0000, + .end = 0xdd0fff, + .flags = IORESOURCE_MEM, +}; + + +static const struct resource a1200_ide_resource __initconst = { + .start = 0xda0000, + .end = 0xda1fff, + .flags = IORESOURCE_MEM, +}; + +static const struct gayle_ide_platform_data a1200_ide_pdata __initconst = { + .base = 0xda0000, + .irqport = 0xda9000, + .explicit_ack = 1, +}; + + +static const struct resource a4000_ide_resource __initconst = { + .start = 0xdd2000, + .end = 0xdd3fff, + .flags = IORESOURCE_MEM, +}; + +static const struct gayle_ide_platform_data a4000_ide_pdata __initconst = { + .base = 0xdd2020, + .irqport = 0xdd3020, + .explicit_ack = 0, +}; + + +static const struct resource amiga_rtc_resource __initconst = { + .start = 0x00dc0000, + .end = 0x00dcffff, + .flags = IORESOURCE_MEM, +}; static int __init amiga_init_devices(void) { + struct platform_device *pdev; + if (!MACH_IS_AMIGA) return -ENODEV; @@ -77,6 +144,53 @@ static int __init amiga_init_devices(void) if (AMIGAHW_PRESENT(AMI_FLOPPY)) platform_device_register_simple("amiga-floppy", -1, NULL, 0); + if (AMIGAHW_PRESENT(A3000_SCSI)) + platform_device_register_simple("amiga-a3000-scsi", -1, + &a3000_scsi_resource, 1); + + if (AMIGAHW_PRESENT(A4000_SCSI)) + platform_device_register_simple("amiga-a4000t-scsi", -1, + &a4000t_scsi_resource, 1); + + if (AMIGAHW_PRESENT(A1200_IDE) || + z_dev_present(ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE)) { + pdev = platform_device_register_simple("amiga-gayle-ide", -1, + &a1200_ide_resource, 1); + platform_device_add_data(pdev, &a1200_ide_pdata, + sizeof(a1200_ide_pdata)); + } + + if (AMIGAHW_PRESENT(A4000_IDE)) { + pdev = platform_device_register_simple("amiga-gayle-ide", -1, + &a4000_ide_resource, 1); + platform_device_add_data(pdev, &a4000_ide_pdata, + sizeof(a4000_ide_pdata)); + } + + + /* other I/O hardware */ + if (AMIGAHW_PRESENT(AMI_KEYBOARD)) + platform_device_register_simple("amiga-keyboard", -1, NULL, 0); + + if (AMIGAHW_PRESENT(AMI_MOUSE)) + platform_device_register_simple("amiga-mouse", -1, NULL, 0); + + if (AMIGAHW_PRESENT(AMI_SERIAL)) + platform_device_register_simple("amiga-serial", -1, NULL, 0); + + if (AMIGAHW_PRESENT(AMI_PARALLEL)) + platform_device_register_simple("amiga-parallel", -1, NULL, 0); + + + /* real time clocks */ + if (AMIGAHW_PRESENT(A2000_CLK)) + platform_device_register_simple("rtc-msm6242", -1, + &amiga_rtc_resource, 1); + + if (AMIGAHW_PRESENT(A3000_CLK)) + platform_device_register_simple("rtc-rp5c01", -1, + &amiga_rtc_resource, 1); + return 0; } diff --git a/arch/m68k/include/asm/amigayle.h b/arch/m68k/include/asm/amigayle.h index bb5a6aa329f3..a01453d9c231 100644 --- a/arch/m68k/include/asm/amigayle.h +++ b/arch/m68k/include/asm/amigayle.h @@ -104,4 +104,10 @@ struct GAYLE { #define GAYLE_CFG_250NS 0x00 #define GAYLE_CFG_720NS 0x0c +struct gayle_ide_platform_data { + unsigned long base; + unsigned long irqport; + int explicit_ack; /* A1200 IDE needs explicit ack */ +}; + #endif /* asm-m68k/amigayle.h */ diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index 8d29145ebb27..eab36dcacf6c 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -3,3 +3,5 @@ #else #include "atomic_mm.h" #endif + +#include <asm-generic/atomic64.h> diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index fed3fd30de7e..ecafbe1718c3 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -8,4 +8,6 @@ #define L1_CACHE_SHIFT 4 #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + #endif diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index ed2b69b96805..db824a4b136e 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -113,6 +113,7 @@ #define MCF_GPIO_PAR_UART (0xA4036) #define MCF_GPIO_PAR_FECI2C (0xA4033) +#define MCF_GPIO_PAR_QSPI (0xA4034) #define MCF_GPIO_PAR_FEC (0xA4038) #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index a34894cf8e6f..e8d06b24a48e 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -127,5 +127,10 @@ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE +/* + * Pin Assignment +*/ +#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) +#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) /****************************************************************************/ #endif /* m523xsim_h */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 14bce877ed88..79b7b402f3c9 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -69,10 +69,12 @@ #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ +#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ /* * Define system peripheral IRQ usage. */ +#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 453356d72d80..1feb46f108ce 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -31,6 +31,7 @@ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ #define MCFINT_UART1 14 /* Interrupt number for UART1 */ #define MCFINT_UART2 15 /* Interrupt number for UART2 */ +#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ /* @@ -120,6 +121,9 @@ #define MCFGPIO_PIN_MAX 100 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE + +#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) +#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) #endif #ifdef CONFIG_M5275 @@ -212,6 +216,8 @@ #define MCFGPIO_PIN_MAX 148 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE + +#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) #endif /* @@ -223,6 +229,7 @@ #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) + /* * GPIO pins setups to enable the UARTs. */ diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index e2ad1f42b657..891cbedad972 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -29,6 +29,7 @@ #define MCFINT_VECBASE 64 /* Vector base number */ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ /* @@ -249,70 +250,4 @@ #define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) Module -* -*********************************************************************/ -/* Derek - 21 Feb 2005 */ -/* change to the format used in I2C */ -/* Read/Write access macros for general use */ -#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 -#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 -#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 -#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C -#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 -#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 -#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 - -/* Bit level definitions and macros */ -#define MCF5282_QSPI_QMR_MSTR (0x8000) -#define MCF5282_QSPI_QMR_DOHIE (0x4000) -#define MCF5282_QSPI_QMR_BITS_16 (0x0000) -#define MCF5282_QSPI_QMR_BITS_8 (0x2000) -#define MCF5282_QSPI_QMR_BITS_9 (0x2400) -#define MCF5282_QSPI_QMR_BITS_10 (0x2800) -#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) -#define MCF5282_QSPI_QMR_BITS_12 (0x3000) -#define MCF5282_QSPI_QMR_BITS_13 (0x3400) -#define MCF5282_QSPI_QMR_BITS_14 (0x3800) -#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) -#define MCF5282_QSPI_QMR_CPOL (0x0200) -#define MCF5282_QSPI_QMR_CPHA (0x0100) -#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QDLYR_SPE (0x80) -#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QWR_HALT (0x8000) -#define MCF5282_QSPI_QWR_WREN (0x4000) -#define MCF5282_QSPI_QWR_WRTO (0x2000) -#define MCF5282_QSPI_QWR_CSIV (0x1000) -#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) -#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) - -#define MCF5282_QSPI_QIR_WCEFB (0x8000) -#define MCF5282_QSPI_QIR_ABRTB (0x4000) -#define MCF5282_QSPI_QIR_ABRTL (0x1000) -#define MCF5282_QSPI_QIR_WCEFE (0x0800) -#define MCF5282_QSPI_QIR_ABRTE (0x0400) -#define MCF5282_QSPI_QIR_SPIFE (0x0100) -#define MCF5282_QSPI_QIR_WCEF (0x0008) -#define MCF5282_QSPI_QIR_ABRT (0x0004) -#define MCF5282_QSPI_QIR_SPIF (0x0001) - -#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) - -#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) -#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) -#define MCF5282_QSPI_QCR_CONT (0x8000) -#define MCF5282_QSPI_QCR_BITSE (0x4000) -#define MCF5282_QSPI_QCR_DT (0x2000) -#define MCF5282_QSPI_QCR_DSCK (0x1000) -#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) - -/****************************************************************************/ #endif /* m528xsim_h */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 36bf15aec9ae..c4bf1c81e3cf 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -17,6 +17,7 @@ #define MCFINT_UART0 26 /* Interrupt number for UART0 */ #define MCFINT_UART1 27 /* Interrupt number for UART1 */ #define MCFINT_UART2 28 /* Interrupt number for UART2 */ +#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCF_WTM_WCR MCF_REG16(0xFC098000) diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h new file mode 100644 index 000000000000..39d90d51111d --- /dev/null +++ b/arch/m68k/include/asm/mcfqspi.h @@ -0,0 +1,64 @@ +/* + * Definitions for Freescale Coldfire QSPI module + * + * Copyright 2010 Steven King <sfking@fdwdc.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * +*/ + +#ifndef mcfqspi_h +#define mcfqspi_h + +#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) +#elif defined(CONFIG_M5249) +#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) +#elif defined(CONFIG_M520x) || defined(CONFIG_M532x) +#define MCFQSPI_IOBASE 0xFC058000 +#endif +#define MCFQSPI_IOSIZE 0x40 + +/** + * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver + * @setup: setup the control; allocate gpio's, etc. May be NULL. + * @teardown: finish with the control; free gpio's, etc. May be NULL. + * @select: output the signals to select the device. Can not be NULL. + * @deselect: output the signals to deselect the device. Can not be NULL. + * + * The QSPI module has 4 hardware chip selects. We don't use them. Instead + * platforms are required to supply a mcfqspi_cs_control as a part of the + * platform data for each QSPI master controller. Only the select and + * deselect functions are required. +*/ +struct mcfqspi_cs_control { + int (*setup)(struct mcfqspi_cs_control *); + void (*teardown)(struct mcfqspi_cs_control *); + void (*select)(struct mcfqspi_cs_control *, u8, bool); + void (*deselect)(struct mcfqspi_cs_control *, u8, bool); +}; + +/** + * struct mcfqspi_platform_data - platform data for the coldfire qspi driver + * @bus_num: board specific identifier for this qspi driver. + * @num_chipselects: number of chip selects supported by this qspi driver. + * @cs_control: platform dependent chip select control. +*/ +struct mcfqspi_platform_data { + s16 bus_num; + u16 num_chipselect; + struct mcfqspi_cs_control *cs_control; +}; + +#endif /* mcfqspi_h */ diff --git a/arch/m68k/include/asm/mcfsmc.h b/arch/m68k/include/asm/mcfsmc.h deleted file mode 100644 index 527bea5d6788..000000000000 --- a/arch/m68k/include/asm/mcfsmc.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************/ - -/* - * mcfsmc.h -- SMC ethernet support for ColdFire environments. - * - * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfsmc_h -#define mcfsmc_h -/****************************************************************************/ - -/* - * None of the current ColdFire targets that use the SMC91x111 - * allow 8 bit accesses. So this code is 16bit access only. - */ - - -#undef outb -#undef inb -#undef outw -#undef outwd -#undef inw -#undef outl -#undef inl - -#undef outsb -#undef outsw -#undef outsl -#undef insb -#undef insw -#undef insl - -/* - * Re-defines for ColdFire environment... The SMC part is - * mapped into memory space, so remap the PC-style in/out - * routines to handle that. - */ -#define outb smc_outb -#define inb smc_inb -#define outw smc_outw -#define outwd smc_outwd -#define inw smc_inw -#define outl smc_outl -#define inl smc_inl - -#define outsb smc_outsb -#define outsw smc_outsw -#define outsl smc_outsl -#define insb smc_insb -#define insw smc_insw -#define insl smc_insl - - -static inline int smc_inb(unsigned int addr) -{ - register unsigned short w; - w = *((volatile unsigned short *) (addr & ~0x1)); - return(((addr & 0x1) ? w : (w >> 8)) & 0xff); -} - -static inline void smc_outw(unsigned int val, unsigned int addr) -{ - *((volatile unsigned short *) addr) = (val << 8) | (val >> 8); -} - -static inline int smc_inw(unsigned int addr) -{ - register unsigned short w; - w = *((volatile unsigned short *) addr); - return(((w << 8) | (w >> 8)) & 0xffff); -} - -static inline void smc_outl(unsigned long val, unsigned int addr) -{ - *((volatile unsigned long *) addr) = - ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) | - ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff); -} - -static inline void smc_outwd(unsigned int val, unsigned int addr) -{ - *((volatile unsigned short *) addr) = val; -} - - -/* - * The rep* functions are used to feed the data port with - * raw data. So we do not byte swap them when copying. - */ - -static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - - /* Copy as words for as long as possible */ - for (ebuf = buf + (len >> 1); (buf < ebuf); ) - *buf++ = *rp; - - /* Lastly, handle left over byte */ - if (len & 0x1) - *((unsigned char *) buf) = (*rp >> 8) & 0xff; -} - -static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *buf++ = *rp; -} - -static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned long *rp; - unsigned long *buf, *ebuf; - - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *buf++ = *rp; -} - -static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *rp = *buf++; -} - -static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned long *rp; - unsigned long *buf, *ebuf; - - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *rp = *buf++; -} - - -#ifdef CONFIG_NETtel -/* - * Re-map the address space of at least one of the SMC ethernet - * parts. Both parts power up decoding the same address, so we - * need to move one of them first, before doing enything else. - * - * We also increase the number of wait states for this part by one. - */ - -void smc_remap(unsigned int ioaddr) -{ - static int once = 0; - extern unsigned short ppdata; - if (once++ == 0) { - *((volatile unsigned short *)MCFSIM_PADDR) = 0x00ec; - ppdata |= 0x0080; - *((volatile unsigned short *)MCFSIM_PADAT) = ppdata; - outw(0x0001, ioaddr + BANK_SELECT); - outw(0x0001, ioaddr + BANK_SELECT); - outw(0x0067, ioaddr + BASE); - - ppdata &= ~0x0080; - *((volatile unsigned short *)MCFSIM_PADAT) = ppdata; - } - - *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180; -} - -#endif - -/****************************************************************************/ -#endif /* mcfsmc_h */ diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index cbd3d4751dd2..7a6a7590cc02 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -44,11 +44,15 @@ static inline void wrusp(unsigned long usp) * User space process size: 3.75GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ +#ifdef CONFIG_MMU #ifndef CONFIG_SUN3 #define TASK_SIZE (0xF0000000UL) #else #define TASK_SIZE (0x0E000000UL) #endif +#else +#define TASK_SIZE (0xFFFFFFFFUL) +#endif #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE diff --git a/arch/m68k/include/asm/scatterlist.h b/arch/m68k/include/asm/scatterlist.h index e27ad902b1cf..175da06c6b95 100644 --- a/arch/m68k/include/asm/scatterlist.h +++ b/arch/m68k/include/asm/scatterlist.h @@ -1,23 +1,9 @@ #ifndef _M68K_SCATTERLIST_H #define _M68K_SCATTERLIST_H -#include <linux/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - unsigned int length; - - dma_addr_t dma_address; /* A place to hang host-specific addresses at. */ -}; +#include <asm-generic/scatterlist.h> /* This is bogus and should go away. */ #define ISA_DMA_THRESHOLD (0x00ffffff) -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - #endif /* !(_M68K_SCATTERLIST_H) */ diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 064f5913db1a..efeb6033fc17 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -566,7 +566,7 @@ config RAMBASE processor address space. config RAMSIZE - hex "Size of RAM (in bytes)" + hex "Size of RAM (in bytes), or 0 for automatic" default "0x400000" help Define the size of the system RAM. If you select 0 then the diff --git a/arch/m68knommu/kernel/vmlinux.lds.S b/arch/m68knommu/kernel/vmlinux.lds.S index 9f1784f586b9..a91b2713451d 100644 --- a/arch/m68knommu/kernel/vmlinux.lds.S +++ b/arch/m68knommu/kernel/vmlinux.lds.S @@ -57,7 +57,7 @@ SECTIONS { .romvec : { __rom_start = . ; _romvec = .; - *(.data.initvect) + *(.data..initvect) } > romvec #endif @@ -68,7 +68,7 @@ SECTIONS { TEXT_TEXT SCHED_TEXT LOCK_TEXT - *(.text.lock) + *(.text..lock) . = ALIGN(16); /* Exception table */ __start___ex_table = .; diff --git a/arch/m68knommu/mm/fault.c b/arch/m68knommu/mm/fault.c index 6f6673cb5829..bc05cf74d9c0 100644 --- a/arch/m68knommu/mm/fault.c +++ b/arch/m68knommu/mm/fault.c @@ -2,7 +2,7 @@ * linux/arch/m68knommu/mm/fault.c * * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, - * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) + * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) * * Based on: * @@ -36,7 +36,7 @@ asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, unsigned long error_code) { #ifdef DEBUG - printk (KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n", + printk(KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n", regs->sr, regs->pc, address, error_code); #endif @@ -44,11 +44,11 @@ asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, * Oops. The kernel tried to access some bad page. We'll have to * terminate things with extreme prejudice. */ - if ((unsigned long) address < PAGE_SIZE) { + if ((unsigned long) address < PAGE_SIZE) printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); - } else + else printk(KERN_ALERT "Unable to handle kernel access"); - printk(KERN_ALERT " at virtual address %08lx\n",address); + printk(KERN_ALERT " at virtual address %08lx\n", address); die_if_kernel("Oops", regs, error_code); do_exit(SIGKILL); diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c index 92614de42cd3..71d2ba474c63 100644 --- a/arch/m68knommu/platform/520x/config.c +++ b/arch/m68knommu/platform/520x/config.c @@ -15,10 +15,13 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -74,9 +77,152 @@ static struct platform_device m520x_fec = { .resource = m520x_fec_resources, }; +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m520x_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINT_VECBASE + MCFINT_QSPI, + .end = MCFINT_VECBASE + MCFINT_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#define MCFQSPI_CS0 62 +#define MCFQSPI_CS1 63 +#define MCFQSPI_CS2 44 + +static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + return 0; + +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m520x_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, cs_high); + break; + } +} + +static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, !cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, !cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, !cs_high); + break; + } +} + +static struct mcfqspi_cs_control m520x_cs_control = { + .setup = m520x_cs_setup, + .teardown = m520x_cs_teardown, + .select = m520x_cs_select, + .deselect = m520x_cs_deselect, +}; + +static struct mcfqspi_platform_data m520x_qspi_data = { + .bus_num = 0, + .num_chipselect = 3, + .cs_control = &m520x_cs_control, +}; + +static struct platform_device m520x_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m520x_qspi_resources), + .resource = m520x_qspi_resources, + .dev.platform_data = &m520x_qspi_data, +}; + +static void __init m520x_qspi_init(void) +{ + u16 par; + /* setup Port QS for QSPI with gpio CS control */ + writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI); + /* make U1CTS and U2RTS gpio for cs_control */ + par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + par &= 0x00ff; + writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ + + static struct platform_device *m520x_devices[] __initdata = { &m520x_uart, &m520x_fec, +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m520x_qspi, +#endif }; /***************************************************************************/ @@ -147,6 +293,9 @@ void __init config_BSP(char *commandp, int size) mach_reset = m520x_cpu_reset; m520x_uarts_init(); m520x_fec_init(); +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m520x_qspi_init(); +#endif } /***************************************************************************/ diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c index 6ba84f2aa397..8980f6d7715a 100644 --- a/arch/m68knommu/platform/523x/config.c +++ b/arch/m68knommu/platform/523x/config.c @@ -16,10 +16,13 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -75,9 +78,173 @@ static struct platform_device m523x_fec = { .resource = m523x_fec_resources, }; +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m523x_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINT_VECBASE + MCFINT_QSPI, + .end = MCFINT_VECBASE + MCFINT_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#define MCFQSPI_CS0 91 +#define MCFQSPI_CS1 92 +#define MCFQSPI_CS2 103 +#define MCFQSPI_CS3 99 + +static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); + goto fail3; + } + status = gpio_direction_output(MCFQSPI_CS3, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); + goto fail4; + } + + return 0; + +fail4: + gpio_free(MCFQSPI_CS3); +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS3); + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m523x_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, cs_high); + break; + } +} + +static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, !cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, !cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, !cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, !cs_high); + break; + } +} + +static struct mcfqspi_cs_control m523x_cs_control = { + .setup = m523x_cs_setup, + .teardown = m523x_cs_teardown, + .select = m523x_cs_select, + .deselect = m523x_cs_deselect, +}; + +static struct mcfqspi_platform_data m523x_qspi_data = { + .bus_num = 0, + .num_chipselect = 4, + .cs_control = &m523x_cs_control, +}; + +static struct platform_device m523x_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m523x_qspi_resources), + .resource = m523x_qspi_resources, + .dev.platform_data = &m523x_qspi_data, +}; + +static void __init m523x_qspi_init(void) +{ + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ + static struct platform_device *m523x_devices[] __initdata = { &m523x_uart, &m523x_fec, +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m523x_qspi, +#endif }; /***************************************************************************/ @@ -114,6 +281,9 @@ void __init config_BSP(char *commandp, int size) static int __init init_BSP(void) { m523x_fec_init(); +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m523x_qspi_init(); +#endif platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices)); return 0; } diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c index 646f5ba462fc..ceb31e5744a6 100644 --- a/arch/m68knommu/platform/5249/config.c +++ b/arch/m68knommu/platform/5249/config.c @@ -12,10 +12,13 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -37,8 +40,196 @@ static struct platform_device m5249_uart = { .dev.platform_data = m5249_uart_platform, }; +#ifdef CONFIG_M5249C3 + +static struct resource m5249_smc91x_resources[] = { + { + .start = 0xe0000300, + .end = 0xe0000300 + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINTC2_GPIOIRQ6, + .end = MCFINTC2_GPIOIRQ6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device m5249_smc91x = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(m5249_smc91x_resources), + .resource = m5249_smc91x_resources, +}; + +#endif /* CONFIG_M5249C3 */ + +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m5249_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_QSPI, + .end = MCF_IRQ_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#define MCFQSPI_CS0 29 +#define MCFQSPI_CS1 24 +#define MCFQSPI_CS2 21 +#define MCFQSPI_CS3 22 + +static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); + goto fail3; + } + status = gpio_direction_output(MCFQSPI_CS3, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); + goto fail4; + } + + return 0; + +fail4: + gpio_free(MCFQSPI_CS3); +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS3); + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m5249_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, cs_high); + break; + } +} + +static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, !cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, !cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, !cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, !cs_high); + break; + } +} + +static struct mcfqspi_cs_control m5249_cs_control = { + .setup = m5249_cs_setup, + .teardown = m5249_cs_teardown, + .select = m5249_cs_select, + .deselect = m5249_cs_deselect, +}; + +static struct mcfqspi_platform_data m5249_qspi_data = { + .bus_num = 0, + .num_chipselect = 4, + .cs_control = &m5249_cs_control, +}; + +static struct platform_device m5249_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m5249_qspi_resources), + .resource = m5249_qspi_resources, + .dev.platform_data = &m5249_qspi_data, +}; + +static void __init m5249_qspi_init(void) +{ + /* QSPI irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCF_MBAR + MCFSIM_QSPIICR); + mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ + + static struct platform_device *m5249_devices[] __initdata = { &m5249_uart, +#ifdef CONFIG_M5249C3 + &m5249_smc91x, +#endif +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m5249_qspi, +#endif }; /***************************************************************************/ @@ -67,6 +258,24 @@ static void __init m5249_uarts_init(void) /***************************************************************************/ +#ifdef CONFIG_M5249C3 + +static void __init m5249_smc91x_init(void) +{ + u32 gpio; + + /* Set the GPIO line as interrupt source for smc91x device */ + gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + + gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); + writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); +} + +#endif /* CONFIG_M5249C3 */ + +/***************************************************************************/ + static void __init m5249_timers_init(void) { /* Timer1 is always used as system timer */ @@ -100,6 +309,12 @@ void __init config_BSP(char *commandp, int size) mach_reset = m5249_cpu_reset; m5249_timers_init(); m5249_uarts_init(); +#ifdef CONFIG_M5249C3 + m5249_smc91x_init(); +#endif +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m5249_qspi_init(); +#endif } /***************************************************************************/ diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c index fa51be172830..3d9c35c98b98 100644 --- a/arch/m68knommu/platform/527x/config.c +++ b/arch/m68knommu/platform/527x/config.c @@ -16,10 +16,13 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -106,12 +109,188 @@ static struct platform_device m527x_fec[] = { }, }; +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m527x_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINT_VECBASE + MCFINT_QSPI, + .end = MCFINT_VECBASE + MCFINT_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#if defined(CONFIG_M5271) +#define MCFQSPI_CS0 91 +#define MCFQSPI_CS1 92 +#define MCFQSPI_CS2 99 +#define MCFQSPI_CS3 103 +#elif defined(CONFIG_M5275) +#define MCFQSPI_CS0 59 +#define MCFQSPI_CS1 60 +#define MCFQSPI_CS2 61 +#define MCFQSPI_CS3 62 +#endif + +static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); + goto fail3; + } + status = gpio_direction_output(MCFQSPI_CS3, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); + goto fail4; + } + + return 0; + +fail4: + gpio_free(MCFQSPI_CS3); +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS3); + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m527x_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, cs_high); + break; + } +} + +static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, !cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, !cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, !cs_high); + break; + case 3: + gpio_set_value(MCFQSPI_CS3, !cs_high); + break; + } +} + +static struct mcfqspi_cs_control m527x_cs_control = { + .setup = m527x_cs_setup, + .teardown = m527x_cs_teardown, + .select = m527x_cs_select, + .deselect = m527x_cs_deselect, +}; + +static struct mcfqspi_platform_data m527x_qspi_data = { + .bus_num = 0, + .num_chipselect = 4, + .cs_control = &m527x_cs_control, +}; + +static struct platform_device m527x_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m527x_qspi_resources), + .resource = m527x_qspi_resources, + .dev.platform_data = &m527x_qspi_data, +}; + +static void __init m527x_qspi_init(void) +{ +#if defined(CONFIG_M5271) + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +#elif defined(CONFIG_M5275) + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x003e, MCFGPIO_PAR_QSPI); +#endif +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ + static struct platform_device *m527x_devices[] __initdata = { &m527x_uart, &m527x_fec[0], #ifdef CONFIG_FEC2 &m527x_fec[1], #endif +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m527x_qspi, +#endif }; /***************************************************************************/ @@ -187,6 +366,9 @@ void __init config_BSP(char *commandp, int size) mach_reset = m527x_cpu_reset; m527x_uarts_init(); m527x_fec_init(); +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m527x_qspi_init(); +#endif } /***************************************************************************/ diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c index 6e608d1836f1..76b743343bfa 100644 --- a/arch/m68knommu/platform/528x/config.c +++ b/arch/m68knommu/platform/528x/config.c @@ -17,10 +17,13 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -76,10 +79,141 @@ static struct platform_device m528x_fec = { .resource = m528x_fec_resources, }; +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m528x_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINT_VECBASE + MCFINT_QSPI, + .end = MCFINT_VECBASE + MCFINT_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#define MCFQSPI_CS0 147 +#define MCFQSPI_CS1 148 +#define MCFQSPI_CS2 149 +#define MCFQSPI_CS3 150 + +static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); + goto fail3; + } + status = gpio_direction_output(MCFQSPI_CS3, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); + goto fail4; + } + + return 0; + +fail4: + gpio_free(MCFQSPI_CS3); +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS3); + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m528x_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high); +} + +static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high); +} + +static struct mcfqspi_cs_control m528x_cs_control = { + .setup = m528x_cs_setup, + .teardown = m528x_cs_teardown, + .select = m528x_cs_select, + .deselect = m528x_cs_deselect, +}; + +static struct mcfqspi_platform_data m528x_qspi_data = { + .bus_num = 0, + .num_chipselect = 4, + .cs_control = &m528x_cs_control, +}; + +static struct platform_device m528x_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m528x_qspi_resources), + .resource = m528x_qspi_resources, + .dev.platform_data = &m528x_qspi_data, +}; + +static void __init m528x_qspi_init(void) +{ + /* setup Port QS for QSPI with gpio CS control */ + __raw_writeb(0x07, MCFGPIO_PQSPAR); +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ static struct platform_device *m528x_devices[] __initdata = { &m528x_uart, &m528x_fec, +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m528x_qspi, +#endif }; /***************************************************************************/ @@ -174,6 +308,9 @@ static int __init init_BSP(void) mach_reset = m528x_cpu_reset; m528x_uarts_init(); m528x_fec_init(); +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m528x_qspi_init(); +#endif platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices)); return 0; } diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile index 667db6598451..6de526976828 100644 --- a/arch/m68knommu/platform/5307/Makefile +++ b/arch/m68knommu/platform/5307/Makefile @@ -14,5 +14,7 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 -obj-y += config.o gpio.o +obj-y += config.o gpio.o +obj-$(CONFIG_NETtel) += nettel.o +obj-$(CONFIG_CLEOPATRA) += nettel.o diff --git a/arch/m68knommu/platform/5307/nettel.c b/arch/m68knommu/platform/5307/nettel.c new file mode 100644 index 000000000000..e925ea4602f8 --- /dev/null +++ b/arch/m68knommu/platform/5307/nettel.c @@ -0,0 +1,153 @@ +/***************************************************************************/ + +/* + * nettel.c -- startup code support for the NETtel boards + * + * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> +#include <asm/nettel.h> + +/***************************************************************************/ + +/* + * Define the IO and interrupt resources of the 2 SMC9196 interfaces. + */ +#define NETTEL_SMC0_ADDR 0x30600300 +#define NETTEL_SMC0_IRQ 29 + +#define NETTEL_SMC1_ADDR 0x30600000 +#define NETTEL_SMC1_IRQ 27 + +/* + * We need some access into the SMC9196 registers. Define those registers + * we will need here (including the smc91x.h doesn't seem to give us these + * in a simple form). + */ +#define SMC91xx_BANKSELECT 14 +#define SMC91xx_BASEADDR 2 +#define SMC91xx_BASEMAC 4 + +/***************************************************************************/ + +static struct resource nettel_smc91x_0_resources[] = { + { + .start = NETTEL_SMC0_ADDR, + .end = NETTEL_SMC0_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, + { + .start = NETTEL_SMC0_IRQ, + .end = NETTEL_SMC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource nettel_smc91x_1_resources[] = { + { + .start = NETTEL_SMC1_ADDR, + .end = NETTEL_SMC1_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, + { + .start = NETTEL_SMC1_IRQ, + .end = NETTEL_SMC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device nettel_smc91x[] = { + { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources), + .resource = nettel_smc91x_0_resources, + }, + { + .name = "smc91x", + .id = 1, + .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources), + .resource = nettel_smc91x_1_resources, + }, +}; + +static struct platform_device *nettel_devices[] __initdata = { + &nettel_smc91x[0], + &nettel_smc91x[1], +}; + +/***************************************************************************/ + +static u8 nettel_macdefault[] __initdata = { + 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01, +}; + +/* + * Set flash contained MAC address into SMC9196 core. Make sure the flash + * MAC address is sane, and not an empty flash. If no good use the Moreton + * Bay default MAC address instead. + */ + +static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr) +{ + u16 *macp; + + macp = (u16 *) flashaddr; + if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff)) + macp = (u16 *) &nettel_macdefault[0]; + + writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); + writew(macp[0], ioaddr + SMC91xx_BASEMAC); + writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); + writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); +} + +/***************************************************************************/ + +/* + * Re-map the address space of at least one of the SMC ethernet + * parts. Both parts power up decoding the same address, so we + * need to move one of them first, before doing anything else. + */ + +static void __init nettel_smc91x_init(void) +{ + writew(0x00ec, MCF_MBAR + MCFSIM_PADDR); + mcf_setppdata(0, 0x0080); + writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); + writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); + mcf_setppdata(0x0080, 0); + + /* Set correct chip select timing for SMC9196 accesses */ + writew(0x1180, MCF_MBAR + MCFSIM_CSCR3); + + /* Set the SMC interrupts to be auto-vectored */ + mcf_autovector(NETTEL_SMC0_IRQ); + mcf_autovector(NETTEL_SMC1_IRQ); + + /* Set MAC addresses from flash for both interfaces */ + nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000); + nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006); +} + +/***************************************************************************/ + +static int __init init_nettel(void) +{ + nettel_smc91x_init(); + platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices)); + return 0; +} + +arch_initcall(init_nettel); + +/***************************************************************************/ diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c index d632948e64e5..ca51323f957b 100644 --- a/arch/m68knommu/platform/532x/config.c +++ b/arch/m68knommu/platform/532x/config.c @@ -21,12 +21,15 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/machdep.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/mcfuart.h> #include <asm/mcfdma.h> #include <asm/mcfwdebug.h> +#include <asm/mcfqspi.h> /***************************************************************************/ @@ -82,9 +85,127 @@ static struct platform_device m532x_fec = { .resource = m532x_fec_resources, }; +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) +static struct resource m532x_qspi_resources[] = { + { + .start = MCFQSPI_IOBASE, + .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINT_VECBASE + MCFINT_QSPI, + .end = MCFINT_VECBASE + MCFINT_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +#define MCFQSPI_CS0 84 +#define MCFQSPI_CS1 85 +#define MCFQSPI_CS2 86 + +static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + + return 0; + +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void m532x_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high); +} + +static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high); +} + +static struct mcfqspi_cs_control m532x_cs_control = { + .setup = m532x_cs_setup, + .teardown = m532x_cs_teardown, + .select = m532x_cs_select, + .deselect = m532x_cs_deselect, +}; + +static struct mcfqspi_platform_data m532x_qspi_data = { + .bus_num = 0, + .num_chipselect = 3, + .cs_control = &m532x_cs_control, +}; + +static struct platform_device m532x_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(m532x_qspi_resources), + .resource = m532x_qspi_resources, + .dev.platform_data = &m532x_qspi_data, +}; + +static void __init m532x_qspi_init(void) +{ + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x01f0, MCF_GPIO_PAR_QSPI); +} +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ + + static struct platform_device *m532x_devices[] __initdata = { &m532x_uart, &m532x_fec, +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + &m532x_qspi, +#endif }; /***************************************************************************/ @@ -158,6 +279,9 @@ static int __init init_BSP(void) { m532x_uarts_init(); m532x_fec_init(); +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) + m532x_qspi_init(); +#endif platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices)); return 0; } diff --git a/arch/m68knommu/platform/68360/commproc.c b/arch/m68knommu/platform/68360/commproc.c index 6acb8d294cb6..f27e688c404e 100644 --- a/arch/m68knommu/platform/68360/commproc.c +++ b/arch/m68knommu/platform/68360/commproc.c @@ -110,7 +110,7 @@ void m360_cpm_reset() /* pte = find_pte(&init_mm, host_page_addr); */ /* pte_val(*pte) |= _PAGE_NO_CACHE; */ /* flush_tlb_page(current->mm->mmap, host_buffer); */ - + /* Tell everyone where the comm processor resides. */ /* cpmp = (cpm360_t *)commproc; */ @@ -191,7 +191,7 @@ cpm_interrupt(int irq, void * dev, struct pt_regs * regs) */ ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec); #endif - + } /* The CPM can generate the error interrupt when there is a race condition diff --git a/arch/m68knommu/platform/68360/head-ram.S b/arch/m68knommu/platform/68360/head-ram.S index 2ef06242398b..8eb94fb6b971 100644 --- a/arch/m68knommu/platform/68360/head-ram.S +++ b/arch/m68knommu/platform/68360/head-ram.S @@ -280,7 +280,7 @@ _dprbase: * and then overwritten as needed. */ -.section ".data.initvect","awx" +.section ".data..initvect","awx" .long RAMEND /* Reset: Initial Stack Pointer - 0. */ .long _start /* Reset: Initial Program Counter - 1. */ .long buserr /* Bus Error - 2. */ diff --git a/arch/m68knommu/platform/68360/head-rom.S b/arch/m68knommu/platform/68360/head-rom.S index 62ecf4144b3b..97510e55b802 100644 --- a/arch/m68knommu/platform/68360/head-rom.S +++ b/arch/m68knommu/platform/68360/head-rom.S @@ -291,7 +291,7 @@ _dprbase: * and then overwritten as needed. */ -.section ".data.initvect","awx" +.section ".data..initvect","awx" .long RAMEND /* Reset: Initial Stack Pointer - 0. */ .long _start /* Reset: Initial Program Counter - 1. */ .long buserr /* Bus Error - 2. */ diff --git a/arch/microblaze/include/asm/device.h b/arch/microblaze/include/asm/device.h index 402b46e630f6..123b2fe72d01 100644 --- a/arch/microblaze/include/asm/device.h +++ b/arch/microblaze/include/asm/device.h @@ -12,29 +12,15 @@ struct device_node; struct dev_archdata { - /* Optional pointer to an OF device node */ - struct device_node *of_node; - /* DMA operations on that device */ struct dma_map_ops *dma_ops; void *dma_data; }; struct pdev_archdata { + u64 dma_mask; }; -static inline void dev_archdata_set_node(struct dev_archdata *ad, - struct device_node *np) -{ - ad->of_node = np; -} - -static inline struct device_node * -dev_archdata_get_node(const struct dev_archdata *ad) -{ - return ad->of_node; -} - #endif /* _ASM_MICROBLAZE_DEVICE_H */ diff --git a/arch/microblaze/include/asm/of_device.h b/arch/microblaze/include/asm/of_device.h index ba917cfaefe6..73cb98040982 100644 --- a/arch/microblaze/include/asm/of_device.h +++ b/arch/microblaze/include/asm/of_device.h @@ -21,9 +21,8 @@ * probed using OF properties. */ struct of_device { - struct device_node *node; /* to be obsoleted */ - u64 dma_mask; /* DMA mask */ struct device dev; /* Generic device interface */ + struct pdev_archdata archdata; }; extern ssize_t of_device_get_modalias(struct of_device *ofdev, diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h index de493f86d28f..464ff32bee3d 100644 --- a/arch/microblaze/include/asm/page.h +++ b/arch/microblaze/include/asm/page.h @@ -34,6 +34,8 @@ /* MS be sure that SLAB allocates aligned objects */ #define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES + #define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1))) #define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1))) diff --git a/arch/microblaze/include/asm/scatterlist.h b/arch/microblaze/include/asm/scatterlist.h index 35d786fe93ae..dc4a8900cc80 100644 --- a/arch/microblaze/include/asm/scatterlist.h +++ b/arch/microblaze/include/asm/scatterlist.h @@ -1 +1,3 @@ #include <asm-generic/scatterlist.h> + +#define ISA_DMA_THRESHOLD (~0UL) diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c index 9dcd90b5df55..79c74659f204 100644 --- a/arch/microblaze/kernel/dma.c +++ b/arch/microblaze/kernel/dma.c @@ -90,7 +90,6 @@ static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, /* FIXME this part of code is untested */ for_each_sg(sgl, sg, nents, i) { sg->dma_address = sg_phys(sg) + get_dma_direct_offset(dev); - sg->dma_length = sg->length; __dma_sync_page(page_to_phys(sg_page(sg)), sg->offset, sg->length, direction); } diff --git a/arch/microblaze/kernel/of_device.c b/arch/microblaze/kernel/of_device.c index 9a0f7632c47c..b372787886ed 100644 --- a/arch/microblaze/kernel/of_device.c +++ b/arch/microblaze/kernel/of_device.c @@ -12,7 +12,7 @@ void of_device_make_bus_id(struct of_device *dev) { static atomic_t bus_no_reg_magic; - struct device_node *node = dev->node; + struct device_node *node = dev->dev.of_node; const u32 *reg; u64 addr; int magic; @@ -49,11 +49,10 @@ struct of_device *of_device_alloc(struct device_node *np, if (!dev) return NULL; - dev->node = of_node_get(np); - dev->dev.dma_mask = &dev->dma_mask; + dev->dev.of_node = of_node_get(np); + dev->dev.dma_mask = &dev->archdata.dma_mask; dev->dev.parent = parent; dev->dev.release = of_release_dev; - dev->dev.archdata.of_node = np; if (bus_id) dev_set_name(&dev->dev, bus_id); @@ -75,17 +74,17 @@ int of_device_uevent(struct device *dev, struct kobj_uevent_env *env) ofdev = to_of_device(dev); - if (add_uevent_var(env, "OF_NAME=%s", ofdev->node->name)) + if (add_uevent_var(env, "OF_NAME=%s", ofdev->dev.of_node->name)) return -ENOMEM; - if (add_uevent_var(env, "OF_TYPE=%s", ofdev->node->type)) + if (add_uevent_var(env, "OF_TYPE=%s", ofdev->dev.of_node->type)) return -ENOMEM; /* Since the compatible field can contain pretty much anything * it's not really legal to split it out with commas. We split it * up using a number of environment variables instead. */ - compat = of_get_property(ofdev->node, "compatible", &cplen); + compat = of_get_property(ofdev->dev.of_node, "compatible", &cplen); while (compat && *compat && cplen > 0) { if (add_uevent_var(env, "OF_COMPATIBLE_%d=%s", seen, compat)) return -ENOMEM; diff --git a/arch/microblaze/kernel/of_platform.c b/arch/microblaze/kernel/of_platform.c index 0dc755286d38..ccf6f4257f4b 100644 --- a/arch/microblaze/kernel/of_platform.c +++ b/arch/microblaze/kernel/of_platform.c @@ -47,7 +47,7 @@ struct of_device *of_platform_device_create(struct device_node *np, if (!dev) return NULL; - dev->dma_mask = 0xffffffffUL; + dev->archdata.dma_mask = 0xffffffffUL; dev->dev.bus = &of_platform_bus_type; /* We do not fill the DMA ops for platform devices by default. @@ -166,7 +166,7 @@ EXPORT_SYMBOL(of_platform_bus_probe); static int of_dev_node_match(struct device *dev, void *data) { - return to_of_device(dev)->node == data; + return to_of_device(dev)->dev.of_node == data; } struct of_device *of_find_device_by_node(struct device_node *np) @@ -184,7 +184,7 @@ EXPORT_SYMBOL(of_find_device_by_node); static int of_dev_phandle_match(struct device *dev, void *data) { phandle *ph = data; - return to_of_device(dev)->node->phandle == *ph; + return to_of_device(dev)->dev.of_node->phandle == *ph; } struct of_device *of_find_device_by_phandle(phandle ph) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 9cb782b8e036..23be25fec4d6 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -1277,6 +1277,7 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus) printk(KERN_WARNING "PCI: Cannot allocate resource region " "%d of PCI bridge %d, will remap\n", i, bus->number); clear_resource: + res->start = res->end = 0; res->flags = 0; } diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7e6fd1cbd3f8..cdaae942623d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1075,6 +1075,8 @@ config CPU_LOONGSON2F bool "Loongson 2F" depends on SYS_HAS_CPU_LOONGSON2F select CPU_LOONGSON2 + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB help The Loongson 2F processor implements the MIPS III instruction set with many extensions. diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 99ae84ce5af3..ca0506a8585a 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -36,6 +36,7 @@ #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/module.h> +#include <linux/sysdev.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_dbdma.h> @@ -174,10 +175,6 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) -#ifdef CONFIG_PM -static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6]; -#endif - static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; @@ -960,29 +957,37 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void) + +struct alchemy_dbdma_sysdev { + struct sys_device sysdev; + u32 pm_regs[NUM_DBDMA_CHANS + 1][6]; +}; + +static int alchemy_dbdma_suspend(struct sys_device *dev, + pm_message_t state) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); + sdev->pm_regs[0][0] = au_readl(addr + 0x00); + sdev->pm_regs[0][1] = au_readl(addr + 0x04); + sdev->pm_regs[0][2] = au_readl(addr + 0x08); + sdev->pm_regs[0][3] = au_readl(addr + 0x0c); /* save channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); - au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); - au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); + sdev->pm_regs[i][0] = au_readl(addr + 0x00); + sdev->pm_regs[i][1] = au_readl(addr + 0x04); + sdev->pm_regs[i][2] = au_readl(addr + 0x08); + sdev->pm_regs[i][3] = au_readl(addr + 0x0c); + sdev->pm_regs[i][4] = au_readl(addr + 0x10); + sdev->pm_regs[i][5] = au_readl(addr + 0x14); /* halt channel */ - au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); + au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); au_sync(); while (!(au_readl(addr + 0x14) & 1)) au_sync(); @@ -992,32 +997,65 @@ void au1xxx_dbdma_suspend(void) /* disable channel interrupts */ au_writel(0, DDMA_GLOBAL_BASE + 0x0c); au_sync(); + + return 0; } -void au1xxx_dbdma_resume(void) +static int alchemy_dbdma_resume(struct sys_device *dev) { + struct alchemy_dbdma_sysdev *sdev = + container_of(dev, struct alchemy_dbdma_sysdev, sysdev); int i; u32 addr; addr = DDMA_GLOBAL_BASE; - au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); + au_writel(sdev->pm_regs[0][0], addr + 0x00); + au_writel(sdev->pm_regs[0][1], addr + 0x04); + au_writel(sdev->pm_regs[0][2], addr + 0x08); + au_writel(sdev->pm_regs[0][3], addr + 0x0c); /* restore channel configurations */ for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { - au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); - au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); - au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); + au_writel(sdev->pm_regs[i][0], addr + 0x00); + au_writel(sdev->pm_regs[i][1], addr + 0x04); + au_writel(sdev->pm_regs[i][2], addr + 0x08); + au_writel(sdev->pm_regs[i][3], addr + 0x0c); + au_writel(sdev->pm_regs[i][4], addr + 0x10); + au_writel(sdev->pm_regs[i][5], addr + 0x14); au_sync(); addr += 0x100; /* next channel base */ } + + return 0; +} + +static struct sysdev_class alchemy_dbdma_sysdev_class = { + .name = "dbdma", + .suspend = alchemy_dbdma_suspend, + .resume = alchemy_dbdma_resume, +}; + +static int __init alchemy_dbdma_sysdev_init(void) +{ + struct alchemy_dbdma_sysdev *sdev; + int ret; + + ret = sysdev_class_register(&alchemy_dbdma_sysdev_class); + if (ret) + return ret; + + sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL); + if (!sdev) + return -ENOMEM; + + sdev->sysdev.id = -1; + sdev->sysdev.cls = &alchemy_dbdma_sysdev_class; + ret = sysdev_register(&sdev->sysdev); + if (ret) + kfree(sdev); + + return ret; } -#endif /* CONFIG_PM */ static int __init au1xxx_dbdma_init(void) { @@ -1046,6 +1084,11 @@ static int __init au1xxx_dbdma_init(void) else { dbdma_initialized = 1; printk(KERN_INFO "Alchemy DBDMA initialized\n"); + ret = alchemy_dbdma_sysdev_init(); + if (ret) { + printk(KERN_ERR "DBDMA PM init failed\n"); + ret = 0; + } } return ret; diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index b2821ace4d00..9f78ada83b3c 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -29,6 +29,8 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/slab.h> +#include <linux/sysdev.h> #include <asm/irq_cpu.h> #include <asm/mipsregs.h> @@ -216,90 +218,6 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { }; -#ifdef CONFIG_PM - -/* - * Save/restore the interrupt controller state. - * Called from the save/restore core registers as part of the - * au_sleep function in power.c.....maybe I should just pm_register() - * them instead? - */ -static unsigned int sleep_intctl_config0[2]; -static unsigned int sleep_intctl_config1[2]; -static unsigned int sleep_intctl_config2[2]; -static unsigned int sleep_intctl_src[2]; -static unsigned int sleep_intctl_assign[2]; -static unsigned int sleep_intctl_wake[2]; -static unsigned int sleep_intctl_mask[2]; - -void save_au1xxx_intctl(void) -{ - sleep_intctl_config0[0] = au_readl(IC0_CFG0RD); - sleep_intctl_config1[0] = au_readl(IC0_CFG1RD); - sleep_intctl_config2[0] = au_readl(IC0_CFG2RD); - sleep_intctl_src[0] = au_readl(IC0_SRCRD); - sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD); - sleep_intctl_wake[0] = au_readl(IC0_WAKERD); - sleep_intctl_mask[0] = au_readl(IC0_MASKRD); - - sleep_intctl_config0[1] = au_readl(IC1_CFG0RD); - sleep_intctl_config1[1] = au_readl(IC1_CFG1RD); - sleep_intctl_config2[1] = au_readl(IC1_CFG2RD); - sleep_intctl_src[1] = au_readl(IC1_SRCRD); - sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD); - sleep_intctl_wake[1] = au_readl(IC1_WAKERD); - sleep_intctl_mask[1] = au_readl(IC1_MASKRD); -} - -/* - * For most restore operations, we clear the entire register and - * then set the bits we found during the save. - */ -void restore_au1xxx_intctl(void) -{ - au_writel(0xffffffff, IC0_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); - au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); - au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); - au_writel(0xffffffff, IC0_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); - au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC0_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); - au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC0_TESTBIT); au_sync(); - - au_writel(0xffffffff, IC1_MASKCLR); au_sync(); - - au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); - au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); - au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); - au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); - au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); - au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); - au_writel(0xffffffff, IC1_SRCCLR); au_sync(); - au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); - au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); - au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); - au_writel(0xffffffff, IC1_WAKECLR); au_sync(); - au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); - au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); - au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); - au_writel(0x00000000, IC1_TESTBIT); au_sync(); - - au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); - - au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); -} -#endif /* CONFIG_PM */ - - static void au1x_ic0_unmask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -635,3 +553,91 @@ void __init arch_init_irq(void) break; } } + +struct alchemy_ic_sysdev { + struct sys_device sysdev; + void __iomem *base; + unsigned long pmdata[7]; +}; + +static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD); + icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD); + icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD); + icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD); + icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD); + icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD); + icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD); + + return 0; +} + +static int alchemy_ic_resume(struct sys_device *dev) +{ + struct alchemy_ic_sysdev *icdev = + container_of(dev, struct alchemy_ic_sysdev, sysdev); + + __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); + __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); + __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); + __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR); + __raw_writel(0xffffffff, icdev->base + IC_WAKECLR); + __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR); + __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR); + __raw_writel(0x00000000, icdev->base + IC_TESTBIT); + wmb(); + __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); + __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); + __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); + __raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET); + __raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET); + __raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET); + wmb(); + + __raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET); + wmb(); + + return 0; +} + +static struct sysdev_class alchemy_ic_sysdev_class = { + .name = "ic", + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, +}; + +static int __init alchemy_ic_sysdev_init(void) +{ + struct alchemy_ic_sysdev *icdev; + unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR }; + int err, i; + + err = sysdev_class_register(&alchemy_ic_sysdev_class); + if (err) + return err; + + for (i = 0; i < 2; i++) { + icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL); + if (!icdev) + return -ENOMEM; + + icdev->base = ioremap(icbase[i], 0x1000); + + icdev->sysdev.id = i; + icdev->sysdev.cls = &alchemy_ic_sysdev_class; + err = sysdev_register(&icdev->sysdev); + if (err) { + kfree(icdev); + return err; + } + } + + return 0; +} +device_initcall(alchemy_ic_sysdev_init); diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 6ab7b42aa1be..14eb8c492da2 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -36,9 +36,6 @@ #include <asm/uaccess.h> #include <asm/mach-au1x00/au1000.h> -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#include <asm/mach-au1x00/au1xxx_dbdma.h> -#endif #ifdef CONFIG_PM @@ -106,9 +103,6 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ #endif - /* Save interrupt controller state. */ - save_au1xxx_intctl(); - /* Clocks and PLLs. */ sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); @@ -132,10 +126,6 @@ static void save_core_regs(void) sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_suspend(); -#endif } static void restore_core_regs(void) @@ -199,12 +189,6 @@ static void restore_core_regs(void) au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); } - - restore_au1xxx_intctl(); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_resume(); -#endif } void au_sleep(void) diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index b5311d8a29ab..4ef50d86b181 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -27,8 +27,10 @@ #include <linux/gpio.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/pm.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-pb1x00/pb1000.h> +#include <asm/reboot.h> #include <prom.h> #include "../platform.h" @@ -38,8 +40,16 @@ const char *get_system_type(void) return "Alchemy Pb1000"; } -void board_reset(void) +static void board_reset(char *c) { + asm volatile ("jr %0" : : "r" (0xbfc00000)); +} + +static void board_power_off(void) +{ + printk(KERN_ALERT "It's now safe to remove power\n"); + while (1) + asm volatile (".set mips3 ; wait ; .set mips1"); } void __init board_setup(void) @@ -177,6 +187,10 @@ void __init board_setup(void) au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); break; } + + pm_power_off = board_power_off; + _machine_halt = board_power_off; + _machine_restart = board_reset; } static int __init pb1000_init_irq(void) diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index c7b4caa81a35..90dda5f3ecc5 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c @@ -39,11 +39,6 @@ const char *get_system_type(void) return "Alchemy Pb1100"; } -void board_reset(void) -{ - bcsr_write(BCSR_SYSTEM, 0); -} - void __init board_setup(void) { volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 3184063f8042..8b4466f2d44a 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c @@ -48,12 +48,6 @@ const char *get_system_type(void) return "Alchemy Pb1200"; } -void board_reset(void) -{ - bcsr_write(BCSR_RESETS, 0); - bcsr_write(BCSR_SYSTEM, 0); -} - void __init board_setup(void) { printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index fa9770ac358a..9cd9dfa698e7 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -45,11 +45,6 @@ const char *get_system_type(void) return "Alchemy Pb1500"; } -void board_reset(void) -{ - bcsr_write(BCSR_SYSTEM, 0); -} - void __init board_setup(void) { u32 pin_func; diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index 1e8fb3ddd726..9d7d6edafa8d 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -48,11 +48,6 @@ const char *get_system_type(void) return "Alchemy Pb1550"; } -void board_reset(void) -{ - bcsr_write(BCSR_SYSTEM, 0); -} - void __init board_setup(void) { u32 pin_func; diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 2fafc78e5ce1..566f2d7f2ea3 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -576,7 +576,6 @@ static int __init ar7_register_devices(void) { void __iomem *bootcr; u32 val; - u16 chip_id; int res; res = ar7_register_uarts(); @@ -635,18 +634,10 @@ static int __init ar7_register_devices(void) val = readl(bootcr); iounmap(bootcr); if (val & AR7_WDT_HW_ENA) { - chip_id = ar7_chip_id(); - switch (chip_id) { - case AR7_CHIP_7100: - case AR7_CHIP_7200: - ar7_wdt_res.start = AR7_REGS_WDT; - break; - case AR7_CHIP_7300: + if (ar7_has_high_vlynq()) ar7_wdt_res.start = UR8_REGS_WDT; - break; - default: - break; - } + else + ar7_wdt_res.start = AR7_REGS_WDT; ar7_wdt_res.end = ar7_wdt_res.start + 0x20; res = platform_device_register(&ar7_wdt); @@ -656,4 +647,4 @@ static int __init ar7_register_devices(void) return 0; } -arch_initcall(ar7_register_devices); +device_initcall(ar7_register_devices); diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index 315bc7f79ce1..f560fe7d38dd 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -91,7 +91,7 @@ static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, spin_lock_irqsave(&bcm63xx_gpio_lock, flags); tmp = bcm_gpio_readl(reg); - if (dir == GPIO_DIR_IN) + if (dir == BCM63XX_GPIO_DIR_IN) tmp &= ~mask; else tmp |= mask; @@ -103,14 +103,14 @@ static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { - return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN); + return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN); } static int bcm63xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { bcm63xx_gpio_set(chip, gpio, value); - return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT); + return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT); } diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c index 8240728d485a..83eac37a1ff9 100644 --- a/arch/mips/cavium-octeon/serial.c +++ b/arch/mips/cavium-octeon/serial.c @@ -65,7 +65,11 @@ static void __init octeon_uart_set_common(struct plat_serial8250_port *p) p->type = PORT_OCTEON; p->iotype = UPIO_MEM; p->regshift = 3; /* I/O addresses are every 8 bytes */ - p->uartclk = mips_hpt_frequency; + if (octeon_is_simulation()) + /* Make simulator output fast*/ + p->uartclk = 115200 * 16; + else + p->uartclk = mips_hpt_frequency; p->serial_in = octeon_serial_in; p->serial_out = octeon_serial_out; } diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 9a06fa9f9f0c..d1b5ffaf0281 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -403,7 +403,6 @@ void __init prom_init(void) const int coreid = cvmx_get_core_num(); int i; int argc; - struct uart_port octeon_port; #ifdef CONFIG_CAVIUM_RESERVE32 int64_t addr = -1; #endif @@ -610,30 +609,6 @@ void __init prom_init(void) _machine_restart = octeon_restart; _machine_halt = octeon_halt; - memset(&octeon_port, 0, sizeof(octeon_port)); - /* - * For early_serial_setup we don't set the port type or - * UPF_FIXED_TYPE. - */ - octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ; - octeon_port.iotype = UPIO_MEM; - /* I/O addresses are every 8 bytes */ - octeon_port.regshift = 3; - /* Clock rate of the chip */ - octeon_port.uartclk = mips_hpt_frequency; - octeon_port.fifosize = 64; - octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart); - octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase); - octeon_port.serial_in = octeon_serial_in; - octeon_port.serial_out = octeon_serial_out; -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - octeon_port.line = 0; -#else - octeon_port.line = octeon_uart; -#endif - octeon_port.irq = 42 + octeon_uart; - early_serial_setup(&octeon_port); - octeon_user_io_init(); register_smp_ops(&octeon_smp_ops); } @@ -727,7 +702,7 @@ int prom_putchar(char c) } while ((lsrval & 0x20) == 0); /* Write the byte */ - cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c); + cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); return 1; } diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig index 5a5b6ba7514e..e70009584090 100644 --- a/arch/mips/configs/ar7_defconfig +++ b/arch/mips/configs/ar7_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30 -# Wed Jun 24 14:08:59 2009 +# Linux kernel version: 2.6.34-rc6 +# Sat May 1 11:35:01 2010 # CONFIG_MIPS=y @@ -11,11 +11,12 @@ CONFIG_MIPS=y # CONFIG_MACH_ALCHEMY is not set CONFIG_AR7=y # CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -26,6 +27,7 @@ CONFIG_AR7=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set @@ -46,6 +48,7 @@ CONFIG_AR7=y # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set # CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -63,10 +66,8 @@ CONFIG_CEVT_R4K=y CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_EARLY_PRINTK=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set @@ -81,7 +82,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -103,6 +105,8 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y @@ -124,6 +128,7 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y @@ -141,8 +146,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y # CONFIG_NO_HZ is not set @@ -165,6 +169,7 @@ CONFIG_KEXEC=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -174,6 +179,14 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_LZMA=y +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -186,14 +199,12 @@ CONFIG_BSD_PROCESS_ACCT=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y # CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_PREEMPT_RCU is not set +CONFIG_TINY_RCU=y # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -204,6 +215,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -225,19 +237,22 @@ CONFIG_SHMEM=y CONFIG_AIO=y # -# Performance Counters +# Kernel Performance Events And Counters # # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_STRIP_ASM_SYMS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 @@ -248,7 +263,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +# CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -256,14 +271,41 @@ CONFIG_BLOCK=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set CONFIG_IOSCHED_DEADLINE=y # CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_AS is not set CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -293,7 +335,6 @@ CONFIG_NET=y # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -377,6 +418,7 @@ CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set # CONFIG_NETFILTER_XT_TARGET_HL is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set @@ -458,6 +500,7 @@ CONFIG_IP_NF_RAW=m # CONFIG_IP_NF_ARPTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set CONFIG_ATM=m # CONFIG_ATM_CLIP is not set @@ -466,6 +509,7 @@ CONFIG_ATM_BR2684=m CONFIG_ATM_BR2684_IPFILTER=y CONFIG_STP=y CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set @@ -541,20 +585,19 @@ CONFIG_HAMRADIO=y # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set CONFIG_MAC80211=m -CONFIG_MAC80211_DEFAULT_PS=y -CONFIG_MAC80211_DEFAULT_PS_VALUE=1 - -# -# Rate control algorithm selection -# CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_PID=y @@ -576,6 +619,7 @@ CONFIG_MAC80211_RC_DEFAULT="pid" # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -585,9 +629,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set @@ -636,6 +680,7 @@ CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_GPIO_ADDR is not set # CONFIG_MTD_PLATRAM is not set # @@ -668,6 +713,10 @@ CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set @@ -687,6 +736,7 @@ CONFIG_HAVE_IDE=y # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # CONFIG_SCSI_DMA is not set @@ -727,6 +777,7 @@ CONFIG_MII=y # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set # CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set @@ -737,23 +788,21 @@ CONFIG_MII=y # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set CONFIG_CPMAC=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_LIBERTAS is not set +CONFIG_WLAN=y # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_MAC80211_HWSIM is not set -# CONFIG_P54_COMMON is not set -# CONFIG_HOSTAP is not set +# CONFIG_ATH_COMMON is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set +# CONFIG_LIBERTAS is not set +# CONFIG_P54_COMMON is not set # CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -813,6 +862,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set @@ -824,11 +874,39 @@ CONFIG_HW_RANDOM=y # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -842,13 +920,7 @@ CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB=y -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set -CONFIG_SSB_SERIAL=y -CONFIG_SSB_DRIVER_MIPS=y -CONFIG_SSB_EMBEDDED=y -CONFIG_SSB_DRIVER_EXTIF=y +# CONFIG_SSB is not set # # Multifunction device drivers @@ -882,15 +954,18 @@ CONFIG_LEDS_CLASS=y # # LED drivers # -# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -921,6 +996,7 @@ CONFIG_VLYNQ=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set @@ -984,6 +1060,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=y # CONFIG_SQUASHFS_EMBEDDED is not set @@ -996,11 +1073,11 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1039,21 +1116,29 @@ CONFIG_ENABLE_WARN_DEPRECATED=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LKDTM is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" # CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_SPINLOCK_TEST is not set # # Security options @@ -1061,13 +1146,16 @@ CONFIG_CMDLINE="rootfstype=squashfs,jffs2" # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m CONFIG_CRYPTO_ALGAPI2=m CONFIG_CRYPTO_AEAD2=m @@ -1108,11 +1196,13 @@ CONFIG_CRYPTO_ECB=m # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 267bd46120bc..bbd826b8032d 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25-rc2 -# Mon Feb 18 11:55:24 2008 +# Linux kernel version: 2.6.34-rc6 +# Sat May 1 12:14:30 2010 # CONFIG_MIPS=y @@ -9,20 +9,25 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set CONFIG_BCM47XX=y +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set @@ -36,10 +41,14 @@ CONFIG_BCM47XX=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -50,16 +59,16 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_CFE=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_EARLY_PRINTK=y +CONFIG_NEED_DMA_MAP_STATE=y CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set @@ -71,7 +80,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -84,6 +94,7 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -91,11 +102,13 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -105,11 +118,13 @@ CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y @@ -122,12 +137,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -144,12 +160,12 @@ CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -CONFIG_RCU_TRACE=y CONFIG_KEXEC=y # CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -163,6 +179,7 @@ CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y @@ -170,25 +187,37 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y + +# +# RCU Subsystem +# +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_PREEMPT_RCU is not set +CONFIG_TINY_RCU=y +# CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_NS=y -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set CONFIG_CGROUP_CPUACCT=y # CONFIG_RESOURCE_COUNTERS is not set -CONFIG_SYSFS_DEPRECATED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y @@ -197,54 +226,90 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y +CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_KPROBES is not set -CONFIG_PROC_PAGE_MONITOR=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_BLOCK=y -CONFIG_LBD=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_LSF=y +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set +# CONFIG_CFQ_GROUP_IOSCHED is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y -# CONFIG_PREEMPT_RCU is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -253,7 +318,8 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -262,31 +328,30 @@ CONFIG_MMU=y # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y @@ -315,7 +380,7 @@ CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_LRO=m +CONFIG_INET_LRO=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_ADVANCED=y @@ -339,36 +404,6 @@ CONFIG_DEFAULT_BIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="bic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y # CONFIG_IPV6_ROUTER_PREF is not set @@ -384,9 +419,12 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set @@ -404,6 +442,7 @@ CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=m CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m CONFIG_NF_CT_PROTO_UDPLITE=m @@ -417,20 +456,25 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -439,20 +483,23 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m # CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -460,20 +507,53 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -481,10 +561,13 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_DCCP=m CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m @@ -493,9 +576,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -507,24 +590,20 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -533,6 +612,7 @@ CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m @@ -545,31 +625,30 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set CONFIG_IP_DCCP=m CONFIG_INET_DCCP_DIAG=m -CONFIG_IP_DCCP_ACKVEC=y # # DCCP CCIDs Configuration (EXPERIMENTAL) # -CONFIG_IP_DCCP_CCID2=m # CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=m +CONFIG_IP_DCCP_CCID3=y # CONFIG_IP_DCCP_CCID3_DEBUG is not set CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=m +CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set # CONFIG_SCTP_HMAC_NONE is not set # CONFIG_SCTP_HMAC_SHA1 is not set CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set CONFIG_TIPC=m CONFIG_TIPC_ADVANCED=y CONFIG_TIPC_ZONES=3 CONFIG_TIPC_CLUSTERS=1 CONFIG_TIPC_NODES=255 -CONFIG_TIPC_SLAVE_NODES=0 CONFIG_TIPC_PORTS=8191 CONFIG_TIPC_LOG=0 # CONFIG_TIPC_DEBUG is not set @@ -580,8 +659,12 @@ CONFIG_ATM_LANE=m CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set @@ -591,6 +674,8 @@ CONFIG_LLC=m # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # @@ -601,7 +686,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -609,6 +694,7 @@ CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set CONFIG_NET_SCH_INGRESS=m # @@ -626,6 +712,7 @@ CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m # CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=m @@ -642,8 +729,10 @@ CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m +# CONFIG_NET_ACT_SKBEDIT is not set CONFIG_NET_CLS_IND=y CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -651,58 +740,7 @@ CONFIG_NET_SCH_FIFO=y CONFIG_NET_PKTGEN=m # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -# CONFIG_IRDA_ULTRA is not set - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -# CONFIG_IRDA_DEBUG is not set - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -CONFIG_ACT200L_DONGLE=m -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_TOSHIBA_FIR=m -CONFIG_VLSI_FIR=m -CONFIG_MCS_FIR=m +# CONFIG_IRDA is not set CONFIG_BT=m # CONFIG_BT_L2CAP is not set # CONFIG_BT_SCO is not set @@ -710,8 +748,7 @@ CONFIG_BT=m # # Bluetooth device drivers # -CONFIG_BT_HCIUSB=m -CONFIG_BT_HCIUSB_SCO=y +# CONFIG_BT_HCIBTUSB is not set CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y @@ -720,51 +757,37 @@ CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y - -# -# Wireless -# +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y CONFIG_CFG80211=m -CONFIG_NL80211=y -CONFIG_WIRELESS_EXT=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set CONFIG_MAC80211=m - -# -# Rate control algorithm selection -# +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_SIMPLE is not set -# CONFIG_MAC80211_RC_DEFAULT_NONE is not set - -# -# Selecting 'y' for an algorithm will -# - -# -# build the algorithm into mac80211. -# +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT="pid" -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_SIMPLE is not set +CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set -# CONFIG_MAC80211_DEBUG is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=m CONFIG_RFKILL_LEDS=y -CONFIG_NET_9P=m -CONFIG_NET_9P_FD=m -# CONFIG_NET_9P_DEBUG is not set +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set # # Device Drivers @@ -774,17 +797,22 @@ CONFIG_NET_9P_FD=m # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -829,9 +857,7 @@ CONFIG_MTD_ABSENT=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x8000000 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set @@ -854,6 +880,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_ONENAND is not set # +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set @@ -866,6 +897,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -875,18 +907,27 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # +CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=m CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -904,10 +945,6 @@ CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -924,21 +961,30 @@ CONFIG_SCSI_ISCSI_ATTRS=m # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set @@ -954,7 +1000,12 @@ CONFIG_ISCSI_TCP=m # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_FUSION is not set @@ -962,11 +1013,18 @@ CONFIG_ISCSI_TCP=m # # IEEE 1394 (FireWire) support # + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_IFB is not set CONFIG_DUMMY=m # CONFIG_BONDING is not set @@ -990,8 +1048,11 @@ CONFIG_SMSC_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_ICPLUS_PHY=m # CONFIG_REALTEK_PHY is not set -# CONFIG_FIXED_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set CONFIG_MDIO_BITBANG=m +# CONFIG_MDIO_GPIO is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set @@ -999,24 +1060,31 @@ CONFIG_MII=y # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_KSZ884X_PCI is not set CONFIG_B44=y CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y # CONFIG_FORCEDETH is not set # CONFIG_TC35815 is not set -# CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set @@ -1026,41 +1094,67 @@ CONFIG_B44_PCI=y # CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_LIBERTAS is not set -# CONFIG_HERMES is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set # CONFIG_PRISM54 is not set # CONFIG_USB_ZD1201 is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_RTL8180 is not set # CONFIG_RTL8187 is not set # CONFIG_ADM8211 is not set -# CONFIG_P54_COMMON is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set CONFIG_ATH5K=m -# CONFIG_IWL4965 is not set -# CONFIG_IWL3945 is not set +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH9K is not set +# CONFIG_AR9170_USB is not set +CONFIG_B43=m +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_LEDS=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_DEBUG=y +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set # CONFIG_HOSTAP is not set -# CONFIG_BCM43XX is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set -# CONFIG_RT2X00 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # # USB Network Adapters @@ -1072,7 +1166,10 @@ CONFIG_USB_RTL8150=m CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set CONFIG_USB_NET_DM9601=m +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m @@ -1086,6 +1183,10 @@ CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y CONFIG_USB_NET_ZAURUS=m +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +CONFIG_USB_SIERRA_NET=m # CONFIG_WAN is not set CONFIG_ATM_DRIVERS=y CONFIG_ATM_DUMMY=m @@ -1099,8 +1200,9 @@ CONFIG_ATM_TCP=m # CONFIG_ATM_AMBASSADOR is not set # CONFIG_ATM_HORIZON is not set # CONFIG_ATM_IA is not set -# CONFIG_ATM_FORE200E_MAYBE is not set +# CONFIG_ATM_FORE200E is not set # CONFIG_ATM_HE is not set +# CONFIG_ATM_SOLOS is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set CONFIG_PPP=m @@ -1120,11 +1222,10 @@ CONFIG_SLHC=m # CONFIG_SLIP_SMART is not set # CONFIG_SLIP_MODE_SLIP6 is not set # CONFIG_NET_FC is not set -CONFIG_NETCONSOLE=y -# CONFIG_NETCONSOLE_DYNAMIC is not set -CONFIG_NETPOLL=y -# CONFIG_NETPOLL_TRAP is not set -CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -1134,6 +1235,7 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -1166,6 +1268,7 @@ CONFIG_INPUT_EVDEV=m # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -1185,23 +1288,24 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set +# CONFIG_SPI is not set # -# SPI support +# PPS support # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +# CONFIG_PPS is not set CONFIG_W1=m CONFIG_W1_CON=y @@ -1217,21 +1321,45 @@ CONFIG_W1_MASTER_DS2490=m # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m +# CONFIG_W1_SLAVE_DS2431 is not set CONFIG_W1_SLAVE_DS2433=m # CONFIG_W1_SLAVE_DS2433_CRC is not set CONFIG_W1_SLAVE_DS2760=m +# CONFIG_W1_SLAVE_BQ27000 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set CONFIG_THERMAL=y -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y # -# Sonics Silicon Backplane +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_BCM47XX_WDT=y + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + # +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# CONFIG_SSB=y +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y CONFIG_SSB_PCIHOST_POSSIBLE=y CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y # CONFIG_SSB_SILENT is not set # CONFIG_SSB_DEBUG is not set CONFIG_SSB_SERIAL=y @@ -1239,24 +1367,26 @@ CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_SSB_PCICORE_HOSTMODE=y CONFIG_SSB_DRIVER_MIPS=y +CONFIG_SSB_EMBEDDED=y CONFIG_SSB_DRIVER_EXTIF=y +CONFIG_SSB_DRIVER_GIGE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -CONFIG_DAB=y -CONFIG_USB_DABUSB=m +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_LPC_SCH is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set @@ -1271,15 +1401,9 @@ CONFIG_DISPLAY_SUPPORT=m # # Display hardware drivers # - -# -# Sound -# CONFIG_SOUND=m - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1292,24 +1416,24 @@ CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_HRTIMER is not set # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# +CONFIG_SND_RAWMIDI_SEQ=m +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y CONFIG_SND_DUMMY=m CONFIG_SND_VIRMIDI=m # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set - -# -# PCI devices -# +CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALI5451 is not set @@ -1318,6 +1442,7 @@ CONFIG_SND_VIRMIDI=m # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set @@ -1325,6 +1450,8 @@ CONFIG_SND_VIRMIDI=m # CONFIG_SND_OXYGEN is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set # CONFIG_SND_DARLA20 is not set # CONFIG_SND_GINA20 is not set # CONFIG_SND_LAYLA20 is not set @@ -1337,6 +1464,8 @@ CONFIG_SND_VIRMIDI=m # CONFIG_SND_INDIGO is not set # CONFIG_SND_INDIGOIO is not set # CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set # CONFIG_SND_EMU10K1 is not set # CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set @@ -1353,6 +1482,7 @@ CONFIG_SND_VIRMIDI=m # CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set # CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set @@ -1368,45 +1498,22 @@ CONFIG_SND_VIRMIDI=m # CONFIG_SND_VIRTUOSO is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set - -# -# ALSA MIPS devices -# - -# -# USB devices -# +CONFIG_SND_MIPS=y +CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set - -# -# System on Chip audio support -# # CONFIG_SND_SOC is not set - -# -# SoC Audio support for SuperH -# - -# -# ALSA SoC audio for Freescale SOCs -# - -# -# Open Sound System -# # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=m -# CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=m -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y # @@ -1414,6 +1521,41 @@ CONFIG_USB_HIDDEV=y # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1429,14 +1571,24 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_HCD_SSB is not set # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set @@ -1446,26 +1598,30 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_U132_HCD=m # CONFIG_USB_SL811_HCD is not set CONFIG_USB_R8A66597_HCD=m +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set # # USB Device Class drivers # CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# may also be needed; see USB_STORAGE Help for more information +# also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y # CONFIG_USB_STORAGE_ISD200 is not set -CONFIG_USB_STORAGE_DPCM=y CONFIG_USB_STORAGE_USBAT=y CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y @@ -1473,6 +1629,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -1480,7 +1637,6 @@ CONFIG_USB_STORAGE_KARMA=y # CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m -# CONFIG_USB_MON is not set # # USB port drivers @@ -1489,13 +1645,12 @@ CONFIG_USB_SERIAL=m CONFIG_USB_EZUSB=y CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_AIRPRIME=m CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_CH341=m # CONFIG_USB_SERIAL_WHITEHEAT is not set CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP2101=m +# CONFIG_USB_SERIAL_CP210X is not set CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -1515,18 +1670,26 @@ CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_MOS7720=m CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MOTOROLA is not set CONFIG_USB_SERIAL_NAVMAN=m CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_OTI6858=m +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_SAFE=m # CONFIG_USB_SERIAL_SAFE_PADDED is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set CONFIG_USB_SERIAL_SIERRAWIRELESS=m +# CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set CONFIG_USB_SERIAL_DEBUG=m # @@ -1535,18 +1698,13 @@ CONFIG_USB_SERIAL_DEBUG=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set CONFIG_USB_ADUTUX=m -CONFIG_USB_AUERSWALD=m +# CONFIG_USB_SEVSEG is not set CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m CONFIG_USB_LED=m CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m -CONFIG_USB_PHIDGET=m -CONFIG_USB_PHIDGETKIT=m -CONFIG_USB_PHIDGETMOTORCONTROL=m -CONFIG_USB_PHIDGETSERVO=m CONFIG_USB_IDMOUSE=m CONFIG_USB_FTDI_ELAN=m # CONFIG_USB_APPLEDISPLAY is not set @@ -1555,6 +1713,7 @@ CONFIG_USB_LD=m CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m @@ -1563,30 +1722,51 @@ CONFIG_USB_XUSBATM=m CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -CONFIG_USB_GADGET_NET2280=y -CONFIG_USB_NET2280=m -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set CONFIG_USB_GADGETFS=m CONFIG_USB_FILE_STORAGE=m # CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set CONFIG_USB_G_SERIAL=m CONFIG_USB_MIDI_GADGET=m # CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -1596,21 +1776,33 @@ CONFIG_LEDS_CLASS=y # LED drivers # CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # -# Userspace I/O +# TI VLYNQ # -# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -1621,10 +1813,11 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y @@ -1642,28 +1835,39 @@ CONFIG_JFS_SECURITY=y CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_NOLOCK=m -CONFIG_GFS2_FS_LOCKING_DLM=m +# CONFIG_GFS2_FS_LOCKING_DLM is not set # CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m CONFIG_QFMT_V1=m CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set CONFIG_GENERIC_ACL=y # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=m @@ -1690,15 +1894,13 @@ CONFIG_NTFS_RW=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y CONFIG_ADFS_FS=m # CONFIG_ADFS_FS_RW is not set CONFIG_AFFS_FS=m @@ -1721,12 +1923,19 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set CONFIG_VXFS_FS=m CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set CONFIG_HPFS_FS=m CONFIG_QNX4FS_FS=m CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y CONFIG_SYSV_FS=m CONFIG_UFS_FS=m # CONFIG_UFS_FS_WRITE is not set @@ -1736,13 +1945,12 @@ CONFIG_NFS_FS=m CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFS_V4_1 is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y -CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m @@ -1750,10 +1958,10 @@ CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m -CONFIG_SUNRPC_BIND34=y CONFIG_RPCSEC_GSS_KRB5=m CONFIG_RPCSEC_GSS_SPKM3=m # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set @@ -1771,9 +1979,7 @@ CONFIG_NCPFS_OS2_NS=y CONFIG_NCPFS_NLS=y CONFIG_NCPFS_EXTRAS=y CONFIG_CODA_FS=m -# CONFIG_CODA_FS_OLD_API is not set # CONFIG_AFS_FS is not set -CONFIG_9P_FS=m # # Partition Types @@ -1846,90 +2052,167 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set +# CONFIG_SPINLOCK_TEST is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_SEQIV is not set +CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_XTS=m -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_SEED=m # CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set CONFIG_CRC_ITU_T=m CONFIG_CRC32=y CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_AUDIT_GENERIC=y -CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 144b94d9a6ad..cff8f4c0e57c 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.23-rc8 -# Sun Sep 30 12:56:10 2007 +# Linux kernel version: 2.6.34-rc6 +# Sat May 1 13:39:10 2010 # CONFIG_MIPS=y @@ -9,20 +9,28 @@ CONFIG_MIPS=y # Machine selection # CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set @@ -33,10 +41,14 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_MIPS_MTX1=y # CONFIG_MIPS_BOSPORUS is not set # CONFIG_MIPS_DB1000 is not set @@ -53,29 +65,38 @@ CONFIG_MIPS_MTX1=y # CONFIG_MIPS_XXS1500 is not set CONFIG_SOC_AU1500=y CONFIG_SOC_AU1X00=y +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_HOTPLUG_CPU is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -88,6 +109,7 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -95,11 +117,14 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -109,28 +134,36 @@ CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -148,6 +181,7 @@ CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -157,23 +191,49 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=17 -CONFIG_SYSFS_DEPRECATED=y +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y @@ -182,61 +242,104 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y CONFIG_BLOCK=y -CONFIG_LBD=y -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=m -# CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_IOCTL=y CONFIG_CARDBUS=y # @@ -251,6 +354,7 @@ CONFIG_YENTA_TOSHIBA=y CONFIG_PD6729=m CONFIG_I82092=m # CONFIG_PCMCIA_AU1X00 is not set +# CONFIG_PCMCIA_ALCHEMY_DEVBOARD is not set CONFIG_PCCARD_NONSTATIC=m # CONFIG_HOTPLUG_PCI is not set @@ -258,35 +362,38 @@ CONFIG_PCCARD_NONSTATIC=m # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y -CONFIG_SUSPEND_UP_POSSIBLE=y CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set # CONFIG_APM_EMULATION is not set - -# -# Networking -# +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y CONFIG_NET=y # # Networking options # CONFIG_PACKET=m -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y @@ -315,42 +422,13 @@ CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y # CONFIG_IPV6_ROUTER_PREF is not set @@ -366,12 +444,15 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m # CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_NETLABEL is not set +# CONFIG_IPV6_MROUTE is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # @@ -380,57 +461,97 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -# CONFIG_NF_CONNTRACK_ENABLED is not set # CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set CONFIG_NETFILTER_XT_TARGET_SECMARK=m # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -439,34 +560,29 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # -# IPv6: Netfilter Configuration (EXPERIMENTAL) +# IPv6: Netfilter Configuration # CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m # CONFIG_IP6_NF_MATCH_MH is not set -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m # # DECnet: Netfilter Configuration # CONFIG_DECNET_NF_GRABULATOR=m - -# -# Bridge: Netfilter Configuration -# CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -475,6 +591,7 @@ CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m @@ -487,25 +604,25 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set CONFIG_IP_DCCP=m CONFIG_INET_DCCP_DIAG=m -CONFIG_IP_DCCP_ACKVEC=y # # DCCP CCIDs Configuration (EXPERIMENTAL) # -CONFIG_IP_DCCP_CCID2=m # CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=m -CONFIG_IP_DCCP_TFRC_LIB=m +CONFIG_IP_DCCP_CCID3=y # CONFIG_IP_DCCP_CCID3_DEBUG is not set CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set # CONFIG_SCTP_HMAC_NONE is not set # CONFIG_SCTP_HMAC_SHA1 is not set CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set CONFIG_TIPC=m # CONFIG_TIPC_ADVANCED is not set # CONFIG_TIPC_DEBUG is not set @@ -516,8 +633,12 @@ CONFIG_ATM_LANE=m CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set CONFIG_DECNET=m # CONFIG_DECNET_ROUTER is not set CONFIG_LLC=y @@ -535,12 +656,9 @@ CONFIG_ECONET=m CONFIG_ECONET_AUNUDP=y CONFIG_ECONET_NATIVE=y CONFIG_WAN_ROUTER=m - -# -# QoS and/or fair queueing -# +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y # # Queueing/Scheduling @@ -550,7 +668,7 @@ CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m -# CONFIG_NET_SCH_RR is not set +# CONFIG_NET_SCH_MULTIQ is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -558,6 +676,7 @@ CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set CONFIG_NET_SCH_INGRESS=m # @@ -574,6 +693,7 @@ CONFIG_NET_CLS_U32=m CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=m @@ -586,10 +706,13 @@ CONFIG_NET_ACT_POLICE=y # CONFIG_NET_ACT_GACT is not set # CONFIG_NET_ACT_MIRRED is not set # CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set # CONFIG_NET_ACT_PEDIT is not set # CONFIG_NET_ACT_SIMP is not set -CONFIG_NET_CLS_POLICE=y +# CONFIG_NET_ACT_SKBEDIT is not set # CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -613,9 +736,8 @@ CONFIG_6PACK=m CONFIG_BPQETHER=m CONFIG_BAYCOM_SER_FDX=m CONFIG_BAYCOM_SER_HDX=m -CONFIG_BAYCOM_PAR=m -CONFIG_BAYCOM_EPP=m CONFIG_YAM=m +# CONFIG_CAN is not set CONFIG_IRDA=m # @@ -657,15 +779,8 @@ CONFIG_MCP2120_DONGLE=m CONFIG_OLD_BELKIN_DONGLE=m CONFIG_ACT200L_DONGLE=m # CONFIG_KINGSUN_DONGLE is not set - -# -# Old SIR device drivers -# -# CONFIG_IRPORT_SIR is not set - -# -# Old Serial dongle support -# +# CONFIG_KSDAZZLE_DONGLE is not set +# CONFIG_KS959_DONGLE is not set # # FIR device drivers @@ -683,17 +798,17 @@ CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_CMTP=m CONFIG_BT_HIDP=m # # Bluetooth device drivers # -CONFIG_BT_HCIUSB=m -CONFIG_BT_HCIUSB_SCO=y +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -702,24 +817,19 @@ CONFIG_BT_HCIBT3C=m CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIBTUART=m CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set CONFIG_AF_RXRPC=m # CONFIG_AF_RXRPC_DEBUG is not set # CONFIG_RXKAD is not set CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set # -# Wireless +# CFG80211 needs to be enabled for MAC80211 # -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -730,40 +840,43 @@ CONFIG_IEEE80211_SOFTMAC=m # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m -CONFIG_MTD=m +CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=m +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=m -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLKDEVS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_BLOCK_RO=m -CONFIG_FTL=m -CONFIG_NFTL=m -CONFIG_NFTL_RW=y -CONFIG_INFTL=m -CONFIG_RFD_FTL=m -CONFIG_SSFDC=m +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y @@ -775,206 +888,81 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=m -CONFIG_MTD_ROM=m -CONFIG_MTD_ABSENT=m +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_START=0x8000000 -CONFIG_MTD_PHYSMAP_LEN=0x4000000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_ALCHEMY is not set -# CONFIG_MTD_MTX1 is not set -CONFIG_MTD_PCI=m -CONFIG_MTD_PLATRAM=m +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -CONFIG_MTD_PMC551=m -# CONFIG_MTD_PMC551_BUGFIX is not set -# CONFIG_MTD_PMC551_DEBUG is not set -CONFIG_MTD_DATAFLASH=m -CONFIG_MTD_M25P80=m -CONFIG_MTD_SLRAM=m -CONFIG_MTD_PHRAM=m -CONFIG_MTD_MTDRAM=m -CONFIG_MTDRAM_TOTAL_SIZE=4096 -CONFIG_MTDRAM_ERASE_SIZE=128 -CONFIG_MTD_BLOCK2MTD=m +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers # -CONFIG_MTD_DOC2000=m -CONFIG_MTD_DOC2001=m -CONFIG_MTD_DOC2001PLUS=m -CONFIG_MTD_DOCPROBE=m -CONFIG_MTD_DOCECC=m -# CONFIG_MTD_DOCPROBE_ADVANCED is not set -CONFIG_MTD_DOCPROBE_ADDRESS=0 -CONFIG_MTD_NAND=m -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=m -CONFIG_MTD_NAND_DISKONCHIP=m -# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 -# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set -# CONFIG_MTD_NAND_CAFE is not set -CONFIG_MTD_NAND_NANDSIM=m -# CONFIG_MTD_NAND_PLATFORM is not set -CONFIG_MTD_ONENAND=m -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set # # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_SERIAL=m -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_PC_SUPERIO=y -CONFIG_PARPORT_PC_PCMCIA=m -# CONFIG_PARPORT_GSC is not set -CONFIG_PARPORT_AX88796=m -CONFIG_PARPORT_1284=y -CONFIG_PARPORT_NOT_PC=y +# CONFIG_PARPORT is not set CONFIG_BLK_DEV=y -CONFIG_PARIDE=m - -# -# Parallel IDE high-level drivers -# -CONFIG_PARIDE_PD=m -CONFIG_PARIDE_PCD=m -CONFIG_PARIDE_PF=m -CONFIG_PARIDE_PT=m -CONFIG_PARIDE_PG=m - -# -# Parallel IDE protocol modules -# -CONFIG_PARIDE_ATEN=m -CONFIG_PARIDE_BPCK=m -CONFIG_PARIDE_BPCK6=m -CONFIG_PARIDE_COMM=m -CONFIG_PARIDE_DSTR=m -CONFIG_PARIDE_FIT2=m -CONFIG_PARIDE_FIT3=m -CONFIG_PARIDE_EPAT=m -CONFIG_PARIDE_EPATC8=y -CONFIG_PARIDE_EPIA=m -CONFIG_PARIDE_FRIQ=m -CONFIG_PARIDE_FRPW=m -CONFIG_PARIDE_KBIC=m -CONFIG_PARIDE_KTTI=m -CONFIG_PARIDE_ON20=m -CONFIG_PARIDE_ON26=m -CONFIG_BLK_CPQ_DA=m -CONFIG_BLK_CPQ_CISS_DA=m -CONFIG_CISS_SCSI_TAPE=y -CONFIG_BLK_DEV_DAC960=m -CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_SX8=m +# CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_SGI_IOC4=m -CONFIG_TIFM_CORE=m -CONFIG_TIFM_7XX1=m -CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=m -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECS=m -# CONFIG_BLK_DEV_DELKIN is not set -CONFIG_BLK_DEV_IDECD=m -CONFIG_BLK_DEV_IDETAPE=m -CONFIG_BLK_DEV_IDEFLOPPY=m -CONFIG_BLK_DEV_IDESCSI=m -# CONFIG_IDE_TASK_IOCTL is not set -CONFIG_IDE_PROC_FS=y - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=m -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y -CONFIG_IDEPCI_PCIBUS_ORDER=y -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=m -CONFIG_BLK_DEV_OPTI621=m -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_ONLYDISK is not set -CONFIG_BLK_DEV_AEC62XX=m -CONFIG_BLK_DEV_ALI15X3=m -# CONFIG_WDC_ALI15X3 is not set -CONFIG_BLK_DEV_AMD74XX=m -CONFIG_BLK_DEV_CMD64X=m -CONFIG_BLK_DEV_TRIFLEX=m -CONFIG_BLK_DEV_CY82C693=m -# CONFIG_BLK_DEV_CS5520 is not set -CONFIG_BLK_DEV_CS5530=m -CONFIG_BLK_DEV_HPT34X=m -# CONFIG_HPT34X_AUTODMA is not set -CONFIG_BLK_DEV_HPT366=m -# CONFIG_BLK_DEV_JMICRON is not set -CONFIG_BLK_DEV_SC1200=m -CONFIG_BLK_DEV_PIIX=m -# CONFIG_BLK_DEV_IT8213 is not set -CONFIG_BLK_DEV_IT821X=m -CONFIG_BLK_DEV_NS87415=m -CONFIG_BLK_DEV_PDC202XX_OLD=m -CONFIG_PDC202XX_BURST=y -CONFIG_BLK_DEV_PDC202XX_NEW=m -CONFIG_BLK_DEV_SVWKS=m -CONFIG_BLK_DEV_SIIMAGE=m -# CONFIG_BLK_DEV_SLC90E66 is not set -CONFIG_BLK_DEV_TRM290=m -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_IDE_ARM is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_TIFM_CORE=m +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # # SCSI device support # -CONFIG_RAID_ATTRS=m +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set CONFIG_SCSI=m CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set @@ -985,18 +973,13 @@ CONFIG_SCSI_PROC_FS=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# +# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CONSTANTS is not set CONFIG_SCSI_LOGGING=y # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m @@ -1009,198 +992,39 @@ CONFIG_SCSI_FC_ATTRS=m CONFIG_SCSI_ISCSI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m CONFIG_SCSI_SAS_LIBSAS=m -# CONFIG_SCSI_SAS_ATA is not set +CONFIG_SCSI_SAS_HOST_SMP=y # CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -CONFIG_BLK_DEV_3W_XXXX_RAID=m -CONFIG_SCSI_3W_9XXX=m -CONFIG_SCSI_ACARD=m -CONFIG_SCSI_AACRAID=m -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -CONFIG_AIC7XXX_DEBUG_ENABLE=y -CONFIG_AIC7XXX_DEBUG_MASK=0 -CONFIG_AIC7XXX_REG_PRETTY_PRINT=y -# CONFIG_SCSI_AIC7XXX_OLD is not set -CONFIG_SCSI_AIC79XX=m -CONFIG_AIC79XX_CMDS_PER_DEVICE=32 -CONFIG_AIC79XX_RESET_DELAY_MS=15000 -CONFIG_AIC79XX_DEBUG_ENABLE=y -CONFIG_AIC79XX_DEBUG_MASK=0 -CONFIG_AIC79XX_REG_PRETTY_PRINT=y -CONFIG_SCSI_AIC94XX=m -# CONFIG_AIC94XX_DEBUG is not set -CONFIG_SCSI_DPT_I2O=m -CONFIG_SCSI_ARCMSR=m -CONFIG_MEGARAID_NEWGEN=y -CONFIG_MEGARAID_MM=m -CONFIG_MEGARAID_MAILBOX=m -CONFIG_MEGARAID_LEGACY=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_HPTIOP=m -CONFIG_SCSI_DMX3191D=m -CONFIG_SCSI_FUTURE_DOMAIN=m -CONFIG_SCSI_IPS=m -CONFIG_SCSI_INITIO=m -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_PPA=m -CONFIG_SCSI_IMM=m -# CONFIG_SCSI_IZIP_EPP16 is not set -# CONFIG_SCSI_IZIP_SLOW_CTR is not set -CONFIG_SCSI_STEX=m -CONFIG_SCSI_SYM53C8XX_2=m -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -CONFIG_SCSI_SYM53C8XX_MMIO=y -CONFIG_SCSI_IPR=m -# CONFIG_SCSI_IPR_TRACE is not set -# CONFIG_SCSI_IPR_DUMP is not set -CONFIG_SCSI_QLOGIC_1280=m -CONFIG_SCSI_QLA_FC=m -CONFIG_SCSI_QLA_ISCSI=m -CONFIG_SCSI_LPFC=m -CONFIG_SCSI_DC395x=m -CONFIG_SCSI_DC390T=m -CONFIG_SCSI_NSP32=m -CONFIG_SCSI_DEBUG=m -# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -CONFIG_ATA=m -# CONFIG_ATA_NONSTANDARD is not set -CONFIG_SATA_AHCI=m -CONFIG_SATA_SVW=m -CONFIG_ATA_PIIX=m -CONFIG_SATA_MV=m -CONFIG_SATA_NV=m -CONFIG_PDC_ADMA=m -CONFIG_SATA_QSTOR=m -CONFIG_SATA_PROMISE=m -CONFIG_SATA_SX4=m -CONFIG_SATA_SIL=m -CONFIG_SATA_SIL24=m -CONFIG_SATA_SIS=m -CONFIG_SATA_ULI=m -CONFIG_SATA_VIA=m -CONFIG_SATA_VITESSE=m -# CONFIG_SATA_INIC162X is not set -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -CONFIG_PATA_CS5520=m -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CYPRESS is not set -CONFIG_PATA_EFAR=m -CONFIG_ATA_GENERIC=m -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_IT8213 is not set -CONFIG_PATA_JMICRON=m -CONFIG_PATA_TRIFLEX=m -# CONFIG_PATA_MARVELL is not set -CONFIG_PATA_MPIIX=m -# CONFIG_PATA_OLDPIIX is not set -CONFIG_PATA_NETCELL=m -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -CONFIG_PATA_PCMCIA=m -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -CONFIG_PATA_RZ1000=m -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SERVERWORKS is not set -CONFIG_PATA_PDC2027X=m -CONFIG_PATA_SIL680=m -CONFIG_PATA_SIS=m -CONFIG_PATA_VIA=m -CONFIG_PATA_WINBOND=m -# CONFIG_PATA_PLATFORM is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -# CONFIG_MD_RAID5_RESHAPE is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m -# CONFIG_DM_MULTIPATH_RDAC is not set -# CONFIG_DM_DELAY is not set - -# -# Fusion MPT device support -# -CONFIG_FUSION=y -CONFIG_FUSION_SPI=m -CONFIG_FUSION_FC=m -CONFIG_FUSION_SAS=m -CONFIG_FUSION_MAX_SGE=128 -CONFIG_FUSION_CTL=m -CONFIG_FUSION_LAN=m -# CONFIG_FUSION_LOGGING is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # -# CONFIG_FIREWIRE is not set -CONFIG_IEEE1394=m - -# -# Subsystem Options -# -# CONFIG_IEEE1394_VERBOSEDEBUG is not set # -# Controllers +# You can enable one or both FireWire driver stacks. # -CONFIG_IEEE1394_PCILYNX=m -CONFIG_IEEE1394_OHCI1394=m # -# Protocols +# The newer stack is recommended. # -CONFIG_IEEE1394_VIDEO1394=m -CONFIG_IEEE1394_SBP2=m -# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set -CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y -CONFIG_IEEE1394_ETH1394=m -CONFIG_IEEE1394_DV1394=m -CONFIG_IEEE1394_RAWIO=m -CONFIG_I2O=m -CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y -CONFIG_I2O_EXT_ADAPTEC=y -CONFIG_I2O_CONFIG=m -CONFIG_I2O_CONFIG_OLD_IOCTL=y -CONFIG_I2O_BUS=m -CONFIG_I2O_BLOCK=m -CONFIG_I2O_SCSI=m -CONFIG_I2O_PROC=m +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_IFB is not set CONFIG_DUMMY=m CONFIG_BONDING=m # CONFIG_MACVLAN is not set CONFIG_EQUALIZER=m CONFIG_TUN=m +# CONFIG_VETH is not set CONFIG_ARCNET=m CONFIG_ARCNET_1201=m CONFIG_ARCNET_1051=m @@ -1225,9 +1049,11 @@ CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set -CONFIG_FIXED_PHY=m -# CONFIG_FIXED_MII_10_FDX is not set -# CONFIG_FIXED_MII_100_FDX is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_AX88796 is not set @@ -1240,8 +1066,12 @@ CONFIG_VORTEX=m CONFIG_TYPHOON=m # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set CONFIG_NET_TULIP=y CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 CONFIG_TULIP=m # CONFIG_TULIP_MWI is not set # CONFIG_TULIP_MMIO is not set @@ -1251,21 +1081,26 @@ CONFIG_WINBOND_840=m CONFIG_DM9102=m CONFIG_ULI526X=m CONFIG_PCMCIA_XIRCOM=m -# CONFIG_PCMCIA_XIRTULIP is not set CONFIG_HP100=m +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y CONFIG_PCNET32=m -# CONFIG_PCNET32_NAPI is not set CONFIG_AMD8111_ETH=m -# CONFIG_AMD8111E_NAPI is not set CONFIG_ADAPTEC_STARFIRE=m -# CONFIG_ADAPTEC_STARFIRE_NAPI is not set +# CONFIG_KSZ884X_PCI is not set CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y CONFIG_FORCEDETH=m # CONFIG_FORCEDETH_NAPI is not set # CONFIG_TC35815 is not set -CONFIG_DGRS=m -CONFIG_EEPRO100=m CONFIG_E100=m CONFIG_FEALNX=m CONFIG_NATSEMI=m @@ -1276,52 +1111,71 @@ CONFIG_8139TOO=m # CONFIG_8139TOO_TUNE_TWISTER is not set CONFIG_8139TOO_8129=y # CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_R6040 is not set CONFIG_SIS900=m CONFIG_EPIC100=m +# CONFIG_SMSC9420 is not set CONFIG_SUNDANCE=m # CONFIG_SUNDANCE_MMIO is not set CONFIG_TLAN=m +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set CONFIG_VIA_RHINE=m # CONFIG_VIA_RHINE_MMIO is not set -# CONFIG_VIA_RHINE_NAPI is not set # CONFIG_SC92031 is not set -CONFIG_NET_POCKET=y -CONFIG_DE600=m -CONFIG_DE620=m +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y CONFIG_ACENIC=m # CONFIG_ACENIC_OMIT_TIGON_I is not set CONFIG_DL2K=m CONFIG_E1000=m -# CONFIG_E1000_NAPI is not set -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set CONFIG_NS83820=m CONFIG_HAMACHI=m CONFIG_YELLOWFIN=m CONFIG_R8169=m -# CONFIG_R8169_NAPI is not set CONFIG_R8169_VLAN=y CONFIG_SIS190=m CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set CONFIG_SKY2=m -CONFIG_SK98LIN=m +# CONFIG_SKY2_DEBUG is not set CONFIG_VIA_VELOCITY=m CONFIG_TIGON3=m CONFIG_BNX2=m +# CONFIG_CNIC is not set CONFIG_QLA3XXX=m # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y +CONFIG_MDIO=m CONFIG_CHELSIO_T1=m # CONFIG_CHELSIO_T1_1G is not set -CONFIG_CHELSIO_T1_NAPI=y +CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4_DEPENDS=y +# CONFIG_CHELSIO_T4 is not set +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set CONFIG_IXGB=m -# CONFIG_IXGB_NAPI is not set CONFIG_S2IO=m -# CONFIG_S2IO_NAPI is not set +# CONFIG_VXGE is not set CONFIG_MYRI10GE=m # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set +# CONFIG_BE2NET is not set CONFIG_TR=y CONFIG_IBMOL=m CONFIG_IBMLS=m @@ -1329,12 +1183,18 @@ CONFIG_3C359=m CONFIG_TMS380TR=m CONFIG_TMSPCI=m CONFIG_ABYSS=m +CONFIG_WLAN=y +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_ATMEL is not set +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set # -# Wireless LAN +# Enable WiMAX (Networking options) to see the WiMAX drivers # -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set # # USB Network Adapters @@ -1343,11 +1203,13 @@ CONFIG_USB_CATC=m CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET_MII=m CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set # CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m @@ -1361,6 +1223,9 @@ CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y # CONFIG_USB_KC2190 is not set CONFIG_USB_NET_ZAURUS=m +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +CONFIG_USB_SIERRA_NET=m CONFIG_NET_PCMCIA=y CONFIG_PCMCIA_3C589=m CONFIG_PCMCIA_3C574=m @@ -1383,16 +1248,6 @@ CONFIG_HDLC_PPP=m CONFIG_HDLC_X25=m CONFIG_PCI200SYN=m CONFIG_WANXL=m -CONFIG_PC300=m -CONFIG_PC300_MLPPP=y - -# -# Cyclades-PC300 MLPPP support is disabled. -# - -# -# Refer to the file README.mlppp, provided by PC300 package. -# # CONFIG_PC300TOO is not set CONFIG_FARSYNC=m CONFIG_DSCC4=m @@ -1428,15 +1283,13 @@ CONFIG_ATM_HORIZON=m # CONFIG_ATM_HORIZON_DEBUG is not set CONFIG_ATM_IA=m # CONFIG_ATM_IA_DEBUG is not set -CONFIG_ATM_FORE200E_MAYBE=m -CONFIG_ATM_FORE200E_PCA=y -CONFIG_ATM_FORE200E_PCA_DEFAULT_FW=y +CONFIG_ATM_FORE200E=m # CONFIG_ATM_FORE200E_USE_TASKLET is not set CONFIG_ATM_FORE200E_TX_RETRY=16 CONFIG_ATM_FORE200E_DEBUG=0 -CONFIG_ATM_FORE200E=m CONFIG_ATM_HE=m CONFIG_ATM_HE_USE_SUNI=y +# CONFIG_ATM_SOLOS is not set CONFIG_FDDI=y CONFIG_DEFXX=m # CONFIG_DEFXX_MMIO is not set @@ -1444,7 +1297,6 @@ CONFIG_SKFP=m CONFIG_HIPPI=y CONFIG_ROADRUNNER=m # CONFIG_ROADRUNNER_LARGE_RINGS is not set -CONFIG_PLIP=m CONFIG_PPP=m CONFIG_PPP_MULTILINK=y CONFIG_PPP_FILTER=y @@ -1462,219 +1314,53 @@ CONFIG_SLHC=m CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y CONFIG_NET_FC=y -CONFIG_SHAPER=m CONFIG_NETCONSOLE=m +# CONFIG_NETCONSOLE_DYNAMIC is not set CONFIG_NETPOLL=y # CONFIG_NETPOLL_TRAP is not set CONFIG_NET_POLL_CONTROLLER=y -CONFIG_ISDN=m -CONFIG_ISDN_I4L=m -CONFIG_ISDN_PPP=y -CONFIG_ISDN_PPP_VJ=y -CONFIG_ISDN_MPP=y -CONFIG_IPPP_FILTER=y -CONFIG_ISDN_PPP_BSDCOMP=m -CONFIG_ISDN_AUDIO=y -CONFIG_ISDN_TTY_FAX=y -CONFIG_ISDN_X25=y - -# -# ISDN feature submodules -# -# CONFIG_ISDN_DRV_LOOP is not set -CONFIG_ISDN_DIVERSION=m - -# -# ISDN4Linux hardware drivers -# - -# -# Passive cards -# -CONFIG_ISDN_DRV_HISAX=m - -# -# D-channel protocol features -# -CONFIG_HISAX_EURO=y -CONFIG_DE_AOC=y -# CONFIG_HISAX_NO_SENDCOMPLETE is not set -# CONFIG_HISAX_NO_LLC is not set -# CONFIG_HISAX_NO_KEYPAD is not set -CONFIG_HISAX_1TR6=y -CONFIG_HISAX_NI1=y -CONFIG_HISAX_MAX_CARDS=8 - -# -# HiSax supported cards -# -CONFIG_HISAX_16_3=y -CONFIG_HISAX_TELESPCI=y -CONFIG_HISAX_S0BOX=y -CONFIG_HISAX_FRITZPCI=y -CONFIG_HISAX_AVM_A1_PCMCIA=y -CONFIG_HISAX_ELSA=y -CONFIG_HISAX_DIEHLDIVA=y -CONFIG_HISAX_SEDLBAUER=y -CONFIG_HISAX_NETJET=y -CONFIG_HISAX_NETJET_U=y -CONFIG_HISAX_NICCY=y -CONFIG_HISAX_BKM_A4T=y -CONFIG_HISAX_SCT_QUADRO=y -CONFIG_HISAX_GAZEL=y -CONFIG_HISAX_HFC_PCI=y -CONFIG_HISAX_W6692=y -CONFIG_HISAX_HFC_SX=y -CONFIG_HISAX_ENTERNOW_PCI=y -# CONFIG_HISAX_DEBUG is not set - -# -# HiSax PCMCIA card service modules -# -CONFIG_HISAX_SEDLBAUER_CS=m -CONFIG_HISAX_ELSA_CS=m -CONFIG_HISAX_AVM_A1_CS=m -CONFIG_HISAX_TELES_CS=m - -# -# HiSax sub driver modules -# -CONFIG_HISAX_ST5481=m -CONFIG_HISAX_HFCUSB=m -CONFIG_HISAX_HFC4S8S=m -CONFIG_HISAX_FRITZ_PCIPNP=m -CONFIG_HISAX_HDLC=y - -# -# Active cards -# -# CONFIG_HYSDN is not set -CONFIG_ISDN_DRV_GIGASET=m -CONFIG_GIGASET_BASE=m -CONFIG_GIGASET_M105=m -# CONFIG_GIGASET_M101 is not set -# CONFIG_GIGASET_DEBUG is not set -# CONFIG_GIGASET_UNDOCREQ is not set -CONFIG_ISDN_CAPI=m -CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y -CONFIG_CAPI_TRACE=y -CONFIG_ISDN_CAPI_MIDDLEWARE=y -CONFIG_ISDN_CAPI_CAPI20=m -CONFIG_ISDN_CAPI_CAPIFS_BOOL=y -CONFIG_ISDN_CAPI_CAPIFS=m -CONFIG_ISDN_CAPI_CAPIDRV=m - -# -# CAPI hardware drivers -# -CONFIG_CAPI_AVM=y -CONFIG_ISDN_DRV_AVMB1_B1PCI=m -CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y -CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m -CONFIG_ISDN_DRV_AVMB1_AVM_CS=m -CONFIG_ISDN_DRV_AVMB1_T1PCI=m -CONFIG_ISDN_DRV_AVMB1_C4=m -CONFIG_CAPI_EICON=y -CONFIG_ISDN_DIVAS=m -CONFIG_ISDN_DIVAS_BRIPCI=y -CONFIG_ISDN_DIVAS_PRIPCI=y -CONFIG_ISDN_DIVAS_DIVACAPI=m -CONFIG_ISDN_DIVAS_USERIDI=m -CONFIG_ISDN_DIVAS_MAINT=m -CONFIG_PHONE=m -CONFIG_PHONE_IXJ=m -CONFIG_PHONE_IXJ_PCMCIA=m +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_TSDEV=m -CONFIG_INPUT_TSDEV_SCREEN_X=240 -CONFIG_INPUT_TSDEV_SCREEN_Y=320 -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SUNKBD=m -CONFIG_KEYBOARD_LKKBD=m -CONFIG_KEYBOARD_XTKBD=m -CONFIG_KEYBOARD_NEWTON=m -CONFIG_KEYBOARD_STOWAWAY=m -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_SERIAL=m -# CONFIG_MOUSE_APPLETOUCH is not set -CONFIG_MOUSE_VSXXXAA=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=y -CONFIG_JOYSTICK_IFORCE_232=y -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_DB9=m -CONFIG_JOYSTICK_GAMECON=m -CONFIG_JOYSTICK_TURBOGRAFX=m -CONFIG_JOYSTICK_JOYDUMP=m -# CONFIG_JOYSTICK_XPAD is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m -# CONFIG_TOUCHSCREEN_FUJITSU is not set -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_MK712=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -# CONFIG_TOUCHSCREEN_UCB1400 is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PCSPKR=m -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -CONFIG_INPUT_UINPUT=m +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Hardware I/O ports @@ -1682,10 +1368,10 @@ CONFIG_INPUT_UINPUT=m CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_PARKBD=m CONFIG_SERIO_PCIPS2=m CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=m +# CONFIG_SERIO_ALTERA_PS2 is not set CONFIG_GAMEPORT=m CONFIG_GAMEPORT_NS558=m CONFIG_GAMEPORT_L4=m @@ -1696,30 +1382,13 @@ CONFIG_GAMEPORT_FM801=m # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_COMPUTONE is not set -CONFIG_ROCKETPORT=m -CONFIG_CYCLADES=m -# CONFIG_CYZ_INTR is not set -CONFIG_DIGIEPCA=m -# CONFIG_MOXA_INTELLIO is not set -CONFIG_MOXA_SMARTIO=m -# CONFIG_MOXA_SMARTIO_NEW is not set -# CONFIG_ISI is not set -CONFIG_SYNCLINKMP=m -CONFIG_SYNCLINK_GT=m -CONFIG_N_HDLC=m -# CONFIG_RISCOM8 is not set -CONFIG_SPECIALIX=m -# CONFIG_SPECIALIX_RTSCTS is not set -CONFIG_SX=m -# CONFIG_RIO is not set -CONFIG_STALDRV=y -# CONFIG_STALLION is not set -# CONFIG_ISTALLION is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -1741,161 +1410,128 @@ CONFIG_SERIAL_8250_RSA=y # CONFIG_SERIAL_CORE=m CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -CONFIG_PRINTER=m -# CONFIG_LP_CONSOLE is not set -CONFIG_PPDEV=m -CONFIG_TIPAR=m -CONFIG_IPMI_HANDLER=m -# CONFIG_IPMI_PANIC_EVENT is not set -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -CONFIG_SOFT_WATCHDOG=m -# CONFIG_WDT_MTX1 is not set - -# -# PCI-based Watchdog Cards -# -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m -CONFIG_WDT_501_PCI=y - -# -# USB-based Watchdog Cards -# -CONFIG_USBPCWATCHDOG=m +# CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -CONFIG_RTC=y -CONFIG_R3964=m -CONFIG_APPLICOM=m -CONFIG_DRM=m -CONFIG_DRM_TDFX=m -CONFIG_DRM_R128=m -CONFIG_DRM_RADEON=m -CONFIG_DRM_MGA=m -CONFIG_DRM_VIA=m -CONFIG_DRM_SAVAGE=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set # # PCMCIA character devices # -CONFIG_SYNCLINK_CS=m -CONFIG_CARDMAN_4000=m -CONFIG_CARDMAN_4040=m -CONFIG_RAW_DRIVER=m -CONFIG_MAX_RAW_DEVS=256 -CONFIG_TCG_TPM=m -CONFIG_TCG_ATMEL=m +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m # -# I2C Algorithms +# I2C Hardware Bus support # -CONFIG_I2C_ALGOBIT=m -CONFIG_I2C_ALGOPCF=m -CONFIG_I2C_ALGOPCA=m # -# I2C Hardware Bus support +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) # -CONFIG_I2C_ALI1535=m -CONFIG_I2C_ALI1563=m -CONFIG_I2C_ALI15X3=m -CONFIG_I2C_AMD756=m -CONFIG_I2C_AMD756_S4882=m -CONFIG_I2C_AMD8111=m -CONFIG_I2C_I801=m -CONFIG_I2C_I810=m -CONFIG_I2C_PIIX4=m -CONFIG_I2C_NFORCE2=m -CONFIG_I2C_OCORES=m -CONFIG_I2C_PARPORT=m -CONFIG_I2C_PARPORT_LIGHT=m -CONFIG_I2C_PROSAVAGE=m -CONFIG_I2C_SAVAGE4=m +CONFIG_I2C_GPIO=m +# CONFIG_I2C_OCORES is not set # CONFIG_I2C_SIMTEC is not set -CONFIG_I2C_SIS5595=m -CONFIG_I2C_SIS630=m -CONFIG_I2C_SIS96X=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set -CONFIG_I2C_STUB=m # CONFIG_I2C_TINY_USB is not set -CONFIG_I2C_VIA=m -CONFIG_I2C_VIAPRO=m -CONFIG_I2C_VOODOO3=m # -# Miscellaneous I2C Chip support +# Other I2C/SMBus bus drivers # -CONFIG_SENSORS_DS1337=m -CONFIG_SENSORS_DS1374=m -# CONFIG_DS1682 is not set -CONFIG_EEPROM_LEGACY=m -CONFIG_SENSORS_PCF8574=m -CONFIG_SENSORS_PCA9539=m -CONFIG_SENSORS_PCF8591=m -CONFIG_EEPROM_MAX6875=m -# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set # -# SPI support +# PPS support # -CONFIG_SPI=y -CONFIG_SPI_MASTER=y +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y # -# SPI Master Controller Drivers +# Memory mapped GPIO expanders: # -CONFIG_SPI_BITBANG=m -CONFIG_SPI_BUTTERFLY=m -# CONFIG_SPI_LM70_LLP is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set # -# SPI Protocol Masters +# I2C GPIO expanders: # -# CONFIG_EEPROM_AT25 is not set -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_W1=m -CONFIG_W1_CON=y +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # -# 1-wire Bus Masters +# PCI GPIO expanders: # -CONFIG_W1_MASTER_MATROX=m -CONFIG_W1_MASTER_DS2490=m -CONFIG_W1_MASTER_DS2482=m +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set # -# 1-wire Slaves +# SPI GPIO expanders: # -CONFIG_W1_SLAVE_THERM=m -CONFIG_W1_SLAVE_SMEM=m -CONFIG_W1_SLAVE_DS2433=m -# CONFIG_W1_SLAVE_DS2433_CRC is not set -# CONFIG_W1_SLAVE_DS2760 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y CONFIG_HWMON_VID=m -CONFIG_SENSORS_ABITUGURU=m -# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m @@ -1903,17 +1539,23 @@ CONFIG_SENSORS_ADM1026=m # CONFIG_SENSORS_ADM1029 is not set CONFIG_SENSORS_ADM1031=m CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ASB100=m +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set CONFIG_SENSORS_ATXP1=m CONFIG_SENSORS_DS1621=m +# CONFIG_SENSORS_I5K_AMB is not set CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_FSCHER=m -CONFIG_SENSORS_FSCPOS=m +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set CONFIG_SENSORS_GL518SM=m CONFIG_SENSORS_GL520SM=m CONFIG_SENSORS_IT87=m CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m +# CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM77=m CONFIG_SENSORS_LM78=m @@ -1924,16 +1566,25 @@ CONFIG_SENSORS_LM87=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM92=m # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set CONFIG_SENSORS_MAX1619=m # CONFIG_SENSORS_MAX6650 is not set CONFIG_SENSORS_PC87360=m # CONFIG_SENSORS_PC87427 is not set +CONFIG_SENSORS_PCF8591=m +# CONFIG_SENSORS_SHT15 is not set CONFIG_SENSORS_SIS5595=m # CONFIG_SENSORS_DME1737 is not set CONFIG_SENSORS_SMSC47M1=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47B397=m +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set CONFIG_SENSORS_VIA686A=m CONFIG_SENSORS_VT1211=m CONFIG_SENSORS_VT8231=m @@ -1942,370 +1593,94 @@ CONFIG_SENSORS_W83791D=m CONFIG_SENSORS_W83792D=m # CONFIG_SENSORS_W83793 is not set CONFIG_SENSORS_W83L785TS=m +# CONFIG_SENSORS_W83L786NG is not set CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_TVAUDIO=m -CONFIG_VIDEO_TDA7432=m -CONFIG_VIDEO_TDA9840=m -CONFIG_VIDEO_TDA9875=m -CONFIG_VIDEO_TEA6415C=m -CONFIG_VIDEO_TEA6420=m -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_BT819=m -CONFIG_VIDEO_BT856=m -CONFIG_VIDEO_KS0127=m -CONFIG_VIDEO_SAA7110=m -CONFIG_VIDEO_SAA7111=m -CONFIG_VIDEO_SAA7114=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_TVP5150=m -CONFIG_VIDEO_VPX3220=m -CONFIG_VIDEO_CX25840=m -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_SAA7185=m -CONFIG_VIDEO_ADV7170=m -CONFIG_VIDEO_ADV7175=m -CONFIG_VIDEO_VIVI=m -CONFIG_VIDEO_BT848=m -CONFIG_VIDEO_BT848_DVB=y -CONFIG_VIDEO_SAA6588=m -CONFIG_VIDEO_BWQCAM=m -CONFIG_VIDEO_CQCAM=m -CONFIG_VIDEO_W9966=m -CONFIG_VIDEO_CPIA=m -CONFIG_VIDEO_CPIA_PP=m -CONFIG_VIDEO_CPIA_USB=m -CONFIG_VIDEO_CPIA2=m -CONFIG_VIDEO_SAA5246A=m -CONFIG_VIDEO_SAA5249=m -CONFIG_TUNER_3036=m -# CONFIG_TUNER_TEA5761 is not set -CONFIG_VIDEO_STRADIS=m -CONFIG_VIDEO_ZORAN_ZR36060=m -CONFIG_VIDEO_ZORAN=m -CONFIG_VIDEO_ZORAN_BUZ=m -CONFIG_VIDEO_ZORAN_DC10=m -CONFIG_VIDEO_ZORAN_DC30=m -CONFIG_VIDEO_ZORAN_LML33=m -CONFIG_VIDEO_ZORAN_LML33R10=m -CONFIG_VIDEO_ZORAN_AVS6EYES=m -CONFIG_VIDEO_SAA7134=m -CONFIG_VIDEO_SAA7134_ALSA=m -CONFIG_VIDEO_SAA7134_OSS=m -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_DPC=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_CX88=m -CONFIG_VIDEO_CX88_ALSA=m -CONFIG_VIDEO_CX88_BLACKBIRD=m -CONFIG_VIDEO_CX88_DVB=m -CONFIG_VIDEO_CX88_VP3054=m -# CONFIG_VIDEO_IVTV is not set -# CONFIG_VIDEO_CAFE_CCIC is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_29XXX=y -CONFIG_VIDEO_PVRUSB2_24XXX=y -CONFIG_VIDEO_PVRUSB2_SYSFS=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_EM28XX=m -# CONFIG_VIDEO_USBVISION is not set -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -# CONFIG_USB_OV511 is not set -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -# CONFIG_USB_ZR364XX is not set -CONFIG_RADIO_ADAPTERS=y -CONFIG_RADIO_GEMTEK_PCI=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_MAESTRO=m -CONFIG_USB_DSBR=m -CONFIG_DVB_CORE=m -CONFIG_DVB_CORE_ATTACH=y -CONFIG_DVB_CAPTURE_DRIVERS=y - -# -# Supported SAA7146 based PCI Adapters -# -CONFIG_DVB_AV7110=m -CONFIG_DVB_AV7110_OSD=y -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_CI=m -CONFIG_DVB_BUDGET_AV=m -CONFIG_DVB_BUDGET_PATCH=m - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -# CONFIG_DVB_USB_M920X is not set -# CONFIG_DVB_USB_GL861 is not set -# CONFIG_DVB_USB_AU6610 is not set -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -# CONFIG_DVB_USB_TTUSB2 is not set -CONFIG_DVB_USB_DTT200U=m -# CONFIG_DVB_USB_OPERA1 is not set -# CONFIG_DVB_USB_AF9005 is not set -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_DVB_CINERGYT2=m -CONFIG_DVB_CINERGYT2_TUNING=y -CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32 -CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512 -CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250 -CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y -CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100 - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported BT878 Adapters -# -CONFIG_DVB_BT8XX=m - -# -# Supported Pluto2 Adapters -# -CONFIG_DVB_PLUTO2=m - -# -# Supported DVB Frontends -# - -# -# Customise DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set - -# -# DVB-S (satellite) frontends -# -CONFIG_DVB_STV0299=m -CONFIG_DVB_CX24110=m -CONFIG_DVB_CX24123=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_MT312=m -CONFIG_DVB_VES1X93=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_TDA10086=m +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y # -# DVB-T (terrestrial) frontends +# Watchdog Device Drivers # -CONFIG_DVB_SP8870=m -CONFIG_DVB_SP887X=m -CONFIG_DVB_CX22700=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_L64781=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_WDT_MTX1=y # -# DVB-C (cable) frontends +# PCI-based Watchdog Cards # -CONFIG_DVB_VES1820=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# USB-based Watchdog Cards # -CONFIG_DVB_NXT200X=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # -# Tuners/PLL support +# Sonics Silicon Backplane # -CONFIG_DVB_PLL=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_TDA827X=m -# CONFIG_DVB_TUNER_QT1010 is not set -CONFIG_DVB_TUNER_MT2060=m +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_SDIOHOST_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set # -# Miscellaneous devices +# Multifunction device drivers # -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_TUA6100=m -CONFIG_VIDEO_SAA7146=m -CONFIG_VIDEO_SAA7146_VV=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_BUF=m -CONFIG_VIDEO_BUF_DVB=m -CONFIG_VIDEO_BTCX=m -CONFIG_VIDEO_IR_I2C=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS65010 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -CONFIG_VGASTATE=m -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_DDC=m -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_SYS_FOPS is not set -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -CONFIG_FB_BACKLIGHT=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y - -# -# Frame buffer hardware drivers -# -CONFIG_FB_CIRRUS=m -CONFIG_FB_PM2=m -CONFIG_FB_PM2_FIFO_DISCONNECT=y -CONFIG_FB_CYBER2000=m -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -CONFIG_FB_S1D13XXX=m -CONFIG_FB_NVIDIA=m -CONFIG_FB_NVIDIA_I2C=y -# CONFIG_FB_NVIDIA_DEBUG is not set -CONFIG_FB_NVIDIA_BACKLIGHT=y -CONFIG_FB_RIVA=m -CONFIG_FB_RIVA_I2C=y -# CONFIG_FB_RIVA_DEBUG is not set -CONFIG_FB_RIVA_BACKLIGHT=y -CONFIG_FB_MATROX=m -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_FB_MATROX_G=y -CONFIG_FB_MATROX_I2C=m -CONFIG_FB_MATROX_MAVEN=m -CONFIG_FB_MATROX_MULTIHEAD=y -CONFIG_FB_RADEON=m -CONFIG_FB_RADEON_I2C=y -CONFIG_FB_RADEON_BACKLIGHT=y -# CONFIG_FB_RADEON_DEBUG is not set -CONFIG_FB_ATY128=m -CONFIG_FB_ATY128_BACKLIGHT=y -CONFIG_FB_ATY=m -CONFIG_FB_ATY_CT=y -CONFIG_FB_ATY_GENERIC_LCD=y -CONFIG_FB_ATY_GX=y -CONFIG_FB_ATY_BACKLIGHT=y -# CONFIG_FB_S3 is not set -CONFIG_FB_SAVAGE=m -CONFIG_FB_SAVAGE_I2C=y -CONFIG_FB_SAVAGE_ACCEL=y -CONFIG_FB_SIS=m -CONFIG_FB_SIS_300=y -CONFIG_FB_SIS_315=y -CONFIG_FB_NEOMAGIC=m -CONFIG_FB_KYRO=m -CONFIG_FB_3DFX=m -# CONFIG_FB_3DFX_ACCEL is not set -CONFIG_FB_VOODOO1=m -# CONFIG_FB_VT8623 is not set -CONFIG_FB_TRIDENT=m -# CONFIG_FB_TRIDENT_ACCEL is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_VIRTUAL is not set # # Console display driver support # -CONFIG_VGA_CONSOLE=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set +# CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=m -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set - -# -# Sound -# CONFIG_SOUND=m - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -2318,32 +1693,29 @@ CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_RTCTIMER=m -CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# +CONFIG_SND_VMASTER=y +CONFIG_SND_RAWMIDI_SEQ=m +CONFIG_SND_OPL3_LIB_SEQ=m +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +CONFIG_SND_EMU10K1_SEQ=m CONFIG_SND_MPU401_UART=m CONFIG_SND_OPL3_LIB=m CONFIG_SND_VX_LIB=m CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y CONFIG_SND_DUMMY=m CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m -CONFIG_SND_MTS64=m CONFIG_SND_SERIAL_U16550=m CONFIG_SND_MPU401=m -# CONFIG_SND_PORTMAN2X4 is not set - -# -# PCI devices -# +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y CONFIG_SND_AD1889=m CONFIG_SND_ALS300=m CONFIG_SND_ALI5451=m @@ -2352,14 +1724,18 @@ CONFIG_SND_ATIIXP_MODEM=m CONFIG_SND_AU8810=m CONFIG_SND_AU8820=m CONFIG_SND_AU8830=m +# CONFIG_SND_AW2 is not set CONFIG_SND_AZT3328=m CONFIG_SND_BT87X=m # CONFIG_SND_BT87X_OVERCLOCK is not set CONFIG_SND_CA0106=m CONFIG_SND_CMIPCI=m +# CONFIG_SND_OXYGEN is not set CONFIG_SND_CS4281=m CONFIG_SND_CS46XX=m CONFIG_SND_CS46XX_NEW_DSP=y +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set CONFIG_SND_DARLA20=m CONFIG_SND_GINA20=m CONFIG_SND_LAYLA20=m @@ -2372,6 +1748,8 @@ CONFIG_SND_ECHO3G=m CONFIG_SND_INDIGO=m CONFIG_SND_INDIGOIO=m CONFIG_SND_INDIGODJ=m +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set CONFIG_SND_EMU10K1=m CONFIG_SND_EMU10K1X=m CONFIG_SND_ENS1370=m @@ -2379,19 +1757,36 @@ CONFIG_SND_ENS1371=m CONFIG_SND_ES1938=m CONFIG_SND_ES1968=m CONFIG_SND_FM801=m -CONFIG_SND_FM801_TEA575X_BOOL=y -CONFIG_SND_FM801_TEA575X=m CONFIG_SND_HDA_INTEL=m +# CONFIG_SND_HDA_HWDEP is not set +# CONFIG_SND_HDA_INPUT_BEEP is not set +# CONFIG_SND_HDA_INPUT_JACK is not set +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_CODEC_REALTEK=y +CONFIG_SND_HDA_CODEC_ANALOG=y +CONFIG_SND_HDA_CODEC_SIGMATEL=y +CONFIG_SND_HDA_CODEC_VIA=y +CONFIG_SND_HDA_CODEC_ATIHDMI=y +CONFIG_SND_HDA_CODEC_NVHDMI=y +CONFIG_SND_HDA_CODEC_INTELHDMI=y +CONFIG_SND_HDA_ELD=y +CONFIG_SND_HDA_CODEC_CIRRUS=y +CONFIG_SND_HDA_CODEC_CONEXANT=y +CONFIG_SND_HDA_CODEC_CA0110=y +CONFIG_SND_HDA_CODEC_CMEDIA=y +CONFIG_SND_HDA_CODEC_SI3054=y +CONFIG_SND_HDA_GENERIC=y +# CONFIG_SND_HDA_POWER_SAVE is not set CONFIG_SND_HDSP=m CONFIG_SND_HDSPM=m +# CONFIG_SND_HIFIER is not set CONFIG_SND_ICE1712=m CONFIG_SND_ICE1724=m CONFIG_SND_INTEL8X0=m CONFIG_SND_INTEL8X0M=m CONFIG_SND_KORG1212=m -CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y +# CONFIG_SND_LX6464ES is not set CONFIG_SND_MAESTRO3=m -CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y CONFIG_SND_MIXART=m CONFIG_SND_NM256=m CONFIG_SND_PCXHR=m @@ -2403,55 +1798,30 @@ CONFIG_SND_SONICVIBES=m CONFIG_SND_TRIDENT=m CONFIG_SND_VIA82XX=m CONFIG_SND_VIA82XX_MODEM=m +# CONFIG_SND_VIRTUOSO is not set CONFIG_SND_VX222=m CONFIG_SND_YMFPCI=m -CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y -# CONFIG_SND_AC97_POWER_SAVE is not set - -# -# ALSA MIPS devices -# +CONFIG_SND_MIPS=y # CONFIG_SND_AU1X00 is not set - -# -# USB devices -# +CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set - -# -# PCMCIA devices -# +CONFIG_SND_PCMCIA=y CONFIG_SND_VXPOCKET=m CONFIG_SND_PDAUDIOCF=m - -# -# System on Chip audio support -# # CONFIG_SND_SOC is not set - -# -# SoC Audio support for SuperH -# - -# -# Open Sound System -# CONFIG_SOUND_PRIME=m -CONFIG_SOUND_TRIDENT=m -# CONFIG_SOUND_MSNDCLAS is not set -# CONFIG_SOUND_MSNDPIN is not set CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y -# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=m -CONFIG_USB_HIDINPUT_POWERBOOK=y -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y # @@ -2459,12 +1829,50 @@ CONFIG_USB_HIDDEV=y # CONFIG_USB_KBD=m CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options @@ -2472,19 +1880,27 @@ CONFIG_USB=m CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_PERSIST is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=m +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_SPLIT_ISO=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_HCD_SSB is not set # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -2493,32 +1909,38 @@ CONFIG_USB_U132_HCD=m CONFIG_USB_SL811_HCD=m CONFIG_USB_SL811_CS=m # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set # # USB Device Class drivers # CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# may also be needed; see USB_STORAGE Help for more information +# also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +# CONFIG_USB_STORAGE_ONETOUCH is not set +CONFIG_USB_STORAGE_KARMA=m +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set CONFIG_USB_LIBUSUAL=y # @@ -2526,25 +1948,20 @@ CONFIG_USB_LIBUSUAL=y # CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m -CONFIG_USB_MON=y # # USB port drivers # -CONFIG_USB_USS720=m - -# -# USB Serial Converter support -# CONFIG_USB_SERIAL=m +CONFIG_USB_EZUSB=y CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_AIRPRIME=m CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_BELKIN=m +# CONFIG_USB_SERIAL_CH341 is not set CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP2101=m +# CONFIG_USB_SERIAL_CP210X is not set CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m @@ -2556,6 +1973,7 @@ CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_GARMIN=m CONFIG_USB_SERIAL_IPW=m +# CONFIG_USB_SERIAL_IUU is not set CONFIG_USB_SERIAL_KEYSPAN_PDA=m CONFIG_USB_SERIAL_KEYSPAN=m # CONFIG_USB_SERIAL_KEYSPAN_MPR is not set @@ -2575,20 +1993,27 @@ CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_MOS7720=m CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MOTOROLA is not set CONFIG_USB_SERIAL_NAVMAN=m CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_SAFE=m # CONFIG_USB_SERIAL_SAFE_PADDED is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set CONFIG_USB_SERIAL_SIERRAWIRELESS=m +# CONFIG_USB_SERIAL_SYMBOL is not set CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_DEBUG is not set -CONFIG_USB_EZUSB=y # # USB Miscellaneous drivers @@ -2596,18 +2021,13 @@ CONFIG_USB_EZUSB=y CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m CONFIG_USB_ADUTUX=m -CONFIG_USB_AUERSWALD=m +# CONFIG_USB_SEVSEG is not set CONFIG_USB_RIO500=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m -# CONFIG_USB_BERRY_CHARGE is not set CONFIG_USB_LED=m CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m -CONFIG_USB_PHIDGET=m -CONFIG_USB_PHIDGETKIT=m -CONFIG_USB_PHIDGETMOTORCONTROL=m -CONFIG_USB_PHIDGETSERVO=m CONFIG_USB_IDMOUSE=m CONFIG_USB_FTDI_ELAN=m CONFIG_USB_APPLEDISPLAY=m @@ -2617,86 +2037,113 @@ CONFIG_USB_LD=m CONFIG_USB_TRANCEVIBRATOR=m # CONFIG_USB_IOWARRIOR is not set CONFIG_USB_TEST=m - -# -# USB DSL modem support -# +# CONFIG_USB_ISIGHTFW is not set CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m - -# -# USB Gadget Support -# CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -CONFIG_USB_GADGET_NET2280=y -CONFIG_USB_NET2280=m -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set CONFIG_USB_GADGETFS=m CONFIG_USB_FILE_STORAGE=m # CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set CONFIG_USB_G_SERIAL=m CONFIG_USB_MIDI_GADGET=m +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set CONFIG_MMC=m # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=m +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SDRICOH_CS is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m +CONFIG_LEDS_CLASS=y # # LED drivers # +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -# CONFIG_LEDS_TRIGGERS is not set -CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_MAD=m -CONFIG_INFINIBAND_USER_ACCESS=m -CONFIG_INFINIBAND_USER_MEM=y -CONFIG_INFINIBAND_ADDR_TRANS=y -CONFIG_INFINIBAND_MTHCA=m -CONFIG_INFINIBAND_MTHCA_DEBUG=y -CONFIG_INFINIBAND_AMSO1100=m -CONFIG_INFINIBAND_AMSO1100_DEBUG=y -# CONFIG_MLX4_INFINIBAND is not set -CONFIG_INFINIBAND_IPOIB=m -# CONFIG_INFINIBAND_IPOIB_CM is not set -CONFIG_INFINIBAND_IPOIB_DEBUG=y -# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set -CONFIG_INFINIBAND_SRP=m -CONFIG_INFINIBAND_ISER=m -CONFIG_RTC_LIB=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=m # @@ -2712,6 +2159,7 @@ CONFIG_RTC_DRV_TEST=m # I2C RTC drivers # CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1374 is not set CONFIG_RTC_DRV_DS1672=m # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_RS5C372=m @@ -2720,48 +2168,45 @@ CONFIG_RTC_DRV_X1205=m CONFIG_RTC_DRV_PCF8563=m CONFIG_RTC_DRV_PCF8583=m # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers # -CONFIG_RTC_DRV_RS5C348=m -CONFIG_RTC_DRV_MAX6902=m # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set CONFIG_RTC_DRV_DS1553=m -# CONFIG_RTC_DRV_STK17TA8 is not set CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_STK17TA8 is not set CONFIG_RTC_DRV_M48T86=m +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set CONFIG_RTC_DRV_V3020=m # # on-CPU RTC drivers # - -# -# DMA Engine support -# -CONFIG_DMA_ENGINE=y - -# -# DMA Clients -# -CONFIG_NET_DMA=y - -# -# DMA Devices -# -CONFIG_INTEL_IOATDMA=m +# CONFIG_RTC_DRV_AU1XXX is not set +# CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # -# Userspace I/O +# TI VLYNQ # -# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -2772,44 +2217,43 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=m -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -CONFIG_JFS_STATISTICS=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y +# CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -CONFIG_MINIX_FS=m -CONFIG_ROMFS_FS=m +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=m -CONFIG_AUTOFS4_FS=m +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems @@ -2838,73 +2282,79 @@ CONFIG_NTFS_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y -CONFIG_VXFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y +# CONFIG_NFS_V4_1 is not set CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set CONFIG_NFSD_V4=y -CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=m CONFIG_RPCSEC_GSS_SPKM3=m CONFIG_SMB_FS=m # CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CEPH_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CIFS_EXPERIMENTAL is not set CONFIG_NCP_FS=m CONFIG_NCPFS_PACKET_SIGNING=y @@ -2916,7 +2366,6 @@ CONFIG_NCPFS_OS2_NS=y CONFIG_NCPFS_NLS=y CONFIG_NCPFS_EXTRAS=y CONFIG_CODA_FS=m -# CONFIG_CODA_FS_OLD_API is not set CONFIG_AFS_FS=m # CONFIG_AFS_DEBUG is not set @@ -2948,10 +2397,6 @@ CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=m @@ -2992,118 +2437,179 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -CONFIG_PROFILING=y -CONFIG_OPROFILE=m +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y # CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set +CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set +# CONFIG_SPINLOCK_TEST is not set # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_DEBUG_PROC_KEYS is not set -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -CONFIG_SECURITY_CAPABILITIES=m -CONFIG_SECURITY_ROOTPLUG=m -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 -CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y -CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set -# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set -CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=m -# CONFIG_CRYPTO_FCRYPT is not set -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_CAMELLIA is not set -CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m CONFIG_CRC16=m -# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_AUDIT_GENERIC=y CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=m -CONFIG_REED_SOLOMON=m -CONFIG_REED_SOLOMON_DEC16=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_CHECK_SIGNATURE=y +CONFIG_NLATTR=y diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index 57a50483abdf..90a032af95ce 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25 -# Mon Apr 28 12:24:17 2008 +# Linux kernel version: 2.6.34-rc6 +# Sat May 1 11:49:51 2010 # CONFIG_MIPS=y @@ -9,22 +9,25 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set # CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set @@ -38,11 +41,14 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set CONFIG_MIKROTIK_RB532=y -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -53,14 +59,15 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_HOTPLUG_CPU is not set +CONFIG_NEED_DMA_MAP_STATE=y # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set @@ -73,7 +80,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=4 # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -86,6 +94,7 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -93,11 +102,13 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -107,11 +118,13 @@ CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y @@ -124,12 +137,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -151,6 +165,7 @@ CONFIG_PREEMPT_NONE=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -168,23 +183,31 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_PREEMPT_RCU is not set +CONFIG_TINY_RCU=y +# CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y # CONFIG_KALLSYMS is not set @@ -192,54 +215,87 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set -CONFIG_COMPAT_BRK=y +CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# # CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_PCI_QUIRKS is not set +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -CONFIG_PROC_PAGE_MONITOR=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set CONFIG_IOSCHED_DEADLINE=y # CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_AS is not set CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" -CONFIG_CLASSIC_RCU=y +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -248,7 +304,8 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -257,25 +314,22 @@ CONFIG_MMU=y # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -325,7 +379,6 @@ CONFIG_DEFAULT_VEGAS=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="vegas" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y @@ -336,8 +389,9 @@ CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration # +CONFIG_NETFILTER_NETLINK=m # CONFIG_NETFILTER_NETLINK_QUEUE is not set -# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NF_CONNTRACK=y CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y @@ -355,18 +409,23 @@ CONFIG_NF_CONNTRACK_IRC=m # CONFIG_NF_CONNTRACK_SIP is not set CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=y # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set CONFIG_NETFILTER_XT_TARGET_TRACE=m # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -375,18 +434,21 @@ CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_DCCP=m # CONFIG_NETFILTER_XT_MATCH_DSCP is not set # CONFIG_NETFILTER_XT_MATCH_ESP is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m # CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set CONFIG_NETFILTER_XT_MATCH_LIMIT=y # CONFIG_NETFILTER_XT_MATCH_MAC is not set # CONFIG_NETFILTER_XT_MATCH_MARK is not set -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=y # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set @@ -394,20 +456,21 @@ CONFIG_NETFILTER_XT_MATCH_STATE=y # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=y -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_ECN is not set +CONFIG_IP_NF_MATCH_ADDRTYPE=m # CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set # CONFIG_IP_NF_MATCH_TTL is not set -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y # CONFIG_IP_NF_TARGET_LOG is not set @@ -415,8 +478,8 @@ CONFIG_IP_NF_TARGET_REJECT=y CONFIG_NF_NAT=y CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=y -# CONFIG_IP_NF_TARGET_REDIRECT is not set # CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_REDIRECT is not set # CONFIG_NF_NAT_SNMP_BASIC is not set CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m @@ -426,17 +489,22 @@ CONFIG_NF_NAT_TFTP=m # CONFIG_NF_NAT_H323 is not set # CONFIG_NF_NAT_SIP is not set CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_RAW=m # CONFIG_IP_NF_ARPTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +CONFIG_STP=y CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_DECNET is not set CONFIG_LLC=y CONFIG_LLC2=m @@ -446,6 +514,8 @@ CONFIG_LLC2=m # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # @@ -455,7 +525,7 @@ CONFIG_NET_SCH_CBQ=m # CONFIG_NET_SCH_HTB is not set # CONFIG_NET_SCH_HFSC is not set CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m +# CONFIG_NET_SCH_MULTIQ is not set # CONFIG_NET_SCH_RED is not set # CONFIG_NET_SCH_SFQ is not set # CONFIG_NET_SCH_TEQL is not set @@ -463,6 +533,7 @@ CONFIG_NET_SCH_RR=m # CONFIG_NET_SCH_GRED is not set # CONFIG_NET_SCH_DSMARK is not set CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set # CONFIG_NET_SCH_INGRESS is not set # @@ -496,8 +567,10 @@ CONFIG_NET_ACT_IPT=m # CONFIG_NET_ACT_NAT is not set CONFIG_NET_ACT_PEDIT=m # CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set CONFIG_NET_CLS_IND=y CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -514,14 +587,19 @@ CONFIG_HAMRADIO=y # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set # -# Wireless +# CFG80211 needs to be enabled for MAC80211 # -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_EXT=y -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -533,13 +611,17 @@ CONFIG_WIRELESS_EXT=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -612,6 +694,11 @@ CONFIG_MTD_NAND_PLATFORM=y # CONFIG_MTD_ONENAND is not set # +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set @@ -623,23 +710,36 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # +CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y @@ -656,10 +756,6 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -676,27 +772,35 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set @@ -708,9 +812,15 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_VERBOSE_ERROR is not set # CONFIG_SATA_PMP is not set # CONFIG_SATA_AHCI is not set # CONFIG_SATA_SIL24 is not set @@ -732,6 +842,7 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_ALI is not set # CONFIG_PATA_AMD is not set # CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATP867X is not set # CONFIG_PATA_ATIIXP is not set # CONFIG_PATA_CMD640_PCI is not set # CONFIG_PATA_CMD64X is not set @@ -747,6 +858,7 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_IT821X is not set # CONFIG_PATA_IT8213 is not set # CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set # CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_MARVELL is not set # CONFIG_PATA_MPIIX is not set @@ -757,29 +869,39 @@ CONFIG_ATA_SFF=y # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set CONFIG_PATA_RB532=y +# CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set CONFIG_IFB=m # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -797,21 +919,28 @@ CONFIG_KORINA=y # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_KSZ884X_PCI is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set # CONFIG_TC35815 is not set -# CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set @@ -821,30 +950,27 @@ CONFIG_NET_PCI=y # CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set CONFIG_VIA_RHINE=y # CONFIG_VIA_RHINE_MMIO is not set -CONFIG_VIA_RHINE_NAPI=y # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_LIBERTAS is not set -# CONFIG_HERMES is not set +CONFIG_WLAN=y CONFIG_ATMEL=m # CONFIG_PCI_ATMEL is not set # CONFIG_PRISM54 is not set -# CONFIG_IWLWIFI_LEDS is not set # CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -864,6 +990,7 @@ CONFIG_SLHC=m # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -872,7 +999,8 @@ CONFIG_SLHC=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -887,17 +1015,29 @@ CONFIG_INPUT=y # CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_PCSPKR is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +CONFIG_INPUT_RB532_BUTTON=y # # Hardware I/O ports @@ -909,6 +1049,7 @@ CONFIG_INPUT_KEYBOARD=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -928,105 +1069,95 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_TIMBERDALE is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -# CONFIG_RTC is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set # -# Watchdog Device Drivers +# PPS support # -# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y # -# PCI-based Watchdog Cards +# Memory mapped GPIO expanders: # -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_SCH is not set # -# Sonics Silicon Backplane +# I2C GPIO expanders: # -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set # -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set - -# -# Multimedia devices -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set - -# -# Encoders/decoders and other helper chips +# PCI GPIO expanders: # +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set # -# Audio decoders +# SPI GPIO expanders: # # -# Video decoders +# AC97 GPIO expanders: # +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y # -# Video and audio decoders +# Watchdog Device Drivers # +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_RC32434_WDT=y # -# MPEG video encoders +# PCI-based Watchdog Cards # -# CONFIG_VIDEO_CX2341X is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set +CONFIG_SSB_POSSIBLE=y # -# Video encoders +# Sonics Silicon Backplane # +# CONFIG_SSB is not set # -# Video improvement chips +# Multifunction device drivers # -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_STRADIS is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # +# CONFIG_VGA_ARB is not set # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set @@ -1037,13 +1168,10 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y # CONFIG_HID is not set +# CONFIG_HID_PID is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1053,9 +1181,18 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_OTG_BLACKLIST_HUB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -1064,41 +1201,67 @@ CONFIG_LEDS_CLASS=y # # LED drivers # +CONFIG_LEDS_MIKROTIK_RB532=y # CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers # -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -1117,15 +1280,13 @@ CONFIG_EXT2_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=y - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1148,9 +1309,14 @@ CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -1160,6 +1326,7 @@ CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set @@ -1198,11 +1365,22 @@ CONFIG_ENABLE_WARN_DEPRECATED=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y # CONFIG_CMDLINE_BOOL is not set # @@ -1210,18 +1388,32 @@ CONFIG_FRAME_WARN=1024 # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=m +CONFIG_CRYPTO_BLKCIPHER2=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH2=m +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=m # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=m # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set CONFIG_CRYPTO_TEST=m @@ -1249,14 +1441,20 @@ CONFIG_CRYPTO_TEST=m # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # -# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1266,7 +1464,7 @@ CONFIG_CRYPTO_TEST=m # # Ciphers # -# CONFIG_CRYPTO_AES is not set +CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set @@ -1286,27 +1484,36 @@ CONFIG_CRYPTO_TEST=m # Compression # # CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_ZLIB=y # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m # CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index ae07423e6e82..e76941db2312 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -190,8 +190,6 @@ extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ void au1xxx_save_and_sleep(void); void au_sleep(void); -void save_au1xxx_intctl(void); -void restore_au1xxx_intctl(void); /* SOC Interrupt numbers */ @@ -835,6 +833,38 @@ enum soc_au1200_ints { #define MEM_STNAND_DATA 0x20 #endif + +/* Interrupt Controller register offsets */ +#define IC_CFG0RD 0x40 +#define IC_CFG0SET 0x40 +#define IC_CFG0CLR 0x44 +#define IC_CFG1RD 0x48 +#define IC_CFG1SET 0x48 +#define IC_CFG1CLR 0x4C +#define IC_CFG2RD 0x50 +#define IC_CFG2SET 0x50 +#define IC_CFG2CLR 0x54 +#define IC_REQ0INT 0x54 +#define IC_SRCRD 0x58 +#define IC_SRCSET 0x58 +#define IC_SRCCLR 0x5C +#define IC_REQ1INT 0x5C +#define IC_ASSIGNRD 0x60 +#define IC_ASSIGNSET 0x60 +#define IC_ASSIGNCLR 0x64 +#define IC_WAKERD 0x68 +#define IC_WAKESET 0x68 +#define IC_WAKECLR 0x6C +#define IC_MASKRD 0x70 +#define IC_MASKSET 0x70 +#define IC_MASKCLR 0x74 +#define IC_RISINGRD 0x78 +#define IC_RISINGCLR 0x78 +#define IC_FALLINGRD 0x7C +#define IC_FALLINGCLR 0x7C +#define IC_TESTBIT 0x80 + + /* Interrupt Controller 0 */ #define IC0_CFG0RD 0xB0400040 #define IC0_CFG0SET 0xB0400040 diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 8c6b1105ce0b..c8a553a36ba4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -358,10 +358,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void); -void au1xxx_dbdma_resume(void); -#endif /* * Flags for the put_source/put_dest functions. diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 43d4da0b1e9f..3999ec0aa7f5 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -20,7 +20,7 @@ static inline unsigned long bcm63xx_gpio_count(void) } } -#define GPIO_DIR_OUT 0x0 -#define GPIO_DIR_IN 0x1 +#define BCM63XX_GPIO_DIR_OUT 0x0 +#define BCM63XX_GPIO_DIR_IN 0x1 #endif /* !BCM63XX_GPIO_H */ diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 16210cedd929..675bd8641d5a 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -52,6 +52,8 @@ #define cpu_has_tx39_cache 0 #define cpu_has_userlocal 0 #define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 diff --git a/arch/mips/include/asm/mach-loongson/gpio.h b/arch/mips/include/asm/mach-loongson/gpio.h new file mode 100644 index 000000000000..e30e73d443df --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/gpio.h @@ -0,0 +1,35 @@ +/* + * STLS2F GPIO Support + * + * Copyright (c) 2008 Richard Liu, STMicroelectronics <richard.liu@st.com> + * Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __STLS2F_GPIO_H +#define __STLS2F_GPIO_H + +#include <asm-generic/gpio.h> + +extern void gpio_set_value(unsigned gpio, int value); +extern int gpio_get_value(unsigned gpio); +extern int gpio_cansleep(unsigned gpio); + +/* The chip can do interrupt + * but it has not been tested and doc not clear + */ +static inline int gpio_to_irq(int gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(int gpio) +{ + return -EINVAL; +} + +#endif /* __STLS2F_GPIO_H */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index ab387910009a..5d33b727acf5 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -344,16 +344,10 @@ unsigned long get_wchan(struct task_struct *p); #ifdef CONFIG_CPU_HAS_PREFETCH #define ARCH_HAS_PREFETCH +#define prefetch(x) __builtin_prefetch((x), 0, 1) -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} +#define ARCH_HAS_PREFETCHW +#define prefetchw(x) __builtin_prefetch((x), 1, 1) #endif diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h index 83d69fe17c9f..9af65e79be36 100644 --- a/arch/mips/include/asm/scatterlist.h +++ b/arch/mips/include/asm/scatterlist.h @@ -1,27 +1,7 @@ #ifndef __ASM_SCATTERLIST_H #define __ASM_SCATTERLIST_H -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0x00ffffffUL) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index be5bb16be4e0..3562b854f2cd 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -125,6 +125,30 @@ static int __init wait_disable(char *s) __setup("nowait", wait_disable); +static int __cpuinitdata mips_fpu_disabled; + +static int __init fpu_disable(char *s) +{ + cpu_data[0].options &= ~MIPS_CPU_FPU; + mips_fpu_disabled = 1; + + return 1; +} + +__setup("nofpu", fpu_disable); + +int __cpuinitdata mips_dsp_disabled; + +static int __init dsp_disable(char *s) +{ + cpu_data[0].ases &= ~MIPS_ASE_DSP; + mips_dsp_disabled = 1; + + return 1; +} + +__setup("nodsp", dsp_disable); + void __init check_wait(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -982,6 +1006,12 @@ __cpuinit void cpu_probe(void) */ BUG_ON(current_cpu_type() != c->cputype); + if (mips_fpu_disabled) + c->options &= ~MIPS_CPU_FPU; + + if (mips_dsp_disabled) + c->ases &= ~MIPS_ASE_DSP; + if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c index 2f6a0b147ab8..ae5db206347c 100644 --- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c +++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c @@ -65,7 +65,7 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy, return -ENODEV; cpus_allowed = current->cpus_allowed; - set_cpus_allowed(current, cpumask_of_cpu(cpu)); + set_cpus_allowed_ptr(current, cpumask_of(cpu)); if (cpufreq_frequency_table_target (policy, &loongson2_clockmod_table[0], target_freq, relation, @@ -91,7 +91,7 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy, /* notifiers */ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - set_cpus_allowed(current, cpus_allowed); + set_cpus_allowed_ptr(current, &cpus_allowed); /* setting the cpu frequency */ clk_set_rate(cpuclk, freq); diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c index cbc6182b0065..f5981c499109 100644 --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c @@ -100,10 +100,10 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, if (test_ti_thread_flag(ti, TIF_FPUBOUND) && cpus_intersects(new_mask, mt_fpu_cpumask)) { cpus_and(effective_mask, new_mask, mt_fpu_cpumask); - retval = set_cpus_allowed(p, effective_mask); + retval = set_cpus_allowed_ptr(p, &effective_mask); } else { clear_ti_thread_flag(ti, TIF_FPUBOUND); - retval = set_cpus_allowed(p, new_mask); + retval = set_cpus_allowed_ptr(p, &new_mask); } out_unlock: diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index f9513f9e61d3..85aef3fc6716 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -569,27 +569,6 @@ void __init setup_arch(char **cmdline_p) plat_smp_setup(); } -static int __init fpu_disable(char *s) -{ - int i; - - for (i = 0; i < NR_CPUS; i++) - cpu_data[i].options &= ~MIPS_CPU_FPU; - - return 1; -} - -__setup("nofpu", fpu_disable); - -static int __init dsp_disable(char *s) -{ - cpu_data[0].ases &= ~MIPS_ASE_DSP; - - return 1; -} - -__setup("nodsp", dsp_disable); - unsigned long kernelsp[NR_CPUS]; unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 950bde8813fc..8bdd6a663c7f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -867,7 +867,7 @@ static void mt_ase_fp_affinity(void) = current->cpus_allowed; cpus_and(tmask, current->cpus_allowed, mt_fpu_cpumask); - set_cpus_allowed(current, tmask); + set_cpus_allowed_ptr(current, &tmask); set_thread_flag(TIF_FPUBOUND); } } diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S index efb95f2609c2..e0ecda92c40a 100644 --- a/arch/mips/lasat/image/head.S +++ b/arch/mips/lasat/image/head.S @@ -1,7 +1,7 @@ #include <asm/lasat/head.h> .text - .section .text.start, "ax" + .section .text..start, "ax" .set noreorder .set mips3 diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal index 988f8ad189cb..0864c963e188 100644 --- a/arch/mips/lasat/image/romscript.normal +++ b/arch/mips/lasat/image/romscript.normal @@ -4,7 +4,7 @@ SECTIONS { .text : { - *(.text.start) + *(.text..start) } /* Data in ROM */ diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 7668c4de1151..cdd2e812ba1a 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -4,6 +4,7 @@ obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ pci.o bonito-irq.o mem.o machtype.o platform.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o # # Serial port support diff --git a/arch/mips/loongson/common/gpio.c b/arch/mips/loongson/common/gpio.c new file mode 100644 index 000000000000..e8a0ffa935b4 --- /dev/null +++ b/arch/mips/loongson/common/gpio.c @@ -0,0 +1,139 @@ +/* + * STLS2F GPIO Support + * + * Copyright (c) 2008 Richard Liu, STMicroelectronics <richard.liu@st.com> + * Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/err.h> +#include <asm/types.h> +#include <loongson.h> +#include <linux/gpio.h> + +#define STLS2F_N_GPIO 4 +#define STLS2F_GPIO_IN_OFFSET 16 + +static DEFINE_SPINLOCK(gpio_lock); + +int gpio_get_value(unsigned gpio) +{ + u32 val; + u32 mask; + + if (gpio >= STLS2F_N_GPIO) + return __gpio_get_value(gpio); + + mask = 1 << (gpio + STLS2F_GPIO_IN_OFFSET); + spin_lock(&gpio_lock); + val = LOONGSON_GPIODATA; + spin_unlock(&gpio_lock); + + return ((val & mask) != 0); +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int state) +{ + u32 val; + u32 mask; + + if (gpio >= STLS2F_N_GPIO) { + __gpio_set_value(gpio, state); + return ; + } + + mask = 1 << gpio; + + spin_lock(&gpio_lock); + val = LOONGSON_GPIODATA; + if (state) + val |= mask; + else + val &= (~mask); + LOONGSON_GPIODATA = val; + spin_unlock(&gpio_lock); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_cansleep(unsigned gpio) +{ + if (gpio < STLS2F_N_GPIO) + return 0; + else + return __gpio_cansleep(gpio); +} +EXPORT_SYMBOL(gpio_cansleep); + +static int ls2f_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + u32 temp; + u32 mask; + + if (gpio >= STLS2F_N_GPIO) + return -EINVAL; + + spin_lock(&gpio_lock); + mask = 1 << gpio; + temp = LOONGSON_GPIOIE; + temp |= mask; + LOONGSON_GPIOIE = temp; + spin_unlock(&gpio_lock); + + return 0; +} + +static int ls2f_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int level) +{ + u32 temp; + u32 mask; + + if (gpio >= STLS2F_N_GPIO) + return -EINVAL; + + gpio_set_value(gpio, level); + spin_lock(&gpio_lock); + mask = 1 << gpio; + temp = LOONGSON_GPIOIE; + temp &= (~mask); + LOONGSON_GPIOIE = temp; + spin_unlock(&gpio_lock); + + return 0; +} + +static int ls2f_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static void ls2f_gpio_set_value(struct gpio_chip *chip, + unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static struct gpio_chip ls2f_chip = { + .label = "ls2f", + .direction_input = ls2f_gpio_direction_input, + .get = ls2f_gpio_get_value, + .direction_output = ls2f_gpio_direction_output, + .set = ls2f_gpio_set_value, + .base = 0, + .ngpio = STLS2F_N_GPIO, +}; + +static int __init ls2f_gpio_setup(void) +{ + return gpiochip_add(&ls2f_chip); +} +arch_initcall(ls2f_gpio_setup); diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index f2338d1c0b48..47842b7d26ae 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -354,7 +354,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; - value = (value & ~0x3) | mips_rm[value & 0x3]; + value = (value & ~FPU_CSR_RM) | + mips_rm[modeindex(value)]; #ifdef CSRTRACE printk("%p gpr[%d]<-csr=%08x\n", (void *) (xcp->cp0_epc), @@ -907,7 +908,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; + ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; rv.w = ieee754sp_tint(fs); ieee754_csr.rm = oldrm; rfmt = w_fmt; @@ -933,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; + ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; rv.l = ieee754sp_tlong(fs); ieee754_csr.rm = oldrm; rfmt = l_fmt; @@ -1081,7 +1082,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; + ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; rv.w = ieee754dp_tint(fs); ieee754_csr.rm = oldrm; rfmt = w_fmt; @@ -1107,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; + ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; rv.l = ieee754dp_tlong(fs); ieee754_csr.rm = oldrm; rfmt = l_fmt; diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index fa3bf661ae29..d0d24e047676 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -8,7 +8,6 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * */ #include <linux/init.h> #include <linux/oprofile.h> @@ -17,24 +16,18 @@ #include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */ #include "op_impl.h" -/* - * a patch should be sent to oprofile with the loongson-specific support. - * otherwise, the oprofile tool will not recognize this and complain about - * "cpu_type 'unset' is not valid". - */ #define LOONGSON2_CPU_TYPE "mips/loongson2" -#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) -#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) - -#define LOONGSON2_PERFCNT_EXL (1UL << 0) -#define LOONGSON2_PERFCNT_KERNEL (1UL << 1) -#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2) -#define LOONGSON2_PERFCNT_USER (1UL << 3) -#define LOONGSON2_PERFCNT_INT_EN (1UL << 4) #define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31) -/* Loongson2 performance counter register */ +#define LOONGSON2_PERFCTRL_EXL (1UL << 0) +#define LOONGSON2_PERFCTRL_KERNEL (1UL << 1) +#define LOONGSON2_PERFCTRL_SUPERVISOR (1UL << 2) +#define LOONGSON2_PERFCTRL_USER (1UL << 3) +#define LOONGSON2_PERFCTRL_ENABLE (1UL << 4) +#define LOONGSON2_PERFCTRL_EVENT(idx, event) \ + (((event) & 0x0f) << ((idx) ? 9 : 5)) + #define read_c0_perfctrl() __read_64bit_c0_register($24, 0) #define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val) #define read_c0_perfcnt() __read_64bit_c0_register($25, 0) @@ -49,7 +42,6 @@ static struct loongson2_register_config { static char *oprofid = "LoongsonPerf"; static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id); -/* Compute all of the registers in preparation for enabling profiling. */ static void loongson2_reg_setup(struct op_counter_config *cfg) { @@ -57,41 +49,38 @@ static void loongson2_reg_setup(struct op_counter_config *cfg) reg.reset_counter1 = 0; reg.reset_counter2 = 0; - /* Compute the performance counter ctrl word. */ - /* For now count kernel and user mode */ + + /* + * Compute the performance counter ctrl word. + * For now, count kernel and user mode. + */ if (cfg[0].enabled) { - ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event); + ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event); reg.reset_counter1 = 0x80000000ULL - cfg[0].count; } if (cfg[1].enabled) { - ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event); - reg.reset_counter2 = (0x80000000ULL - cfg[1].count); + ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event); + reg.reset_counter2 = 0x80000000ULL - cfg[1].count; } if (cfg[0].enabled || cfg[1].enabled) { - ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN; + ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE; if (cfg[0].kernel || cfg[1].kernel) - ctrl |= LOONGSON2_PERFCNT_KERNEL; + ctrl |= LOONGSON2_PERFCTRL_KERNEL; if (cfg[0].user || cfg[1].user) - ctrl |= LOONGSON2_PERFCNT_USER; + ctrl |= LOONGSON2_PERFCTRL_USER; } reg.ctrl = ctrl; reg.cnt1_enabled = cfg[0].enabled; reg.cnt2_enabled = cfg[1].enabled; - } -/* Program all of the registers in preparation for enabling profiling. */ - static void loongson2_cpu_setup(void *args) { - uint64_t perfcount; - - perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1; - write_c0_perfcnt(perfcount); + write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1); } static void loongson2_cpu_start(void *args) @@ -114,15 +103,8 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) struct pt_regs *regs = get_irq_regs(); int enabled; - /* - * LOONGSON2 defines two 32-bit performance counters. - * To avoid a race updating the registers we need to stop the counters - * while we're messing with - * them ... - */ - /* Check whether the irq belongs to me */ - enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN; + enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE; if (!enabled) return IRQ_NONE; enabled = reg.cnt1_enabled | reg.cnt2_enabled; diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c index cd5b76a1c951..3fc5d46687a9 100644 --- a/arch/mips/powertv/asic/prealloc-calliope.c +++ b/arch/mips/powertv/asic/prealloc-calliope.c @@ -22,7 +22,9 @@ */ #include <linux/init.h> +#include <linux/ioport.h> #include <asm/mach-powertv/asic.h> +#include "prealloc.h" /* * NON_DVR_CAPABLE CALLIOPE RESOURCES @@ -32,432 +34,234 @@ struct resource non_dvr_calliope_resources[] __initdata = /* * VIDEO / LX1 */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /*8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~36.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26700000-1, + IORESOURCE_MEM) + /* * Sysaudio Driver */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * STAVEM driver/STAPI */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00600000 - 1, /* 6 MB total */ - .flags = IORESOURCE_MEM, - }, + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * DOCSIS Subsystem */ - { - .name = "Docsis", - .start = 0x22000000, - .end = 0x22700000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x27500000, 0x27c00000-1, IORESOURCE_MEM) + /* * GHW HAL Driver */ - { - .name = "GraphicsHeap", - .start = 0x22700000, - .end = 0x23500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x26700000, 0x26700000+(14*1048576)-1, + IORESOURCE_MEM) + /* * multi com buffer area */ - { - .name = "MulticomSHM", - .start = 0x23700000, - .end = 0x23720000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, + IORESOURCE_MEM) + /* * DMA Ring buffer (don't need recording buffers) */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Display bins buffer for unit0 */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * PMEM */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Smartcard */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * NAND Flash */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + /* * Synopsys GMAC Memory Region */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * Add other resources here + * TFTPBuffer * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images */ - { }, -}; + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) -struct resource non_dvr_vz_calliope_resources[] __initdata = -{ /* - * VIDEO / LX1 - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2 Meg */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8k block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x22202000, - .end = 0x22C20B85 - 1, /* 10.12 Meg */ - .flags = IORESOURCE_MEM, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x20300000, - .end = 0x20620000-1, /*3.125 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x20100000, - .end = 0x20300000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x23900000, - .end = 0x23920000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash + * Add other resources here */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE+0x400 - 1, - .flags = IORESOURCE_IO, - }, + /* - * Synopsys GMAC Memory Region + * End of Resource marker */ { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, + .flags = 0, }, - /* - * Add other resources here - */ - { }, }; + struct resource non_dvr_vze_calliope_resources[] __initdata = { /* * VIDEO / LX1 */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x22000000, - .end = 0x22200000 - 1, /*2 Meg */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8k block ST231a monitor */ - .start = 0x22200000, - .end = 0x22202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x22202000, - .end = 0x22C20B85 - 1, /* 10.12 Meg */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x22000000, 0x22200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x22200000, 0x22202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (10.12MiB) */ + PREALLOC_NORMAL("MediaMemory1", 0x22202000, 0x22C20B85-1, + IORESOURCE_MEM) + /* * Sysaudio Driver */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * STAVEM driver/STAPI */ - { - .name = "AVMEMPartition0", - .start = 0x20396000, - .end = 0x206B6000 - 1, /* 3.125 MB total */ - .flags = IORESOURCE_MEM, - }, + /* 3.125MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x20396000, 0x206B6000-1, + IORESOURCE_MEM) + /* * GHW HAL Driver */ - { - .name = "GraphicsHeap", - .start = 0x20100000, - .end = 0x20396000 - 1, - .flags = IORESOURCE_MEM, - }, + /* PowerTV Graphics Heap (2.59MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x20100000, 0x20396000-1, + IORESOURCE_MEM) + /* * multi com buffer area */ - { - .name = "MulticomSHM", - .start = 0x206B6000, - .end = 0x206D6000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x206B6000, 0x206D6000-1, + IORESOURCE_MEM) + /* - * DMA Ring buffer + * DMA Ring buffer (don't need recording buffers) */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Display bins buffer for unit0 */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * PMEM */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Smartcard */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * NAND Flash */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE+0x400 - 1, - .flags = IORESOURCE_MEM, - }, + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + /* * Synopsys GMAC Memory Region */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; struct resource non_dvr_vzf_calliope_resources[] __initdata = @@ -465,156 +269,117 @@ struct resource non_dvr_vzf_calliope_resources[] __initdata = /* * VIDEO / LX1 */ - { - .name = "ST231aImage", /*Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /*8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */ - .end = 0x25580000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~19.4 (21.5MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25580000-1, + IORESOURCE_MEM) + /* * Sysaudio Driver */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * STAVEM driver/STAPI */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00480000 - 1, /* 4.5 MB total */ - .flags = IORESOURCE_MEM, - }, + /* 4.5MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00480000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * GHW HAL Driver */ - { - .name = "GraphicsHeap", - .start = 0x22700000, - .end = 0x23500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x25600000, 0x25600000+(14*1048576)-1, + IORESOURCE_MEM) + /* * multi com buffer area */ - { - .name = "MulticomSHM", - .start = 0x23700000, - .end = 0x23720000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, + IORESOURCE_MEM) + /* * DMA Ring buffer (don't need recording buffers) */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Display bins buffer for unit0 */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Display bins buffer for unit1 */ - { - .name = "DisplayBins1", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * PMEM */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Smartcard */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * NAND Flash */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_MEM, - }, + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + /* * Synopsys GMAC Memory Region */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c index 45a5c3ea718c..c532b50521ec 100644 --- a/arch/mips/powertv/asic/prealloc-cronus.c +++ b/arch/mips/powertv/asic/prealloc-cronus.c @@ -22,7 +22,9 @@ */ #include <linux/init.h> +#include <linux/ioport.h> #include <asm/mach-powertv/asic.h> +#include "prealloc.h" /* * DVR_CAPABLE CRONUS RESOURCES @@ -30,305 +32,161 @@ struct resource dvr_cronus_resources[] __initdata = { /* - * * VIDEO1 / LX1 - * */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, + IORESOURCE_MEM) + /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + /* - * * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * STAVEM driver/STAPI * - * This driver requires: - * - * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + IORESOURCE_MEM) + /* - * * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + /* - * * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + /* - * * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + /* - * * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x002EA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * + * Display bins buffer for unit1 */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + /* - * * ITFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "ITFS", - .start = 0x64180000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x6430DFFF, - .flags = IORESOURCE_IO, - }, + /* 815,104 bytes each for 2 ITFS partitions. */ + PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, IORESOURCE_MEM) + /* - * * AVFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ - .end = 0x64AD0000 - 1, - .flags = IORESOURCE_IO, - }, - { - .name = "AvfsFileSys", - .start = 0x64AD0000, - .end = 0x64AD1000 - 1, /* 4K */ - .flags = IORESOURCE_IO, - }, + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, + IORESOURCE_MEM) + + /* 4KiB */ + PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + /* - * * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + IORESOURCE_MEM) + /* - * * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; /* @@ -337,272 +195,146 @@ struct resource dvr_cronus_resources[] __initdata = struct resource non_dvr_cronus_resources[] __initdata = { /* - * * VIDEO1 / LX1 - * */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, + IORESOURCE_MEM) + /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + /* - * * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * STAVEM driver/STAPI * - * This driver requires: - * - * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + IORESOURCE_MEM) + /* - * * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + /* - * * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + /* - * * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * + * DMA Ring buffer (don't need recording buffers) */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * + * Display bins buffer for unit1 */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, IORESOURCE_MEM) + /* - * * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) + /* - * * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 + */ + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * Add other resources here + */ + + /* + * End of Resource marker */ { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, + .flags = 0, }, - { }, }; diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c index 23a905613c04..b5537e49e7f5 100644 --- a/arch/mips/powertv/asic/prealloc-cronuslite.c +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c @@ -22,7 +22,9 @@ */ #include <linux/init.h> +#include <linux/ioport.h> #include <asm/mach-powertv/asic.h> +#include "prealloc.h" /* * NON_DVR_CAPABLE CRONUSLITE RESOURCES @@ -30,261 +32,143 @@ struct resource non_dvr_cronuslite_resources[] __initdata = { /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231aImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + /* - * * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * STAVEM driver/STAPI * - * This driver requires: - * - * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x63B80000 - 1, /* 6 MB total */ - .flags = IORESOURCE_IO, - }, + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + IORESOURCE_MEM) + /* - * * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + /* - * * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + /* - * * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * + * DMA Ring buffer (don't need recording buffers) */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * + * Display bins buffer for unit1 */ - { - .name = "DisplayBins1", - .start = 0x63B83000, - .end = 0x63B84000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x63B84000, - .end = 0x63E48C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * */ - { - .name = "SmartCardInfo", - .start = 0x63B80000, - .end = 0x63B82800 - 1, - .flags = IORESOURCE_IO, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) + /* - * * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + /* * NAND Flash */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c index 018d4514dbe3..96480a2395c0 100644 --- a/arch/mips/powertv/asic/prealloc-zeus.c +++ b/arch/mips/powertv/asic/prealloc-zeus.c @@ -22,7 +22,9 @@ */ #include <linux/init.h> +#include <linux/ioport.h> #include <asm/mach-powertv/asic.h> +#include "prealloc.h" /* * DVR_CAPABLE RESOURCES @@ -30,280 +32,151 @@ struct resource dvr_zeus_resources[] __initdata = { /* - * * VIDEO1 / LX1 - * */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x20000000, - .end = 0x201FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x20200000, - .end = 0x20201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x20202000, - .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, + IORESOURCE_MEM) + /* - * * VIDEO2 / LX2 - * */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x30000000, - .end = 0x301FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x30200000, - .end = 0x30201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x30202000, - .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x30000000, 0x30200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x30200000, 0x30202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x30202000, 0x32000000-1, + IORESOURCE_MEM) + /* - * * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * STAVEM driver/STAPI * - * This driver requires: - * - * Arbitrary Based Buffers: * This memory area is used for allocating buffers for Video decoding * purposes. Allocation/De-allocation within this buffer is managed * by the STAVMEM driver of the STAPI. They could be Decimated * Picture Buffers, Intermediate Buffers, as deemed necessary for * video decoding purposes, for any video decoders on Zeus. - * */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00c00000 - 1, /* 12 MB total */ - .flags = IORESOURCE_MEM, - }, + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "Docsis", - .start = 0x40100000, - .end = 0x407fffff, - .flags = IORESOURCE_MEM, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) + /* - * * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * */ - { - .name = "GraphicsHeap", - .start = 0x46900000, - .end = 0x47700000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, + IORESOURCE_MEM) + /* - * * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "MulticomSHM", - .start = 0x47900000, - .end = 0x47920000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, + IORESOURCE_MEM) + /* - * * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 2.5MiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * + * Display bins buffer for unit1 */ - { - .name = "DisplayBins1", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * ITFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "ITFS", - .start = 0x00000000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x0018DFFF, - .flags = IORESOURCE_MEM, - }, + /* 815,104 bytes each for 2 ITFS partitions. */ + PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * AVFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ - .end = 0x007c2000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "AvfsFileSys", - .start = 0x00000000, - .end = 0x00001000 - 1, /* 4K */ - .flags = IORESOURCE_MEM, - }, + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* 4KiB */ + PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * TFTPBuffer * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; /* @@ -314,146 +187,118 @@ struct resource non_dvr_zeus_resources[] __initdata = /* * VIDEO1 / LX1 */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x20000000, - .end = 0x201FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x20200000, - .end = 0x20201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x20202000, - .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, + IORESOURCE_MEM) + /* * Sysaudio Driver */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * STAVEM driver/STAPI */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00600000 - 1, /* 6 MB total */ - .flags = IORESOURCE_MEM, - }, + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * DOCSIS Subsystem */ - { - .name = "Docsis", - .start = 0x40100000, - .end = 0x407fffff, - .flags = IORESOURCE_MEM, - }, + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) + /* * GHW HAL Driver */ - { - .name = "GraphicsHeap", - .start = 0x46900000, - .end = 0x47700000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, + IORESOURCE_MEM) + /* * multi com buffer area */ - { - .name = "MulticomSHM", - .start = 0x47900000, - .end = 0x47920000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, + IORESOURCE_MEM) + /* * DMA Ring buffer */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, + /* 2.5MiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Display bins buffer for unit0 */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* - * * AVFS: player HAL memory - * - * */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * PMEM */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Smartcard */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * NAND Flash */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* * Add other resources here */ - { }, + + /* + * End of Resource marker + */ + { + .flags = 0, + }, }; diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h new file mode 100644 index 000000000000..8e682df17856 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc.h @@ -0,0 +1,70 @@ +/* + * Definitions for memory preallocations + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H +#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H + +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ + +/* "struct resource" array element definition */ +#define PREALLOC(NAME, START, END, FLAGS) { \ + .name = (NAME), \ + .start = (START), \ + .end = (END), \ + .flags = (FLAGS) \ + }, + +/* Individual resources in the preallocated resource arrays are defined using + * macros. These macros are conditionally defined based on their + * corresponding kernel configuration flag: + * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box + * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource + * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource + * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory + */ +#ifdef CONFIG_PREALLOC_NORMAL +#define PREALLOC_NORMAL(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_NORMAL(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_TFTP +#define PREALLOC_TFTP(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_TFTP(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_DOCSIS +#define PREALLOC_DOCSIS(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_DOCSIS(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_PMEM +#define PREALLOC_PMEM(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_PMEM(name, start, end, flags) +#endif +#endif diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h index e41222d6c2fd..f0cc1f84a72f 100644 --- a/arch/mn10300/include/asm/atomic.h +++ b/arch/mn10300/include/asm/atomic.h @@ -1,157 +1 @@ -/* MN10300 Atomic counter operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_ATOMIC_H -#define _ASM_ATOMIC_H - -#ifdef CONFIG_SMP -#error not SMP safe -#endif - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ - -/** - * atomic_read - read atomic variable - * @v: pointer of type atomic_t - * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_read(v) (*(volatile int *)&(v)->counter) - -/** - * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value - * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_set(v, i) (((v)->counter) = (i)) - -#include <asm/system.h> - -/** - * atomic_add_return - add integer to atomic variable - * @i: integer value to add - * @v: pointer of type atomic_t - * - * Atomically adds @i to @v and returns the result - * Note that the guaranteed useful range of an atomic_t is only 24 bits. - */ -static inline int atomic_add_return(int i, atomic_t *v) -{ - unsigned long flags; - int temp; - - local_irq_save(flags); - temp = v->counter; - temp += i; - v->counter = temp; - local_irq_restore(flags); - - return temp; -} - -/** - * atomic_sub_return - subtract integer from atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v and returns the result - * Note that the guaranteed useful range of an atomic_t is only 24 bits. - */ -static inline int atomic_sub_return(int i, atomic_t *v) -{ - unsigned long flags; - int temp; - - local_irq_save(flags); - temp = v->counter; - temp -= i; - v->counter = temp; - local_irq_restore(flags); - - return temp; -} - -static inline int atomic_add_negative(int i, atomic_t *v) -{ - return atomic_add_return(i, v) < 0; -} - -static inline void atomic_add(int i, atomic_t *v) -{ - atomic_add_return(i, v); -} - -static inline void atomic_sub(int i, atomic_t *v) -{ - atomic_sub_return(i, v); -} - -static inline void atomic_inc(atomic_t *v) -{ - atomic_add_return(1, v); -} - -static inline void atomic_dec(atomic_t *v) -{ - atomic_sub_return(1, v); -} - -#define atomic_dec_return(v) atomic_sub_return(1, (v)) -#define atomic_inc_return(v) atomic_add_return(1, (v)) - -#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) -#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) -#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) - -#define atomic_add_unless(v, a, u) \ -({ \ - int c, old; \ - c = atomic_read(v); \ - while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ - c = old; \ - c != (u); \ -}) - -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - mask = ~mask; - local_irq_save(flags); - *addr &= mask; - local_irq_restore(flags); -} - -#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v))) -#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) - -/* Atomic operations are already serializing on MN10300??? */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#include <asm-generic/atomic-long.h> - -#endif /* __KERNEL__ */ -#endif /* _ASM_ATOMIC_H */ +#include <asm-generic/atomic.h> diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h index e03cfa2e997e..6e2fe28dde4e 100644 --- a/arch/mn10300/include/asm/cache.h +++ b/arch/mn10300/include/asm/cache.h @@ -21,6 +21,8 @@ #define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES #endif +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + /* data cache purge registers * - read from the register to unconditionally purge that cache line * - write address & 0xffffff00 to conditionally purge that cache line diff --git a/arch/mn10300/include/asm/scatterlist.h b/arch/mn10300/include/asm/scatterlist.h index 67535901b9ff..7bd00b9e030d 100644 --- a/arch/mn10300/include/asm/scatterlist.h +++ b/arch/mn10300/include/asm/scatterlist.h @@ -11,45 +11,8 @@ #ifndef _ASM_SCATTERLIST_H #define _ASM_SCATTERLIST_H -#include <asm/types.h> - -/* - * Drivers must set either ->address or (preferred) page and ->offset - * to indicate where data must be transferred to/from. - * - * Using page is recommended since it handles highmem data as well as - * low mem. ->address is restricted to data which has a virtual mapping, and - * it will go away in the future. Updating to page can be automated very - * easily -- something like - * - * sg->address = some_ptr; - * - * can be rewritten as - * - * sg_set_page(virt_to_page(some_ptr)); - * sg->offset = (unsigned long) some_ptr & ~PAGE_MASK; - * - * and that's it. There's no excuse for not highmem enabling YOUR driver. /jens - */ -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; /* for highmem, page offset */ - dma_addr_t dma_address; - unsigned int length; -}; +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (0x00ffffff) -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - #endif /* _ASM_SCATTERLIST_H */ diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c index 53bb17d0f068..81f153fa51b4 100644 --- a/arch/mn10300/mm/fault.c +++ b/arch/mn10300/mm/fault.c @@ -338,11 +338,10 @@ no_context: */ out_of_memory: up_read(&mm->mmap_sem); - monitor_signal(regs); - printk(KERN_ALERT "VM: killing process %s\n", tsk->comm); - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) - do_exit(SIGKILL); - goto no_context; + if ((fault_code & MMUFCR_xFC_ACCESS) != MMUFCR_xFC_ACCESS_USR) + goto no_context; + pagefault_out_of_memory(); + return; do_sigbus: up_read(&mm->mmap_sem); diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c index d6119b879a98..45b40ac6c464 100644 --- a/arch/mn10300/unit-asb2305/pci-asb2305.c +++ b/arch/mn10300/unit-asb2305/pci-asb2305.c @@ -117,6 +117,7 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) * Invalidate the resource to prevent * child resource allocations in this * range. */ + r->start = r->end = 0; r->flags = 0; } } diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 9c4da3d63bfb..05a366a5c4d5 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -98,6 +98,9 @@ config STACKTRACE_SUPPORT config NEED_DMA_MAP_STATE def_bool y +config NEED_SG_DMA_LENGTH + def_bool y + config ISA_DMA_API bool diff --git a/arch/parisc/include/asm/bug.h b/arch/parisc/include/asm/bug.h index 75e46c557a16..72cfdb0cfdd1 100644 --- a/arch/parisc/include/asm/bug.h +++ b/arch/parisc/include/asm/bug.h @@ -44,7 +44,7 @@ #endif #ifdef CONFIG_DEBUG_BUGVERBOSE -#define __WARN() \ +#define __WARN_TAINT(taint) \ do { \ asm volatile("\n" \ "1:\t" PARISC_BUG_BREAK_ASM "\n" \ @@ -54,11 +54,11 @@ "\t.org 2b+%c3\n" \ "\t.popsection" \ : : "i" (__FILE__), "i" (__LINE__), \ - "i" (BUGFLAG_WARNING), \ + "i" (BUGFLAG_TAINT(taint)), \ "i" (sizeof(struct bug_entry)) ); \ } while(0) #else -#define __WARN() \ +#define __WARN_TAINT(taint) \ do { \ asm volatile("\n" \ "1:\t" PARISC_BUG_BREAK_ASM "\n" \ @@ -67,7 +67,7 @@ "\t.short %c0\n" \ "\t.org 2b+%c1\n" \ "\t.popsection" \ - : : "i" (BUGFLAG_WARNING), \ + : : "i" (BUGFLAG_TAINT(taint)), \ "i" (sizeof(struct bug_entry)) ); \ } while(0) #endif diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 32c2cca74345..45effe6978fa 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -28,7 +28,7 @@ #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) void parisc_cache_init(void); /* initializes cache-flushing */ void disable_sr_hashing_asm(int); /* low level support for above */ diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h index 477277739da5..4556d820128a 100644 --- a/arch/parisc/include/asm/cacheflush.h +++ b/arch/parisc/include/asm/cacheflush.h @@ -2,6 +2,7 @@ #define _PARISC_CACHEFLUSH_H #include <linux/mm.h> +#include <linux/uaccess.h> /* The usual comment is "Caches aren't brain-dead on the <architecture>". * Unfortunately, that doesn't apply to PA-RISC. */ @@ -125,11 +126,20 @@ static inline void *kmap(struct page *page) #define kunmap(page) kunmap_parisc(page_address(page)) -#define kmap_atomic(page, idx) page_address(page) +static inline void *kmap_atomic(struct page *page, enum km_type idx) +{ + pagefault_disable(); + return page_address(page); +} -#define kunmap_atomic(addr, idx) kunmap_parisc(addr) +static inline void kunmap_atomic(void *addr, enum km_type idx) +{ + kunmap_parisc(addr); + pagefault_enable(); +} -#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn)) +#define kmap_atomic_prot(page, idx, prot) kmap_atomic(page, idx) +#define kmap_atomic_pfn(pfn, idx) kmap_atomic(pfn_to_page(pfn), (idx)) #define kmap_atomic_to_page(ptr) virt_to_page(ptr) #endif diff --git a/arch/parisc/include/asm/scatterlist.h b/arch/parisc/include/asm/scatterlist.h index 62269b31ebf4..2c3b79b54b28 100644 --- a/arch/parisc/include/asm/scatterlist.h +++ b/arch/parisc/include/asm/scatterlist.h @@ -3,25 +3,9 @@ #include <asm/page.h> #include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - - unsigned int length; - - /* an IOVA can be 64-bits on some PA-Risc platforms. */ - dma_addr_t iova; /* I/O Virtual Address */ - __u32 iova_length; /* bytes mapped */ -}; - -#define sg_virt_addr(sg) ((unsigned long)sg_virt(sg)) -#define sg_dma_address(sg) ((sg)->iova) -#define sg_dma_len(sg) ((sg)->iova_length) +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (~0UL) +#define sg_virt_addr(sg) ((unsigned long)sg_virt(sg)) #endif /* _ASM_PARISC_SCATTERLIST_H */ diff --git a/arch/parisc/include/asm/system.h b/arch/parisc/include/asm/system.h index 4653c77bf9d1..2ab4af58ecb9 100644 --- a/arch/parisc/include/asm/system.h +++ b/arch/parisc/include/asm/system.h @@ -174,7 +174,7 @@ static inline void set_eiem(unsigned long val) }) #ifdef CONFIG_SMP -# define __lock_aligned __attribute__((__section__(".data.lock_aligned"))) +# define __lock_aligned __attribute__((__section__(".data..lock_aligned"))) #endif #define arch_align_stack(x) (x) diff --git a/arch/parisc/kernel/asm-offsets.c b/arch/parisc/kernel/asm-offsets.c index ec787b411e9a..dcd55103a4bb 100644 --- a/arch/parisc/kernel/asm-offsets.c +++ b/arch/parisc/kernel/asm-offsets.c @@ -45,8 +45,12 @@ #else #define FRAME_SIZE 64 #endif +#define FRAME_ALIGN 64 -#define align(x,y) (((x)+FRAME_SIZE+(y)-1) - (((x)+(y)-1)%(y))) +/* Add FRAME_SIZE to the size x and align it to y. All definitions + * that use align_frame will include space for a frame. + */ +#define align_frame(x,y) (((x)+FRAME_SIZE+(y)-1) - (((x)+(y)-1)%(y))) int main(void) { @@ -146,7 +150,8 @@ int main(void) DEFINE(TASK_PT_IOR, offsetof(struct task_struct, thread.regs.ior)); BLANK(); DEFINE(TASK_SZ, sizeof(struct task_struct)); - DEFINE(TASK_SZ_ALGN, align(sizeof(struct task_struct), 64)); + /* TASK_SZ_ALGN includes space for a stack frame. */ + DEFINE(TASK_SZ_ALGN, align_frame(sizeof(struct task_struct), FRAME_ALIGN)); BLANK(); DEFINE(PT_PSW, offsetof(struct pt_regs, gr[ 0])); DEFINE(PT_GR1, offsetof(struct pt_regs, gr[ 1])); @@ -233,7 +238,8 @@ int main(void) DEFINE(PT_ISR, offsetof(struct pt_regs, isr)); DEFINE(PT_IOR, offsetof(struct pt_regs, ior)); DEFINE(PT_SIZE, sizeof(struct pt_regs)); - DEFINE(PT_SZ_ALGN, align(sizeof(struct pt_regs), 64)); + /* PT_SZ_ALGN includes space for a stack frame. */ + DEFINE(PT_SZ_ALGN, align_frame(sizeof(struct pt_regs), FRAME_ALIGN)); BLANK(); DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain)); @@ -242,7 +248,8 @@ int main(void) DEFINE(TI_SEGMENT, offsetof(struct thread_info, addr_limit)); DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count)); DEFINE(THREAD_SZ, sizeof(struct thread_info)); - DEFINE(THREAD_SZ_ALGN, align(sizeof(struct thread_info), 64)); + /* THREAD_SZ_ALGN includes space for a stack frame. */ + DEFINE(THREAD_SZ_ALGN, align_frame(sizeof(struct thread_info), FRAME_ALIGN)); BLANK(); DEFINE(ICACHE_BASE, offsetof(struct pdc_cache_info, ic_base)); DEFINE(ICACHE_STRIDE, offsetof(struct pdc_cache_info, ic_stride)); diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 3a44f7f704fa..6337adef30f6 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -364,32 +364,6 @@ .align 32 .endm - /* The following are simple 32 vs 64 bit instruction - * abstractions for the macros */ - .macro EXTR reg1,start,length,reg2 -#ifdef CONFIG_64BIT - extrd,u \reg1,32+(\start),\length,\reg2 -#else - extrw,u \reg1,\start,\length,\reg2 -#endif - .endm - - .macro DEP reg1,start,length,reg2 -#ifdef CONFIG_64BIT - depd \reg1,32+(\start),\length,\reg2 -#else - depw \reg1,\start,\length,\reg2 -#endif - .endm - - .macro DEPI val,start,length,reg -#ifdef CONFIG_64BIT - depdi \val,32+(\start),\length,\reg -#else - depwi \val,\start,\length,\reg -#endif - .endm - /* In LP64, the space contains part of the upper 32 bits of the * fault. We have to extract this and place it in the va, * zeroing the corresponding bits in the space register */ @@ -442,19 +416,19 @@ */ .macro L2_ptep pmd,pte,index,va,fault #if PT_NLEVELS == 3 - EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index + extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index #else - EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index + extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index #endif - DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ + dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */ copy %r0,\pte ldw,s \index(\pmd),\pmd bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault - DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ + dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ copy \pmd,%r9 SHLREG %r9,PxD_VALUE_SHIFT,\pmd - EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index - DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ + extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index + dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */ shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd LDREG %r0(\pmd),\pte /* pmd is now pte */ bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault @@ -605,7 +579,7 @@ depdi 0,31,32,\tmp #endif copy \va,\tmp1 - DEPI 0,31,23,\tmp1 + depi 0,31,23,\tmp1 cmpb,COND(<>),n \tmp,\tmp1,\fault ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot depd,z \prot,8,7,\prot @@ -997,13 +971,6 @@ intr_restore: rfi nop - nop - nop - nop - nop - nop - nop - nop #ifndef CONFIG_PREEMPT # define intr_do_preempt intr_restore @@ -2076,9 +2043,10 @@ syscall_restore: LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */ /* NOTE: We use rsm/ssm pair to make this operation atomic */ + LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */ rsm PSW_SM_I, %r0 - LDREG TASK_PT_GR30(%r1),%r30 /* restore user sp */ - mfsp %sr3,%r1 /* Get users space id */ + copy %r1,%r30 /* Restore user sp */ + mfsp %sr3,%r1 /* Get user space id */ mtsp %r1,%sr7 /* Restore sr7 */ ssm PSW_SM_I, %r0 diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S index 0e3d9f9b9e33..4dbdf0ed6fa0 100644 --- a/arch/parisc/kernel/head.S +++ b/arch/parisc/kernel/head.S @@ -345,7 +345,7 @@ smp_slave_stext: ENDPROC(stext) #ifndef CONFIG_64BIT - .section .data.read_mostly + .section .data..read_mostly .align 4 .export $global$,data diff --git a/arch/parisc/kernel/init_task.c b/arch/parisc/kernel/init_task.c index d020eae6525c..4a91e433416f 100644 --- a/arch/parisc/kernel/init_task.c +++ b/arch/parisc/kernel/init_task.c @@ -53,11 +53,11 @@ union thread_union init_thread_union __init_task_data * guarantee that global objects will be laid out in memory in the same order * as the order of declaration, so put these in different sections and use * the linker script to order them. */ -pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data.vm0.pmd"), aligned(PAGE_SIZE))); +pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data..vm0.pmd"), aligned(PAGE_SIZE))); #endif -pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data.vm0.pgd"), aligned(PAGE_SIZE))); -pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data.vm0.pte"), aligned(PAGE_SIZE))); +pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data..vm0.pgd"), aligned(PAGE_SIZE))); +pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pte"), aligned(PAGE_SIZE))); /* * Initial task structure. diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S index f5f96021caa0..68e75ce838d6 100644 --- a/arch/parisc/kernel/syscall.S +++ b/arch/parisc/kernel/syscall.S @@ -47,18 +47,17 @@ ENTRY(linux_gateway_page) KILL_INSN .endr - /* ADDRESS 0xb0 to 0xb4, lws uses 1 insns for entry */ + /* ADDRESS 0xb0 to 0xb8, lws uses two insns for entry */ /* Light-weight-syscall entry must always be located at 0xb0 */ /* WARNING: Keep this number updated with table size changes */ #define __NR_lws_entries (2) lws_entry: - /* Unconditional branch to lws_start, located on the - same gateway page */ - b,n lws_start + gate lws_start, %r0 /* increase privilege */ + depi 3, 31, 2, %r31 /* Ensure we return into user mode. */ - /* Fill from 0xb4 to 0xe0 */ - .rept 11 + /* Fill from 0xb8 to 0xe0 */ + .rept 10 KILL_INSN .endr @@ -423,9 +422,6 @@ tracesys_sigexit: *********************************************************/ lws_start: - /* Gate and ensure we return to userspace */ - gate .+8, %r0 - depi 3, 31, 2, %r31 /* Ensure we return to userspace */ #ifdef CONFIG_64BIT /* FIXME: If we are a 64-bit kernel just @@ -442,7 +438,7 @@ lws_start: #endif /* Is the lws entry number valid? */ - comiclr,>>= __NR_lws_entries, %r20, %r0 + comiclr,>> __NR_lws_entries, %r20, %r0 b,n lws_exit_nosys /* WARNING: Trashing sr2 and sr3 */ @@ -473,7 +469,7 @@ lws_exit: /* now reset the lowest bit of sp if it was set */ xor %r30,%r1,%r30 #endif - be,n 0(%sr3, %r31) + be,n 0(%sr7, %r31) @@ -529,7 +525,6 @@ lws_compare_and_swap32: #endif lws_compare_and_swap: -#ifdef CONFIG_SMP /* Load start of lock table */ ldil L%lws_lock_start, %r20 ldo R%lws_lock_start(%r20), %r28 @@ -572,8 +567,6 @@ cas_wouldblock: ldo 2(%r0), %r28 /* 2nd case */ b lws_exit /* Contended... */ ldo -EAGAIN(%r0), %r21 /* Spin in userspace */ -#endif -/* CONFIG_SMP */ /* prev = *addr; @@ -601,13 +594,11 @@ cas_action: 1: ldw 0(%sr3,%r26), %r28 sub,<> %r28, %r25, %r0 2: stw %r24, 0(%sr3,%r26) -#ifdef CONFIG_SMP /* Free lock */ stw %r20, 0(%sr2,%r20) -# if ENABLE_LWS_DEBUG +#if ENABLE_LWS_DEBUG /* Clear thread register indicator */ stw %r0, 4(%sr2,%r20) -# endif #endif /* Return to userspace, set no error */ b lws_exit @@ -615,12 +606,10 @@ cas_action: 3: /* Error occured on load or store */ -#ifdef CONFIG_SMP /* Free lock */ stw %r20, 0(%sr2,%r20) -# if ENABLE_LWS_DEBUG +#if ENABLE_LWS_DEBUG stw %r0, 4(%sr2,%r20) -# endif #endif b lws_exit ldo -EFAULT(%r0),%r21 /* set errno */ @@ -672,7 +661,6 @@ ENTRY(sys_call_table64) END(sys_call_table64) #endif -#ifdef CONFIG_SMP /* All light-weight-syscall atomic operations will use this set of locks @@ -694,8 +682,6 @@ ENTRY(lws_lock_start) .endr END(lws_lock_start) .previous -#endif -/* CONFIG_SMP for lws_lock_start */ .end diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S index 9dab4a4e09f7..d64a6bbec2aa 100644 --- a/arch/parisc/kernel/vmlinux.lds.S +++ b/arch/parisc/kernel/vmlinux.lds.S @@ -94,8 +94,8 @@ SECTIONS /* PA-RISC locks requires 16-byte alignment */ . = ALIGN(16); - .data.lock_aligned : { - *(.data.lock_aligned) + .data..lock_aligned : { + *(.data..lock_aligned) } /* End of data section */ @@ -105,10 +105,10 @@ SECTIONS __bss_start = .; /* page table entries need to be PAGE_SIZE aligned */ . = ALIGN(PAGE_SIZE); - .data.vmpages : { - *(.data.vm0.pmd) - *(.data.vm0.pgd) - *(.data.vm0.pte) + .data..vmpages : { + *(.data..vm0.pmd) + *(.data..vm0.pgd) + *(.data..vm0.pte) } .bss : { *(.bss) diff --git a/arch/parisc/math-emu/decode_exc.c b/arch/parisc/math-emu/decode_exc.c index 3ca1c6149218..27a7492ddb0d 100644 --- a/arch/parisc/math-emu/decode_exc.c +++ b/arch/parisc/math-emu/decode_exc.c @@ -342,6 +342,7 @@ decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[]) return SIGNALCODE(SIGFPE, FPE_FLTINV); case DIVISIONBYZEROEXCEPTION: update_trap_counts(Fpu_register, aflags, bflags, trap_counts); + Clear_excp_register(exception_index); return SIGNALCODE(SIGFPE, FPE_FLTDIV); case INEXACTEXCEPTION: update_trap_counts(Fpu_register, aflags, bflags, trap_counts); diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c index c6afbfc95770..18162ce4261e 100644 --- a/arch/parisc/mm/fault.c +++ b/arch/parisc/mm/fault.c @@ -264,8 +264,7 @@ no_context: out_of_memory: up_read(&mm->mmap_sem); - printk(KERN_CRIT "VM: killing process %s\n", current->comm); - if (user_mode(regs)) - do_group_exit(SIGKILL); - goto no_context; + if (!user_mode(regs)) + goto no_context; + pagefault_out_of_memory(); } diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c4c4549c22bb..328774bd41ee 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -351,7 +351,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE config KEXEC bool "kexec system call (EXPERIMENTAL)" - depends on PPC_BOOK3S && EXPERIMENTAL + depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot @@ -663,6 +663,9 @@ config ZONE_DMA config NEED_DMA_MAP_STATE def_bool (PPC64 || NOT_COHERENT_CACHE) +config NEED_SG_DMA_LENGTH + def_bool y + config GENERIC_ISA_DMA bool depends on PPC64 || POWER4 || 6xx && !CPM2 diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 1a54a3b3a3fa..42dcd3f4ad7b 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -112,6 +112,11 @@ KBUILD_CFLAGS += $(call cc-option,-mspe=no) # kernel considerably. KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time) +# FIXME: the module load should be taught about the additional relocs +# generated by this. +# revert to pre-gcc-4.4 behaviour of .eh_frame +KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + # Never use string load/store instructions as they are # often slow when they are implemented at all KBUILD_CFLAGS += -mno-string diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 27db8938827a..9d3bd4c45a24 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -519,7 +519,7 @@ void ibm440ep_fixup_clocks(unsigned int sys_clk, { unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); - /* serial clocks beed fixup based on int/ext */ + /* serial clocks need fixup based on int/ext */ eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk); eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk); @@ -532,7 +532,7 @@ void ibm440gx_fixup_clocks(unsigned int sys_clk, { unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); - /* serial clocks beed fixup based on int/ext */ + /* serial clocks need fixup based on int/ext */ eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk); } @@ -543,10 +543,10 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk, { unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); - /* serial clocks beed fixup based on int/ext */ - eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk); - eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk); - eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk); + /* serial clocks need fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk); + eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk); } void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) diff --git a/arch/powerpc/boot/dts/icon.dts b/arch/powerpc/boot/dts/icon.dts new file mode 100644 index 000000000000..abcd0caeccae --- /dev/null +++ b/arch/powerpc/boot/dts/icon.dts @@ -0,0 +1,447 @@ +/* + * Device Tree Source for Mosaix Technologies, Inc. ICON board + * + * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "mosaixtech,icon"; + compatible = "mosaixtech,icon"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440SPe"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + reset-type = <2>; /* Use chip-reset */ + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440spe"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440spe"; + dcr-reg = <0x00c 0x002>; + }; + + MQ0: mq { + compatible = "ibm,mq-440spe"; + dcr-reg = <0x040 0x020>; + }; + + plb { + compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + /* addr-child addr-parent size */ + ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 + 0x4 0x00200000 0x4 0x00200000 0x00000400 + 0x4 0xe0000000 0x4 0xe0000000 0x20000000 + 0xc 0x00000000 0xc 0x00000000 0x20000000 + 0xd 0x00000000 0xd 0x00000000 0x80000000 + 0xd 0x80000000 0xd 0x80000000 0x80000000 + 0xe 0x00000000 0xe 0x00000000 0x80000000 + 0xe 0x80000000 0xe 0x80000000 0x80000000 + 0xf 0x00000000 0xf 0x00000000 0x80000000 + 0xf 0x80000000 0xf 0x80000000 0x80000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <2>; + num-rx-chans = <1>; + interrupt-parent = <&MAL0>; + interrupts = <0x0 0x1 0x2 0x3 0x4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4 + /*RXEOB*/ 0x1 &UIC1 0x7 0x4 + /*SERR*/ 0x2 &UIC1 0x1 0x4 + /*TXDE*/ 0x3 &UIC1 0x2 0x4 + /*RXDE*/ 0x4 &UIC1 0x3 0x4>; + }; + + POB0: opb { + compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x5 0x1>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x01000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "user"; + reg = <0x00400000 0x00b60000>; + }; + partition@f60000 { + label = "env"; + reg = <0x00f60000 0x00040000>; + }; + partition@fa0000 { + label = "u-boot"; + reg = <0x00fa0000 0x00060000>; + }; + }; + + SysACE_CompactFlash: sysace@1,0 { + compatible = "xlnx,sysace"; + interrupt-parent = <&UIC2>; + interrupts = <24 0x4>; + reg = <0x00000001 0x00000000 0x10000>; + }; + }; + + UART0: serial@f0000200 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xf0000200 0x00000008>; + virtual-reg = <0xa0000200>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <115200>; + interrupt-parent = <&UIC0>; + interrupts = <0x0 0x4>; + }; + + UART1: serial@f0000300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xf0000300 0x00000008>; + virtual-reg = <0xa0000300>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <0x1 0x4>; + }; + + + UART2: serial@f0000600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xf0000600 0x00000008>; + virtual-reg = <0xa0000600>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <0x5 0x4>; + }; + + IIC0: i2c@f0000400 { + compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; + reg = <0xf0000400 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + }; + + IIC1: i2c@f0000500 { + compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; + reg = <0xf0000500 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@68 { + compatible = "stm,m41t00"; + reg = <0x68>; + }; + }; + + EMAC0: ethernet@f0000800 { + linux,network-index = <0x0>; + device_type = "network"; + compatible = "ibm,emac-440spe", "ibm,emac4"; + interrupt-parent = <&UIC1>; + interrupts = <0x1c 0x4 0x1d 0x4>; + reg = <0xf0000800 0x00000074>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + phy-mode = "gmii"; + phy-map = <0x00000000>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; + + /* Inbound 4GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + + /* This drives busses 0 to 0xf */ + bus-range = <0x0 0xf>; + + /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */ + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x10000000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 4GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + + /* This drives busses 0x10 to 0x1f */ + bus-range = <0x10 0x1f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x10001000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 4GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + + /* This drives busses 0x20 to 0x2f */ + bus-range = <0x20 0x2f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; + }; + + I2O: i2o@400100000 { + compatible = "ibm,i2o-440spe"; + reg = <0x00000004 0x00100000 0x100>; + dcr-reg = <0x060 0x020>; + }; + + DMA0: dma0@400100100 { + compatible = "ibm,dma-440spe"; + cell-index = <0>; + reg = <0x00000004 0x00100100 0x100>; + dcr-reg = <0x060 0x020>; + interrupt-parent = <&DMA0>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = < + 0 &UIC0 0x14 4 + 1 &UIC1 0x16 4>; + }; + + DMA1: dma1@400100200 { + compatible = "ibm,dma-440spe"; + cell-index = <1>; + reg = <0x00000004 0x00100200 0x100>; + dcr-reg = <0x060 0x020>; + interrupt-parent = <&DMA1>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = < + 0 &UIC0 0x16 4 + 1 &UIC1 0x16 4>; + }; + + xor-accel@400200000 { + compatible = "amcc,xor-accelerator"; + reg = <0x00000004 0x00200000 0x400>; + interrupt-parent = <&UIC1>; + interrupts = <0x1f 4>; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@f0000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts index 8cf2c0c88c05..7c3be5e45748 100644 --- a/arch/powerpc/boot/dts/katmai.dts +++ b/arch/powerpc/boot/dts/katmai.dts @@ -44,6 +44,7 @@ d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; + reset-type = <2>; /* Use chip-reset */ }; }; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 4173af387c63..0f5262452682 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -20,10 +20,8 @@ aliases { ethernet0 = &enet0; ethernet1 = &enet1; -/* ethernet2 = &enet2; ethernet3 = &enet3; -*/ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; @@ -254,7 +252,6 @@ }; }; -/* eTSEC 3/4 are currently broken enet2: ethernet@26000 { #address-cells = <1>; #size-cells = <1>; @@ -310,7 +307,6 @@ }; }; }; - */ serial0: serial@4500 { cell-index = <0>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts index 5bd1011fde96..3375c2ab0c32 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts @@ -215,6 +215,18 @@ clock-frequency = <0>; }; + msi@41600 { + compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x80>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0>; + interrupt-parent = <&mpic>; + }; + global-utilities@e0000 { //global utilities block compatible = "fsl,mpc8572-guts"; reg = <0xe0000 0x1000>; @@ -243,8 +255,7 @@ protected-sources = < 31 32 33 37 38 39 /* enet2 enet3 */ 76 77 78 79 26 42 /* dma2 pci2 serial*/ - 0xe0 0xe1 0xe2 0xe3 /* msi */ - 0xe4 0xe5 0xe6 0xe7 + 0xe4 0xe5 0xe6 0xe7 /* msi */ >; }; }; diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts index 0efc3456e297..e7b477f6a3fe 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts @@ -154,12 +154,8 @@ msi@41600 { compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; reg = <0x41600 0x80>; - msi-available-ranges = <0 0x100>; + msi-available-ranges = <0x80 0x80>; interrupts = < - 0xe0 0 - 0xe1 0 - 0xe2 0 - 0xe3 0 0xe4 0 0xe5 0 0xe6 0 @@ -190,6 +186,7 @@ 0x1 0x2 0x3 0x4 /* pci slot */ 0x9 0xa 0xb 0xc /* usb */ 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */ + 0xe0 0xe1 0xe2 0xe3 /* msi */ >; }; }; diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts new file mode 100644 index 000000000000..7fad2df25981 --- /dev/null +++ b/arch/powerpc/boot/dts/p1021mds.dts @@ -0,0 +1,698 @@ +/* + * P1021 MDS Device Tree Source + * + * Copyright 2010 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; +/ { + model = "fsl,P1021"; + compatible = "fsl,P1021MDS"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + ethernet4 = &enet4; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1021@0 { + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + + PowerPC,P1021@1 { + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + }; + + localbus@ffe05000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xffe05000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + /* NAND Flash, BCSR, PMC0/1*/ + ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 + 0x1 0x0 0x0 0xf8000000 0x00008000 + 0x2 0x0 0x0 0xf8010000 0x00020000 + 0x3 0x0 0x0 0xf8020000 0x00020000>; + + nand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,p1021-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <0x0 0x0 0x40000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND (RO) U-Boot Image"; + read-only; + }; + + partition@100000 { + /* 1MB for DTB Image */ + reg = <0x00100000 0x00100000>; + label = "NAND (RO) DTB Image"; + read-only; + }; + + partition@200000 { + /* 4MB for Linux Kernel Image */ + reg = <0x00200000 0x00400000>; + label = "NAND (RO) Linux Kernel Image"; + read-only; + }; + + partition@600000 { + /* 5MB for Compressed Root file System Image */ + reg = <0x00600000 0x00500000>; + label = "NAND (RO) Compressed RFS Image"; + read-only; + }; + + partition@b00000 { + /* 6MB for JFFS2 based Root file System */ + reg = <0x00a00000 0x00600000>; + label = "NAND (RW) JFFS2 Root File System"; + }; + + partition@1100000 { + /* 14MB for JFFS2 based Root file System */ + reg = <0x01100000 0x00e00000>; + label = "NAND (RW) Writable User area"; + }; + + partition@1f00000 { + /* 1MB for microcode */ + reg = <0x01f00000 0x00100000>; + label = "NAND (RO) QE Ucode"; + read-only; + }; + }; + + bcsr@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,p1021mds-bcsr"; + reg = <1 0 0x8000>; + ranges = <0 1 0 0x8000>; + }; + + pib@2,0 { + compatible = "fsl,p1021mds-pib"; + reg = <2 0 0x10000>; + }; + + pib@3,0 { + compatible = "fsl,p1021mds-pib"; + reg = <3 0 0x10000>; + }; + }; + + soc@ffe00000 { + + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1021-immr", "simple-bus"; + ranges = <0x0 0x0 0xffe00000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,p1021-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <16 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,p1021-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + spi@7000 { + cell-index = <0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,espi"; + reg = <0x7000 0x1000>; + interrupts = <59 0x2>; + interrupt-parent = <&mpic>; + espi,num-ss-bits = <4>; + mode = "cpu"; + + fsl_m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,espi-flash"; + reg = <0>; + linux,modalias = "fsl_m25p80"; + spi-max-frequency = <40000000>; /* input clock */ + partition@u-boot { + label = "u-boot-spi"; + reg = <0x00000000 0x00100000>; + read-only; + }; + partition@kernel { + label = "kernel-spi"; + reg = <0x00100000 0x00500000>; + read-only; + }; + partition@dtb { + label = "dtb-spi"; + reg = <0x00600000 0x00100000>; + read-only; + }; + partition@fs { + label = "file system-spi"; + reg = <0x00700000 0x00900000>; + }; + }; + }; + + gpio: gpio-controller@f000 { + #gpio-cells = <2>; + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x100>; + interrupts = <47 0x2>; + interrupt-parent = <&mpic>; + gpio-controller; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,p1021-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2,256K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + usb@22000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <28 0x2>; + phy_type = "ulpi"; + }; + + mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <1 1>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1>; + reg = <0x1>; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&mpic>; + reg = <0x4>; + }; + }; + + mdio@25000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x25000 0x1000 0xb1030 0x4>; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@B0000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + queue-group@0{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB0000 0x1000>; + interrupts = <29 2 30 2 34 2>; + }; + queue-group@1{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB4000 0x1000>; + interrupts = <17 2 18 2 24 2>; + }; + }; + + enet1: ethernet@B1000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupt-parent = <&mpic>; + phy-handle = <&phy4>; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + queue-group@0{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB1000 0x1000>; + interrupts = <35 2 36 2 40 2>; + }; + queue-group@1{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB5000 0x1000>; + interrupts = <51 2 52 2 67 2>; + }; + }; + + enet2: ethernet@B2000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + queue-group@0{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB2000 0x1000>; + interrupts = <31 2 32 2 33 2>; + }; + queue-group@1{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB6000 0x1000>; + interrupts = <25 2 26 2 27 2>; + }; + }; + + sdhci@2e000 { + compatible = "fsl,p1021-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + + crypto@30000 { + compatible = "fsl,sec3.3", "fsl,sec3.1", + "fsl,sec3.0", "fsl,sec2.4", + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x97c>; + fsl,descriptor-types-mask = <0x3a30abf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + msi@41600 { + compatible = "fsl,p1021-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,p1021-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + par_io@e0100 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe0100 0x60>; + ranges = <0x0 0xe0100 0x60>; + device_type = "par_io"; + num-ports = <3>; + pio1: ucc_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ + 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ + 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 +*/ + 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ + 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ + 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ + 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ + 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ + 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ + 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ + 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ + 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ + 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ + 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ + 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ + 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ + 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ + }; + + pio2: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ + 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ + 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ + 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ + 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ + 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ + 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ + 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ + 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ + }; + }; + }; + + pci0: pcie@ffe09000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xffe09000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xffe0a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + qe@ffe80000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0x0 0xffe80000 0x40000>; + reg = <0 0xffe80000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <63 2 60 2>; //high:47 low:44 + interrupt-parent = <&mpic>; + }; + + enet3: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "clk12"; + tx-clock-name = "clk9"; + pio-handle = <&pio1>; + phy-handle = <&qe_phy0>; + phy-connection-type = "mii"; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2120 0x18>; + compatible = "fsl,ucc-mdio"; + + qe_phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x0>; + device_type = "ethernet-phy"; + }; + qe_phy1: ethernet-phy@03 { + interrupt-parent = <&mpic>; + interrupts = <5 1>; + reg = <0x3>; + device_type = "ethernet-phy"; + }; + tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet4: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk13"; + pio-handle = <&pio2>; + phy-handle = <&qe_phy1>; + phy-connection-type = "rmii"; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts index d2af32e2bf7a..81636c01d906 100644 --- a/arch/powerpc/boot/dts/redwood.dts +++ b/arch/powerpc/boot/dts/redwood.dts @@ -234,10 +234,132 @@ has-inverted-stacr-oc; has-new-stacr-staopc; }; + }; + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x10000000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + /* This drives busses 10 to 0x1f */ + bus-range = <0x10 0x1f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x10001000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 10 to 0x1f */ + bus-range = <0x20 0x2f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; + }; + + PCIE2: pciex@d40000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex"; + primary; + port = <0x2>; /* port number */ + reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */ + 0x0000000c 0x10002000 0x00001000>; /* Registers */ + dcr-reg = <0x140 0x020>; + sdr-base = <0x370>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 10 to 0x1f */ + bus-range = <0x30 0x3f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; }; }; + chosen { linux,stdout-path = "/plb/opb/serial@ef600200"; }; diff --git a/arch/powerpc/configs/44x/icon_defconfig b/arch/powerpc/configs/44x/icon_defconfig new file mode 100644 index 000000000000..277f88c2750f --- /dev/null +++ b/arch/powerpc/configs/44x/icon_defconfig @@ -0,0 +1,1451 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc7 +# Fri May 21 17:40:22 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +# CONFIG_LOGBUFFER is not set +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +CONFIG_ICON=y +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_PPC44x_SIMPLE=y +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440SPe=y +CONFIG_STDBINUTILS=y +# CONFIG_IPIC is not set +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_ARCH_HAS_NMI_WATCHDOG is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIEASPM is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_XILINX_SYSACE=y +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=y +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_FUSION=y +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +CONFIG_FUSION_SAS=y +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=y +CONFIG_FUSION_LOGGING=y + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_IBM_NEW_EMAC=y +CONFIG_IBM_NEW_EMAC_RXB=128 +CONFIG_IBM_NEW_EMAC_TXB=64 +CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32 +CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256 +CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0 +# CONFIG_IBM_NEW_EMAC_DEBUG is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +CONFIG_IBM_NEW_EMAC_EMAC4=y +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +# CONFIG_MOUSE_PS2_ALPS is not set +# CONFIG_MOUSE_PS2_LOGIPS2PP is not set +# CONFIG_MOUSE_PS2_SYNAPTICS is not set +# CONFIG_MOUSE_PS2_TRACKPOINT is not set +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_BOOTCOUNT is not set +# CONFIG_DISPLAY_PDSP1880 is not set +# CONFIG_MUCMC52_IO is not set +# CONFIG_UC101_IO is not set +# CONFIG_SRAM is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_IBM_IIC=y +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +CONFIG_MFD_SM501=y +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SM501=y +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_IRQSTACKS is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_PPC4XX is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index a9b91ed3d4b9..2048a6aeea91 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -21,6 +21,7 @@ /* operations for longs and pointers */ #define PPC_LL stringify_in_c(ld) #define PPC_STL stringify_in_c(std) +#define PPC_STLU stringify_in_c(stdu) #define PPC_LCMPI stringify_in_c(cmpdi) #define PPC_LONG stringify_in_c(.llong) #define PPC_LONG_ALIGN stringify_in_c(.balign 8) @@ -44,6 +45,7 @@ /* operations for longs and pointers */ #define PPC_LL stringify_in_c(lwz) #define PPC_STL stringify_in_c(stw) +#define PPC_STLU stringify_in_c(stwu) #define PPC_LCMPI stringify_in_c(cmpwi) #define PPC_LONG stringify_in_c(.long) #define PPC_LONG_ALIGN stringify_in_c(.balign 4) diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h index 2c15212e1700..065c590c991d 100644 --- a/arch/powerpc/include/asm/bug.h +++ b/arch/powerpc/include/asm/bug.h @@ -85,12 +85,12 @@ } \ } while (0) -#define __WARN() do { \ +#define __WARN_TAINT(taint) do { \ __asm__ __volatile__( \ "1: twi 31,0,0\n" \ _EMIT_BUG_ENTRY \ : : "i" (__FILE__), "i" (__LINE__), \ - "i" (BUGFLAG_WARNING), \ + "i" (BUGFLAG_TAINT(taint)), \ "i" (sizeof(struct bug_entry))); \ } while (0) @@ -104,7 +104,7 @@ "1: "PPC_TLNEI" %4,0\n" \ _EMIT_BUG_ENTRY \ : : "i" (__FILE__), "i" (__LINE__), \ - "i" (BUGFLAG_WARNING), \ + "i" (BUGFLAG_TAINT(TAINT_WARN)), \ "i" (sizeof(struct bug_entry)), \ "r" (__ret_warn_on)); \ } \ diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index 725634fc18c6..4b509411ad8a 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -42,7 +42,7 @@ extern struct ppc64_caches ppc64_caches; #endif /* __powerpc64__ && ! __ASSEMBLY__ */ #if !defined(__ASSEMBLY__) -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index e3cba4e1eb34..b0b21134f61a 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -70,6 +70,7 @@ struct pt_regs; extern int machine_check_generic(struct pt_regs *regs); extern int machine_check_4xx(struct pt_regs *regs); extern int machine_check_440A(struct pt_regs *regs); +extern int machine_check_e500mc(struct pt_regs *regs); extern int machine_check_e500(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs); diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h index 6d94d27ed850..a3954e4fcbe2 100644 --- a/arch/powerpc/include/asm/device.h +++ b/arch/powerpc/include/asm/device.h @@ -10,9 +10,6 @@ struct dma_map_ops; struct device_node; struct dev_archdata { - /* Optional pointer to an OF device node */ - struct device_node *of_node; - /* DMA operations on that device */ struct dma_map_ops *dma_ops; @@ -30,19 +27,8 @@ struct dev_archdata { #endif }; -static inline void dev_archdata_set_node(struct dev_archdata *ad, - struct device_node *np) -{ - ad->of_node = np; -} - -static inline struct device_node * -dev_archdata_get_node(const struct dev_archdata *ad) -{ - return ad->of_node; -} - struct pdev_archdata { + u64 dma_mask; }; #endif /* _ASM_POWERPC_DEVICE_H */ diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h index a6ca6da1430b..2a9cd74a841e 100644 --- a/arch/powerpc/include/asm/kexec.h +++ b/arch/powerpc/include/asm/kexec.h @@ -2,6 +2,18 @@ #define _ASM_POWERPC_KEXEC_H #ifdef __KERNEL__ +#ifdef CONFIG_FSL_BOOKE + +/* + * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory + * and therefore we can only deal with memory within this range + */ +#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) +#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) +#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL) + +#else + /* * Maximum page that is mapped directly into kernel memory. * XXX: Since we copy virt we can use any page we allocate @@ -21,6 +33,7 @@ /* TASK_SIZE, probably left over from use_mm ?? */ #define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE #endif +#endif #define KEXEC_CONTROL_PAGE_SIZE 4096 diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h index 81f3b0b5601e..6c5547d82bbe 100644 --- a/arch/powerpc/include/asm/kvm.h +++ b/arch/powerpc/include/asm/kvm.h @@ -77,4 +77,14 @@ struct kvm_debug_exit_arch { struct kvm_guest_debug_arch { }; +#define KVM_REG_MASK 0x001f +#define KVM_REG_EXT_MASK 0xffe0 +#define KVM_REG_GPR 0x0000 +#define KVM_REG_FPR 0x0020 +#define KVM_REG_QPR 0x0040 +#define KVM_REG_FQPR 0x0060 + +#define KVM_INTERRUPT_SET -1U +#define KVM_INTERRUPT_UNSET -2U + #endif /* __LINUX_KVM_POWERPC_H */ diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h index aadf2dd6f84e..c5ea4cda34b3 100644 --- a/arch/powerpc/include/asm/kvm_asm.h +++ b/arch/powerpc/include/asm/kvm_asm.h @@ -88,6 +88,8 @@ #define BOOK3S_HFLAG_DCBZ32 0x1 #define BOOK3S_HFLAG_SLB 0x2 +#define BOOK3S_HFLAG_PAIRED_SINGLE 0x4 +#define BOOK3S_HFLAG_NATIVE_PS 0x8 #define RESUME_FLAG_NV (1<<0) /* Reload guest nonvolatile state? */ #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index db7db0a96967..6f74d93725a0 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -22,46 +22,47 @@ #include <linux/types.h> #include <linux/kvm_host.h> -#include <asm/kvm_book3s_64_asm.h> +#include <asm/kvm_book3s_asm.h> struct kvmppc_slb { u64 esid; u64 vsid; u64 orige; u64 origv; - bool valid; - bool Ks; - bool Kp; - bool nx; - bool large; /* PTEs are 16MB */ - bool tb; /* 1TB segment */ - bool class; + bool valid : 1; + bool Ks : 1; + bool Kp : 1; + bool nx : 1; + bool large : 1; /* PTEs are 16MB */ + bool tb : 1; /* 1TB segment */ + bool class : 1; }; struct kvmppc_sr { u32 raw; u32 vsid; - bool Ks; - bool Kp; - bool nx; + bool Ks : 1; + bool Kp : 1; + bool nx : 1; + bool valid : 1; }; struct kvmppc_bat { u64 raw; u32 bepi; u32 bepi_mask; - bool vs; - bool vp; u32 brpn; u8 wimg; u8 pp; + bool vs : 1; + bool vp : 1; }; struct kvmppc_sid_map { u64 guest_vsid; u64 guest_esid; u64 host_vsid; - bool valid; + bool valid : 1; }; #define SID_MAP_BITS 9 @@ -70,7 +71,7 @@ struct kvmppc_sid_map { struct kvmppc_vcpu_book3s { struct kvm_vcpu vcpu; - struct kvmppc_book3s_shadow_vcpu shadow_vcpu; + struct kvmppc_book3s_shadow_vcpu *shadow_vcpu; struct kvmppc_sid_map sid_map[SID_MAP_NUM]; struct kvmppc_slb slb[64]; struct { @@ -82,9 +83,10 @@ struct kvmppc_vcpu_book3s { struct kvmppc_bat ibat[8]; struct kvmppc_bat dbat[8]; u64 hid[6]; + u64 gqr[8]; int slb_nr; + u32 dsisr; u64 sdr1; - u64 dsisr; u64 hior; u64 msr_mask; u64 vsid_first; @@ -98,15 +100,15 @@ struct kvmppc_vcpu_book3s { #define CONTEXT_GUEST 1 #define CONTEXT_GUEST_END 2 -#define VSID_REAL 0xfffffffffff00000 -#define VSID_REAL_DR 0xffffffffffe00000 -#define VSID_REAL_IR 0xffffffffffd00000 -#define VSID_BAT 0xffffffffffc00000 -#define VSID_PR 0x8000000000000000 +#define VSID_REAL 0x1fffffffffc00000ULL +#define VSID_BAT 0x1fffffffffb00000ULL +#define VSID_REAL_DR 0x2000000000000000ULL +#define VSID_REAL_IR 0x4000000000000000ULL +#define VSID_PR 0x8000000000000000ULL -extern void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 ea, u64 ea_mask); +extern void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong ea, ulong ea_mask); extern void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 vp, u64 vp_mask); -extern void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end); +extern void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end); extern void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 new_msr); extern void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu); extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu); @@ -114,11 +116,13 @@ extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte); extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr); extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu); extern struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data); -extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr, bool data); -extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr); +extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data); +extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data); extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec); extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper, u32 val); +extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr); +extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu); extern u32 kvmppc_trampoline_lowmem; extern u32 kvmppc_trampoline_enter; @@ -126,6 +130,8 @@ extern void kvmppc_rmcall(ulong srr0, ulong srr1); extern void kvmppc_load_up_fpu(void); extern void kvmppc_load_up_altivec(void); extern void kvmppc_load_up_vsx(void); +extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst); +extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst); static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu) { @@ -140,7 +146,108 @@ static inline ulong dsisr(void) } extern void kvm_return_point(void); +static inline struct kvmppc_book3s_shadow_vcpu *to_svcpu(struct kvm_vcpu *vcpu); + +static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) +{ + if ( num < 14 ) { + to_svcpu(vcpu)->gpr[num] = val; + to_book3s(vcpu)->shadow_vcpu->gpr[num] = val; + } else + vcpu->arch.gpr[num] = val; +} + +static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num) +{ + if ( num < 14 ) + return to_svcpu(vcpu)->gpr[num]; + else + return vcpu->arch.gpr[num]; +} + +static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) +{ + to_svcpu(vcpu)->cr = val; + to_book3s(vcpu)->shadow_vcpu->cr = val; +} + +static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->cr; +} + +static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val) +{ + to_svcpu(vcpu)->xer = val; + to_book3s(vcpu)->shadow_vcpu->xer = val; +} + +static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->xer; +} + +static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) +{ + to_svcpu(vcpu)->ctr = val; +} + +static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->ctr; +} + +static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) +{ + to_svcpu(vcpu)->lr = val; +} + +static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->lr; +} + +static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) +{ + to_svcpu(vcpu)->pc = val; +} + +static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->pc; +} + +static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu) +{ + ulong pc = kvmppc_get_pc(vcpu); + struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu); + + /* Load the instruction manually if it failed to do so in the + * exit path */ + if (svcpu->last_inst == KVM_INST_FETCH_FAILED) + kvmppc_ld(vcpu, &pc, sizeof(u32), &svcpu->last_inst, false); + + return svcpu->last_inst; +} + +static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu) +{ + return to_svcpu(vcpu)->fault_dar; +} + +/* Magic register values loaded into r3 and r4 before the 'sc' assembly + * instruction for the OSI hypercalls */ +#define OSI_SC_MAGIC_R3 0x113724FA +#define OSI_SC_MAGIC_R4 0x77810F9B #define INS_DCBZ 0x7c0007ec +/* Also add subarch specific defines */ + +#ifdef CONFIG_PPC_BOOK3S_32 +#include <asm/kvm_book3s_32.h> +#else +#include <asm/kvm_book3s_64.h> +#endif + #endif /* __ASM_KVM_BOOK3S_H__ */ diff --git a/arch/powerpc/include/asm/kvm_book3s_32.h b/arch/powerpc/include/asm/kvm_book3s_32.h new file mode 100644 index 000000000000..de604db135f5 --- /dev/null +++ b/arch/powerpc/include/asm/kvm_book3s_32.h @@ -0,0 +1,42 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright SUSE Linux Products GmbH 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +#ifndef __ASM_KVM_BOOK3S_32_H__ +#define __ASM_KVM_BOOK3S_32_H__ + +static inline struct kvmppc_book3s_shadow_vcpu *to_svcpu(struct kvm_vcpu *vcpu) +{ + return to_book3s(vcpu)->shadow_vcpu; +} + +#define PTE_SIZE 12 +#define VSID_ALL 0 +#define SR_INVALID 0x00000001 /* VSID 1 should always be unused */ +#define SR_KP 0x20000000 +#define PTE_V 0x80000000 +#define PTE_SEC 0x00000040 +#define PTE_M 0x00000010 +#define PTE_R 0x00000100 +#define PTE_C 0x00000080 + +#define SID_SHIFT 28 +#define ESID_MASK 0xf0000000 +#define VSID_MASK 0x00fffffff0000000ULL + +#endif /* __ASM_KVM_BOOK3S_32_H__ */ diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h new file mode 100644 index 000000000000..4cadd612d575 --- /dev/null +++ b/arch/powerpc/include/asm/kvm_book3s_64.h @@ -0,0 +1,28 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright SUSE Linux Products GmbH 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +#ifndef __ASM_KVM_BOOK3S_64_H__ +#define __ASM_KVM_BOOK3S_64_H__ + +static inline struct kvmppc_book3s_shadow_vcpu *to_svcpu(struct kvm_vcpu *vcpu) +{ + return &get_paca()->shadow_vcpu; +} + +#endif /* __ASM_KVM_BOOK3S_64_H__ */ diff --git a/arch/powerpc/include/asm/kvm_book3s_64_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h index 183461b48407..36fdb3aff30b 100644 --- a/arch/powerpc/include/asm/kvm_book3s_64_asm.h +++ b/arch/powerpc/include/asm/kvm_book3s_asm.h @@ -22,7 +22,7 @@ #ifdef __ASSEMBLY__ -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER +#ifdef CONFIG_KVM_BOOK3S_HANDLER #include <asm/kvm_asm.h> @@ -55,7 +55,7 @@ kvmppc_resume_\intno: .macro DO_KVM intno .endm -#endif /* CONFIG_KVM_BOOK3S_64_HANDLER */ +#endif /* CONFIG_KVM_BOOK3S_HANDLER */ #else /*__ASSEMBLY__ */ @@ -63,12 +63,33 @@ struct kvmppc_book3s_shadow_vcpu { ulong gpr[14]; u32 cr; u32 xer; + + u32 fault_dsisr; + u32 last_inst; + ulong ctr; + ulong lr; + ulong pc; + ulong shadow_srr1; + ulong fault_dar; + ulong host_r1; ulong host_r2; ulong handler; ulong scratch0; ulong scratch1; ulong vmhandler; + u8 in_guest; + +#ifdef CONFIG_PPC_BOOK3S_32 + u32 sr[16]; /* Guest SRs */ +#endif +#ifdef CONFIG_PPC_BOOK3S_64 + u8 slb_max; /* highest used guest slb entry */ + struct { + u64 esid; + u64 vsid; + } slb[64]; /* guest SLB */ +#endif }; #endif /*__ASSEMBLY__ */ diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h new file mode 100644 index 000000000000..9c9ba3d59b1b --- /dev/null +++ b/arch/powerpc/include/asm/kvm_booke.h @@ -0,0 +1,96 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright SUSE Linux Products GmbH 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +#ifndef __ASM_KVM_BOOKE_H__ +#define __ASM_KVM_BOOKE_H__ + +#include <linux/types.h> +#include <linux/kvm_host.h> + +static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) +{ + vcpu->arch.gpr[num] = val; +} + +static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num) +{ + return vcpu->arch.gpr[num]; +} + +static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) +{ + vcpu->arch.cr = val; +} + +static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.cr; +} + +static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val) +{ + vcpu->arch.xer = val; +} + +static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.xer; +} + +static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.last_inst; +} + +static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) +{ + vcpu->arch.ctr = val; +} + +static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.ctr; +} + +static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) +{ + vcpu->arch.lr = val; +} + +static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.lr; +} + +static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) +{ + vcpu->arch.pc = val; +} + +static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.pc; +} + +static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.fault_dear; +} + +#endif /* __ASM_KVM_BOOKE_H__ */ diff --git a/arch/powerpc/include/asm/kvm_fpu.h b/arch/powerpc/include/asm/kvm_fpu.h new file mode 100644 index 000000000000..94f05de9ad04 --- /dev/null +++ b/arch/powerpc/include/asm/kvm_fpu.h @@ -0,0 +1,85 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright Novell Inc. 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +#ifndef __ASM_KVM_FPU_H__ +#define __ASM_KVM_FPU_H__ + +#include <linux/types.h> + +extern void fps_fres(struct thread_struct *t, u32 *dst, u32 *src1); +extern void fps_frsqrte(struct thread_struct *t, u32 *dst, u32 *src1); +extern void fps_fsqrts(struct thread_struct *t, u32 *dst, u32 *src1); + +extern void fps_fadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2); +extern void fps_fdivs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2); +extern void fps_fmuls(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2); +extern void fps_fsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2); + +extern void fps_fmadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2, + u32 *src3); +extern void fps_fmsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2, + u32 *src3); +extern void fps_fnmadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2, + u32 *src3); +extern void fps_fnmsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2, + u32 *src3); +extern void fps_fsel(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2, + u32 *src3); + +#define FPD_ONE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \ + u64 *dst, u64 *src1); +#define FPD_TWO_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \ + u64 *dst, u64 *src1, u64 *src2); +#define FPD_THREE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \ + u64 *dst, u64 *src1, u64 *src2, u64 *src3); + +extern void fpd_fcmpu(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2); +extern void fpd_fcmpo(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2); + +FPD_ONE_IN(fsqrts) +FPD_ONE_IN(frsqrtes) +FPD_ONE_IN(fres) +FPD_ONE_IN(frsp) +FPD_ONE_IN(fctiw) +FPD_ONE_IN(fctiwz) +FPD_ONE_IN(fsqrt) +FPD_ONE_IN(fre) +FPD_ONE_IN(frsqrte) +FPD_ONE_IN(fneg) +FPD_ONE_IN(fabs) +FPD_TWO_IN(fadds) +FPD_TWO_IN(fsubs) +FPD_TWO_IN(fdivs) +FPD_TWO_IN(fmuls) +FPD_TWO_IN(fcpsgn) +FPD_TWO_IN(fdiv) +FPD_TWO_IN(fadd) +FPD_TWO_IN(fmul) +FPD_TWO_IN(fsub) +FPD_THREE_IN(fmsubs) +FPD_THREE_IN(fmadds) +FPD_THREE_IN(fnmsubs) +FPD_THREE_IN(fnmadds) +FPD_THREE_IN(fsel) +FPD_THREE_IN(fmsub) +FPD_THREE_IN(fmadd) +FPD_THREE_IN(fnmsub) +FPD_THREE_IN(fnmadd) + +#endif diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index 5e5bae7e152f..0c9ad869decd 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -66,7 +66,7 @@ struct kvm_vcpu_stat { u32 dec_exits; u32 ext_intr_exits; u32 halt_wakeup; -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S u32 pf_storage; u32 pf_instruc; u32 sp_storage; @@ -124,12 +124,12 @@ struct kvm_arch { }; struct kvmppc_pte { - u64 eaddr; + ulong eaddr; u64 vpage; - u64 raddr; - bool may_read; - bool may_write; - bool may_execute; + ulong raddr; + bool may_read : 1; + bool may_write : 1; + bool may_execute : 1; }; struct kvmppc_mmu { @@ -145,7 +145,7 @@ struct kvmppc_mmu { int (*xlate)(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data); void (*reset_msr)(struct kvm_vcpu *vcpu); void (*tlbie)(struct kvm_vcpu *vcpu, ulong addr, bool large); - int (*esid_to_vsid)(struct kvm_vcpu *vcpu, u64 esid, u64 *vsid); + int (*esid_to_vsid)(struct kvm_vcpu *vcpu, ulong esid, u64 *vsid); u64 (*ea_to_vp)(struct kvm_vcpu *vcpu, gva_t eaddr, bool data); bool (*is_dcbz32)(struct kvm_vcpu *vcpu); }; @@ -160,7 +160,7 @@ struct hpte_cache { struct kvm_vcpu_arch { ulong host_stack; u32 host_pid; -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S ulong host_msr; ulong host_r2; void *host_retip; @@ -175,7 +175,7 @@ struct kvm_vcpu_arch { ulong gpr[32]; u64 fpr[32]; - u32 fpscr; + u64 fpscr; #ifdef CONFIG_ALTIVEC vector128 vr[32]; @@ -186,19 +186,23 @@ struct kvm_vcpu_arch { u64 vsr[32]; #endif +#ifdef CONFIG_PPC_BOOK3S + /* For Gekko paired singles */ + u32 qpr[32]; +#endif + +#ifdef CONFIG_BOOKE ulong pc; ulong ctr; ulong lr; -#ifdef CONFIG_BOOKE ulong xer; u32 cr; #endif ulong msr; -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S ulong shadow_msr; - ulong shadow_srr1; ulong hflags; ulong guest_owned_ext; #endif @@ -253,20 +257,22 @@ struct kvm_vcpu_arch { struct dentry *debugfs_exit_timing; #endif +#ifdef CONFIG_BOOKE u32 last_inst; -#ifdef CONFIG_PPC64 - ulong fault_dsisr; -#endif ulong fault_dear; ulong fault_esr; ulong queued_dear; ulong queued_esr; +#endif gpa_t paddr_accessed; u8 io_gpr; /* GPR used as IO source/target */ u8 mmio_is_bigendian; + u8 mmio_sign_extend; u8 dcr_needed; u8 dcr_is_write; + u8 osi_needed; + u8 osi_enabled; u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */ @@ -275,7 +281,7 @@ struct kvm_vcpu_arch { u64 dec_jiffies; unsigned long pending_exceptions; -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S struct hpte_cache hpte_cache[HPTEG_CACHE_NUM]; int hpte_cache_offset; #endif diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index e2642829e435..18d139ec2d22 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -30,6 +30,8 @@ #include <linux/kvm_host.h> #ifdef CONFIG_PPC_BOOK3S #include <asm/kvm_book3s.h> +#else +#include <asm/kvm_booke.h> #endif enum emulation_result { @@ -37,6 +39,7 @@ enum emulation_result { EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ EMULATE_DO_DCR, /* kvm_run filled with DCR request */ EMULATE_FAIL, /* can't emulate this instruction */ + EMULATE_AGAIN, /* something went wrong. go again */ }; extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu); @@ -48,8 +51,11 @@ extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu); extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int rt, unsigned int bytes, int is_bigendian); +extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu, + unsigned int rt, unsigned int bytes, + int is_bigendian); extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, - u32 val, unsigned int bytes, int is_bigendian); + u64 val, unsigned int bytes, int is_bigendian); extern int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu); @@ -63,6 +69,7 @@ extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr, extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode); extern void kvmppc_mmu_switch_pid(struct kvm_vcpu *vcpu, u32 pid); extern void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu); +extern int kvmppc_mmu_init(struct kvm_vcpu *vcpu); extern int kvmppc_mmu_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr); extern int kvmppc_mmu_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr); extern gpa_t kvmppc_mmu_xlate(struct kvm_vcpu *vcpu, unsigned int gtlb_index, @@ -88,6 +95,8 @@ extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu); extern void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu); extern void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq); +extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, + struct kvm_interrupt *irq); extern int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int op, int *advance); @@ -99,81 +108,37 @@ extern void kvmppc_booke_exit(void); extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu); -#ifdef CONFIG_PPC_BOOK3S - -/* We assume we're always acting on the current vcpu */ - -static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) -{ - if ( num < 14 ) { - get_paca()->shadow_vcpu.gpr[num] = val; - to_book3s(vcpu)->shadow_vcpu.gpr[num] = val; - } else - vcpu->arch.gpr[num] = val; -} - -static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num) -{ - if ( num < 14 ) - return get_paca()->shadow_vcpu.gpr[num]; - else - return vcpu->arch.gpr[num]; -} - -static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) -{ - get_paca()->shadow_vcpu.cr = val; - to_book3s(vcpu)->shadow_vcpu.cr = val; -} - -static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu) -{ - return get_paca()->shadow_vcpu.cr; -} - -static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val) -{ - get_paca()->shadow_vcpu.xer = val; - to_book3s(vcpu)->shadow_vcpu.xer = val; -} - -static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu) +/* + * Cuts out inst bits with ordering according to spec. + * That means the leftmost bit is zero. All given bits are included. + */ +static inline u32 kvmppc_get_field(u64 inst, int msb, int lsb) { - return get_paca()->shadow_vcpu.xer; -} + u32 r; + u32 mask; -#else + BUG_ON(msb > lsb); -static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) -{ - vcpu->arch.gpr[num] = val; -} + mask = (1 << (lsb - msb + 1)) - 1; + r = (inst >> (63 - lsb)) & mask; -static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num) -{ - return vcpu->arch.gpr[num]; + return r; } -static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) +/* + * Replaces inst bits with ordering according to spec. + */ +static inline u32 kvmppc_set_field(u64 inst, int msb, int lsb, int value) { - vcpu->arch.cr = val; -} + u32 r; + u32 mask; -static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.cr; -} + BUG_ON(msb > lsb); -static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val) -{ - vcpu->arch.xer = val; -} + mask = ((1 << (lsb - msb + 1)) - 1) << (63 - lsb); + r = (inst & ~mask) | ((value << (63 - lsb)) & mask); -static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.xer; + return r; } -#endif - #endif /* __POWERPC_KVM_PPC_H__ */ diff --git a/arch/powerpc/include/asm/macio.h b/arch/powerpc/include/asm/macio.h index a062c57696d0..675e159b5ef4 100644 --- a/arch/powerpc/include/asm/macio.h +++ b/arch/powerpc/include/asm/macio.h @@ -108,7 +108,7 @@ static inline void* macio_get_drvdata(struct macio_dev *dev) static inline struct device_node *macio_get_of_node(struct macio_dev *mdev) { - return mdev->ofdev.node; + return mdev->ofdev.dev.of_node; } #ifdef CONFIG_PCI @@ -123,10 +123,6 @@ static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev) */ struct macio_driver { - char *name; - struct of_device_id *match_table; - struct module *owner; - int (*probe)(struct macio_dev* dev, const struct of_device_id *match); int (*remove)(struct macio_dev* dev); diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h index 26383e0778aa..81fb41289d6c 100644 --- a/arch/powerpc/include/asm/mmu_context.h +++ b/arch/powerpc/include/asm/mmu_context.h @@ -27,6 +27,8 @@ extern int __init_new_context(void); extern void __destroy_context(int context_id); static inline void mmu_context_init(void) { } #else +extern unsigned long __init_new_context(void); +extern void __destroy_context(unsigned long context_id); extern void mmu_context_init(void); #endif diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h index 42561f4f032d..ecc4fc69ac13 100644 --- a/arch/powerpc/include/asm/mpc52xx_psc.h +++ b/arch/powerpc/include/asm/mpc52xx_psc.h @@ -248,6 +248,7 @@ struct mpc52xx_psc_fifo { u16 tflwfptr; /* PSC + 0x9e */ }; +#define MPC512x_PSC_FIFO_EOF 0x100 #define MPC512x_PSC_FIFO_RESET_SLICE 0x80 #define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01 #define MPC512x_PSC_FIFO_ENABLE_DMA 0x04 diff --git a/arch/powerpc/include/asm/of_device.h b/arch/powerpc/include/asm/of_device.h index a64debf177dc..444e97e2982e 100644 --- a/arch/powerpc/include/asm/of_device.h +++ b/arch/powerpc/include/asm/of_device.h @@ -12,9 +12,8 @@ */ struct of_device { - struct device_node *node; /* to be obsoleted */ - u64 dma_mask; /* DMA mask */ struct device dev; /* Generic device interface */ + struct pdev_archdata archdata; }; extern struct of_device *of_device_alloc(struct device_node *np, diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index 971dfa4815f0..8ce7963ad41d 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h @@ -23,7 +23,7 @@ #include <asm/page.h> #include <asm/exception-64e.h> #ifdef CONFIG_KVM_BOOK3S_64_HANDLER -#include <asm/kvm_book3s_64_asm.h> +#include <asm/kvm_book3s_asm.h> #endif register struct paca_struct *local_paca asm("r13"); @@ -137,15 +137,9 @@ struct paca_struct { u64 startpurr; /* PURR/TB value snapshot */ u64 startspurr; /* SPURR value snapshot */ -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER - struct { - u64 esid; - u64 vsid; - } kvm_slb[64]; /* guest SLB */ +#ifdef CONFIG_KVM_BOOK3S_HANDLER /* We use this to store guest state in */ struct kvmppc_book3s_shadow_vcpu shadow_vcpu; - u8 kvm_slb_max; /* highest used guest slb entry */ - u8 kvm_in_guest; /* are we inside the guest? */ #endif }; diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h index bfc4e027e2ad..358ff14ea25e 100644 --- a/arch/powerpc/include/asm/page_64.h +++ b/arch/powerpc/include/asm/page_64.h @@ -162,14 +162,6 @@ do { \ #endif /* !CONFIG_HUGETLB_PAGE */ -#ifdef MODULE -#define __page_aligned __attribute__((__aligned__(PAGE_SIZE))) -#else -#define __page_aligned \ - __attribute__((__aligned__(PAGE_SIZE), \ - __section__(".data.page_aligned"))) -#endif - #define VM_DATA_DEFAULT_FLAGS \ (test_thread_flag(TIF_32BIT) ? \ VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 221ba6240464..7492fe8ad6e4 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -229,6 +229,9 @@ struct thread_struct { unsigned long spefscr; /* SPE & eFP status */ int used_spe; /* set if process has used spe */ #endif /* CONFIG_SPE */ +#ifdef CONFIG_KVM_BOOK3S_32_HANDLER + void* kvm_shadow_vcpu; /* KVM internal data */ +#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ }; #define ARCH_MIN_TASKALIGN 16 diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b68f025924a8..d62fdf4e504b 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -293,10 +293,12 @@ #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ #define HID1_PS (1<<16) /* 750FX PLL selection */ #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ +#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_IABR2 0x3FA /* 83xx */ #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ #define SPRN_HID4 0x3F4 /* 970 HID4 */ +#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ #define SPRN_HID5 0x3F6 /* 970 HID5 */ #define SPRN_HID6 0x3F9 /* BE HID 6 */ #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ @@ -465,6 +467,14 @@ #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ #define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ +#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ +#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ +#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ +#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ +#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ +#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ + #define SPRN_SCOMC 0x114 /* SCOM Access Control */ #define SPRN_SCOMD 0x115 /* SCOM Access DATA */ diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 5304a37ba425..2360317179a9 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -4,6 +4,12 @@ * are not true Book E PowerPCs, they borrowed a number of features * before Book E was finalized, and are included here as well. Unfortunatly, * they sometimes used different locations than true Book E CPUs did. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. */ #ifdef __KERNEL__ #ifndef __ASM_POWERPC_REG_BOOKE_H__ @@ -88,6 +94,7 @@ #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ +#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */ #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ #define SPRN_MCSR 0x23C /* Machine Check Status Register */ @@ -196,8 +203,11 @@ #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ #ifdef CONFIG_E500 +/* All e500 */ #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ + +/* e500v1/v2 */ #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ @@ -209,12 +219,20 @@ #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ -/* e500 parts may set unused bits in MCSR; mask these off */ -#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \ - MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \ - MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \ - MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR) +/* e500mc */ +#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */ +#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */ +#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */ +#define MCSR_MAV 0x00080000UL /* MCAR address valid */ +#define MCSR_MEA 0x00040000UL /* MCAR is effective address */ +#define MCSR_IF 0x00010000UL /* Instruction Fetch */ +#define MCSR_LD 0x00008000UL /* Load */ +#define MCSR_ST 0x00004000UL /* Store */ +#define MCSR_LDG 0x00002000UL /* Guarded Load */ +#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */ +#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */ #endif + #ifdef CONFIG_E200 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ @@ -225,11 +243,6 @@ #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered store or cache line push */ - -/* e200 parts may set unused bits in MCSR; mask these off */ -#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \ - MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \ - MCSR_BUS_WRERR) #endif /* Bit definitions for the DBSR. */ diff --git a/arch/powerpc/include/asm/scatterlist.h b/arch/powerpc/include/asm/scatterlist.h index 912bf597870f..34cc78fd0ef4 100644 --- a/arch/powerpc/include/asm/scatterlist.h +++ b/arch/powerpc/include/asm/scatterlist.h @@ -9,38 +9,12 @@ * 2 of the License, or (at your option) any later version. */ -#ifdef __KERNEL__ -#include <linux/types.h> #include <asm/dma.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - unsigned int length; - - /* For TCE or SWIOTLB support */ - dma_addr_t dma_address; - u32 dma_length; -}; - -/* - * These macros should be used after a dma_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->dma_length) +#include <asm-generic/scatterlist.h> #ifdef __powerpc64__ #define ISA_DMA_THRESHOLD (~0UL) #endif - #define ARCH_HAS_SG_CHAIN -#endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_SCATTERLIST_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 877326320e74..58d0572de6f9 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -57,8 +57,12 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_E500) += idle_e500.o obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o obj-$(CONFIG_TAU) += tau_6xx.o -obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \ - swsusp_$(CONFIG_WORD_SIZE).o +obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o +ifeq ($(CONFIG_FSL_BOOKE),y) +obj-$(CONFIG_HIBERNATION) += swsusp_booke.o +else +obj-$(CONFIG_HIBERNATION) += swsusp_$(CONFIG_WORD_SIZE).o +endif obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o obj-$(CONFIG_44x) += cpu_setup_44x.o diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 28a686fb269c..496cc5b3984f 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -50,6 +50,9 @@ #endif #ifdef CONFIG_KVM #include <linux/kvm_host.h> +#ifndef CONFIG_BOOKE +#include <asm/kvm_book3s.h> +#endif #endif #ifdef CONFIG_PPC32 @@ -105,6 +108,9 @@ int main(void) DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe)); #endif /* CONFIG_SPE */ #endif /* CONFIG_PPC64 */ +#ifdef CONFIG_KVM_BOOK3S_32_HANDLER + DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); +#endif DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags)); @@ -191,33 +197,9 @@ int main(void) DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset)); DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); #ifdef CONFIG_KVM_BOOK3S_64_HANDLER - DEFINE(PACA_KVM_IN_GUEST, offsetof(struct paca_struct, kvm_in_guest)); - DEFINE(PACA_KVM_SLB, offsetof(struct paca_struct, kvm_slb)); - DEFINE(PACA_KVM_SLB_MAX, offsetof(struct paca_struct, kvm_slb_max)); - DEFINE(PACA_KVM_CR, offsetof(struct paca_struct, shadow_vcpu.cr)); - DEFINE(PACA_KVM_XER, offsetof(struct paca_struct, shadow_vcpu.xer)); - DEFINE(PACA_KVM_R0, offsetof(struct paca_struct, shadow_vcpu.gpr[0])); - DEFINE(PACA_KVM_R1, offsetof(struct paca_struct, shadow_vcpu.gpr[1])); - DEFINE(PACA_KVM_R2, offsetof(struct paca_struct, shadow_vcpu.gpr[2])); - DEFINE(PACA_KVM_R3, offsetof(struct paca_struct, shadow_vcpu.gpr[3])); - DEFINE(PACA_KVM_R4, offsetof(struct paca_struct, shadow_vcpu.gpr[4])); - DEFINE(PACA_KVM_R5, offsetof(struct paca_struct, shadow_vcpu.gpr[5])); - DEFINE(PACA_KVM_R6, offsetof(struct paca_struct, shadow_vcpu.gpr[6])); - DEFINE(PACA_KVM_R7, offsetof(struct paca_struct, shadow_vcpu.gpr[7])); - DEFINE(PACA_KVM_R8, offsetof(struct paca_struct, shadow_vcpu.gpr[8])); - DEFINE(PACA_KVM_R9, offsetof(struct paca_struct, shadow_vcpu.gpr[9])); - DEFINE(PACA_KVM_R10, offsetof(struct paca_struct, shadow_vcpu.gpr[10])); - DEFINE(PACA_KVM_R11, offsetof(struct paca_struct, shadow_vcpu.gpr[11])); - DEFINE(PACA_KVM_R12, offsetof(struct paca_struct, shadow_vcpu.gpr[12])); - DEFINE(PACA_KVM_R13, offsetof(struct paca_struct, shadow_vcpu.gpr[13])); - DEFINE(PACA_KVM_HOST_R1, offsetof(struct paca_struct, shadow_vcpu.host_r1)); - DEFINE(PACA_KVM_HOST_R2, offsetof(struct paca_struct, shadow_vcpu.host_r2)); - DEFINE(PACA_KVM_VMHANDLER, offsetof(struct paca_struct, - shadow_vcpu.vmhandler)); - DEFINE(PACA_KVM_SCRATCH0, offsetof(struct paca_struct, - shadow_vcpu.scratch0)); - DEFINE(PACA_KVM_SCRATCH1, offsetof(struct paca_struct, - shadow_vcpu.scratch1)); + DEFINE(PACA_KVM_SVCPU, offsetof(struct paca_struct, shadow_vcpu)); + DEFINE(SVCPU_SLB, offsetof(struct kvmppc_book3s_shadow_vcpu, slb)); + DEFINE(SVCPU_SLB_MAX, offsetof(struct kvmppc_book3s_shadow_vcpu, slb_max)); #endif #endif /* CONFIG_PPC64 */ @@ -228,8 +210,8 @@ int main(void) /* Interrupt register frame */ DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD); DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); -#ifdef CONFIG_PPC64 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); +#ifdef CONFIG_PPC64 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */ DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); @@ -412,9 +394,6 @@ int main(void) DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack)); DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid)); DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr)); - DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); - DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); - DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.msr)); DEFINE(VCPU_SPRG4, offsetof(struct kvm_vcpu, arch.sprg4)); DEFINE(VCPU_SPRG5, offsetof(struct kvm_vcpu, arch.sprg5)); @@ -422,27 +401,68 @@ int main(void) DEFINE(VCPU_SPRG7, offsetof(struct kvm_vcpu, arch.sprg7)); DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid)); - DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); - DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear)); - DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr)); - - /* book3s_64 */ -#ifdef CONFIG_PPC64 - DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr)); + /* book3s */ +#ifdef CONFIG_PPC_BOOK3S DEFINE(VCPU_HOST_RETIP, offsetof(struct kvm_vcpu, arch.host_retip)); - DEFINE(VCPU_HOST_R2, offsetof(struct kvm_vcpu, arch.host_r2)); DEFINE(VCPU_HOST_MSR, offsetof(struct kvm_vcpu, arch.host_msr)); DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr)); - DEFINE(VCPU_SHADOW_SRR1, offsetof(struct kvm_vcpu, arch.shadow_srr1)); DEFINE(VCPU_TRAMPOLINE_LOWMEM, offsetof(struct kvm_vcpu, arch.trampoline_lowmem)); DEFINE(VCPU_TRAMPOLINE_ENTER, offsetof(struct kvm_vcpu, arch.trampoline_enter)); DEFINE(VCPU_HIGHMEM_HANDLER, offsetof(struct kvm_vcpu, arch.highmem_handler)); DEFINE(VCPU_RMCALL, offsetof(struct kvm_vcpu, arch.rmcall)); DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags)); + DEFINE(VCPU_SVCPU, offsetof(struct kvmppc_vcpu_book3s, shadow_vcpu) - + offsetof(struct kvmppc_vcpu_book3s, vcpu)); + DEFINE(SVCPU_CR, offsetof(struct kvmppc_book3s_shadow_vcpu, cr)); + DEFINE(SVCPU_XER, offsetof(struct kvmppc_book3s_shadow_vcpu, xer)); + DEFINE(SVCPU_CTR, offsetof(struct kvmppc_book3s_shadow_vcpu, ctr)); + DEFINE(SVCPU_LR, offsetof(struct kvmppc_book3s_shadow_vcpu, lr)); + DEFINE(SVCPU_PC, offsetof(struct kvmppc_book3s_shadow_vcpu, pc)); + DEFINE(SVCPU_R0, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[0])); + DEFINE(SVCPU_R1, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[1])); + DEFINE(SVCPU_R2, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[2])); + DEFINE(SVCPU_R3, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[3])); + DEFINE(SVCPU_R4, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[4])); + DEFINE(SVCPU_R5, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[5])); + DEFINE(SVCPU_R6, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[6])); + DEFINE(SVCPU_R7, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[7])); + DEFINE(SVCPU_R8, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[8])); + DEFINE(SVCPU_R9, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[9])); + DEFINE(SVCPU_R10, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[10])); + DEFINE(SVCPU_R11, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[11])); + DEFINE(SVCPU_R12, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[12])); + DEFINE(SVCPU_R13, offsetof(struct kvmppc_book3s_shadow_vcpu, gpr[13])); + DEFINE(SVCPU_HOST_R1, offsetof(struct kvmppc_book3s_shadow_vcpu, host_r1)); + DEFINE(SVCPU_HOST_R2, offsetof(struct kvmppc_book3s_shadow_vcpu, host_r2)); + DEFINE(SVCPU_VMHANDLER, offsetof(struct kvmppc_book3s_shadow_vcpu, + vmhandler)); + DEFINE(SVCPU_SCRATCH0, offsetof(struct kvmppc_book3s_shadow_vcpu, + scratch0)); + DEFINE(SVCPU_SCRATCH1, offsetof(struct kvmppc_book3s_shadow_vcpu, + scratch1)); + DEFINE(SVCPU_IN_GUEST, offsetof(struct kvmppc_book3s_shadow_vcpu, + in_guest)); + DEFINE(SVCPU_FAULT_DSISR, offsetof(struct kvmppc_book3s_shadow_vcpu, + fault_dsisr)); + DEFINE(SVCPU_FAULT_DAR, offsetof(struct kvmppc_book3s_shadow_vcpu, + fault_dar)); + DEFINE(SVCPU_LAST_INST, offsetof(struct kvmppc_book3s_shadow_vcpu, + last_inst)); + DEFINE(SVCPU_SHADOW_SRR1, offsetof(struct kvmppc_book3s_shadow_vcpu, + shadow_srr1)); +#ifdef CONFIG_PPC_BOOK3S_32 + DEFINE(SVCPU_SR, offsetof(struct kvmppc_book3s_shadow_vcpu, sr)); +#endif #else DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr)); DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer)); -#endif /* CONFIG_PPC64 */ + DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); + DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); + DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); + DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); + DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear)); + DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr)); +#endif /* CONFIG_PPC_BOOK3S */ #endif #ifdef CONFIG_44x DEFINE(PGD_T_LOG2, PGD_T_LOG2); diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 9556be903e96..87aa0f3c6047 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1840,7 +1840,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .oprofile_cpu_type = "ppc/e500mc", .oprofile_type = PPC_OPROFILE_FSL_EMB, .cpu_setup = __setup_cpu_e500mc, - .machine_check = machine_check_e500, + .machine_check = machine_check_e500mc, .platform = "ppce500mc", }, { /* default match */ diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index 8c066d6a8e4b..b46f2e09bd81 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c @@ -163,6 +163,7 @@ static void crash_kexec_prepare_cpus(int cpu) } /* wait for all the CPUs to hit real mode but timeout if they don't come in */ +#ifdef CONFIG_PPC_STD_MMU_64 static void crash_kexec_wait_realmode(int cpu) { unsigned int msecs; @@ -187,6 +188,7 @@ static void crash_kexec_wait_realmode(int cpu) } mb(); } +#endif /* * This function will be called by secondary cpus or by kexec cpu @@ -445,7 +447,9 @@ void default_machine_crash_shutdown(struct pt_regs *regs) crash_kexec_prepare_cpus(crashing_cpu); cpu_set(crashing_cpu, cpus_in_crash); crash_kexec_stop_spus(); +#ifdef CONFIG_PPC_STD_MMU_64 crash_kexec_wait_realmode(crashing_cpu); +#endif if (ppc_md.kexec_cpu_down) ppc_md.kexec_cpu_down(1, 0); } diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c index 4ff4da2c238b..e7fe218b8697 100644 --- a/arch/powerpc/kernel/dma-swiotlb.c +++ b/arch/powerpc/kernel/dma-swiotlb.c @@ -39,8 +39,8 @@ struct dma_map_ops swiotlb_dma_ops = { .dma_supported = swiotlb_dma_supported, .map_page = swiotlb_map_page, .unmap_page = swiotlb_unmap_page, - .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu, - .sync_single_range_for_device = swiotlb_sync_single_range_for_device, + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, + .sync_single_for_device = swiotlb_sync_single_for_device, .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, .sync_sg_for_device = swiotlb_sync_sg_for_device, .mapping_error = swiotlb_dma_mapping_error, diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index 6c1df5757cd6..8d1de6f31d5a 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c @@ -127,11 +127,11 @@ static inline void dma_direct_sync_sg(struct device *dev, __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction); } -static inline void dma_direct_sync_single_range(struct device *dev, - dma_addr_t dma_handle, unsigned long offset, size_t size, - enum dma_data_direction direction) +static inline void dma_direct_sync_single(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) { - __dma_sync(bus_to_virt(dma_handle+offset), size, direction); + __dma_sync(bus_to_virt(dma_handle), size, direction); } #endif @@ -144,8 +144,8 @@ struct dma_map_ops dma_direct_ops = { .map_page = dma_direct_map_page, .unmap_page = dma_direct_unmap_page, #ifdef CONFIG_NOT_COHERENT_CACHE - .sync_single_range_for_cpu = dma_direct_sync_single_range, - .sync_single_range_for_device = dma_direct_sync_single_range, + .sync_single_for_cpu = dma_direct_sync_single, + .sync_single_for_device = dma_direct_sync_single, .sync_sg_for_cpu = dma_direct_sync_sg, .sync_sg_for_device = dma_direct_sync_sg, #endif diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S new file mode 100644 index 000000000000..beb4d78a2304 --- /dev/null +++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S @@ -0,0 +1,237 @@ + +/* 1. Find the index of the entry we're executing in */ + bl invstr /* Find our address */ +invstr: mflr r6 /* Make it accessible */ + mfmsr r7 + rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ + mfspr r7, SPRN_PID0 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ + mfspr r7,SPRN_MAS1 + andis. r7,r7,MAS1_VALID@h + bne match_TLB + + mfspr r7,SPRN_MMUCFG + rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ + cmpwi r7,3 + bne match_TLB /* skip if NPIDS != 3 */ + + mfspr r7,SPRN_PID1 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ + mfspr r7,SPRN_MAS1 + andis. r7,r7,MAS1_VALID@h + bne match_TLB + mfspr r7, SPRN_PID2 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* Fall through, we had to match */ + +match_TLB: + mfspr r7,SPRN_MAS0 + rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ + + mfspr r7,SPRN_MAS1 /* Insure IPROT set */ + oris r7,r7,MAS1_IPROT@h + mtspr SPRN_MAS1,r7 + tlbwe + +/* 2. Invalidate all entries except the entry we're executing in */ + mfspr r9,SPRN_TLB1CFG + andi. r9,r9,0xfff + li r6,0 /* Set Entry counter to 0 */ +1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ + mtspr SPRN_MAS0,r7 + tlbre + mfspr r7,SPRN_MAS1 + rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ + cmpw r3,r6 + beq skpinv /* Dont update the current execution TLB */ + mtspr SPRN_MAS1,r7 + tlbwe + isync +skpinv: addi r6,r6,1 /* Increment */ + cmpw r6,r9 /* Are we done? */ + bne 1b /* If not, repeat */ + + /* Invalidate TLB0 */ + li r6,0x04 + tlbivax 0,r6 + TLBSYNC + /* Invalidate TLB1 */ + li r6,0x0c + tlbivax 0,r6 + TLBSYNC + +/* 3. Setup a temp mapping and jump to it */ + andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ + addi r5, r5, 0x1 + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ + mtspr SPRN_MAS0,r7 + tlbre + + /* grab and fixup the RPN */ + mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ + rlwinm r6,r6,25,27,31 + li r8,-1 + addi r6,r6,10 + slw r6,r8,r6 /* convert to mask */ + + bl 1f /* Find our address */ +1: mflr r7 + + mfspr r8,SPRN_MAS3 +#ifdef CONFIG_PHYS_64BIT + mfspr r23,SPRN_MAS7 +#endif + and r8,r6,r8 + subfic r9,r6,-4096 + and r9,r9,r7 + + or r25,r8,r9 + ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR) + + /* Just modify the entry ID and EPN for the temp mapping */ + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ + mtspr SPRN_MAS0,r7 + xori r6,r4,1 /* Setup TMP mapping in the other Address space */ + slwi r6,r6,12 + oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l + mtspr SPRN_MAS1,r6 + mfspr r6,SPRN_MAS2 + li r7,0 /* temp EPN = 0 */ + rlwimi r7,r6,0,20,31 + mtspr SPRN_MAS2,r7 + mtspr SPRN_MAS3,r8 + tlbwe + + xori r6,r4,1 + slwi r6,r6,5 /* setup new context with other address space */ + bl 1f /* Find our address */ +1: mflr r9 + rlwimi r7,r9,0,20,31 + addi r7,r7,(2f - 1b) + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi +2: +/* 4. Clear out PIDs & Search info */ + li r6,0 + mtspr SPRN_MAS6,r6 + mtspr SPRN_PID0,r6 + + mfspr r7,SPRN_MMUCFG + rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ + cmpwi r7,3 + bne 2f /* skip if NPIDS != 3 */ + + mtspr SPRN_PID1,r6 + mtspr SPRN_PID2,r6 + +/* 5. Invalidate mapping we started in */ +2: + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ + mtspr SPRN_MAS0,r7 + tlbre + mfspr r6,SPRN_MAS1 + rlwinm r6,r6,0,2,0 /* clear IPROT */ + mtspr SPRN_MAS1,r6 + tlbwe + /* Invalidate TLB1 */ + li r9,0x0c + tlbivax 0,r9 + TLBSYNC + +/* The mapping only needs to be cache-coherent on SMP */ +#ifdef CONFIG_SMP +#define M_IF_SMP MAS2_M +#else +#define M_IF_SMP 0 +#endif + +#if defined(ENTRY_MAPPING_BOOT_SETUP) + +/* 6. Setup KERNELBASE mapping in TLB1[0] */ + lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ + mtspr SPRN_MAS0,r6 + lis r6,(MAS1_VALID|MAS1_IPROT)@h + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l + mtspr SPRN_MAS1,r6 + lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h + ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l + mtspr SPRN_MAS2,r6 + mtspr SPRN_MAS3,r8 + tlbwe + +/* 7. Jump to KERNELBASE mapping */ + lis r6,(KERNELBASE & ~0xfff)@h + ori r6,r6,(KERNELBASE & ~0xfff)@l + +#elif defined(ENTRY_MAPPING_KEXEC_SETUP) +/* + * 6. Setup a 1:1 mapping in TLB1. Esel 0 is unsued, 1 or 2 contains the tmp + * mapping so we start at 3. We setup 8 mappings, each 256MiB in size. This + * will cover the first 2GiB of memory. + */ + + lis r10, (MAS1_VALID|MAS1_IPROT)@h + ori r10,r10, (MAS1_TSIZE(BOOK3E_PAGESZ_256M))@l + li r11, 0 + li r0, 8 + mtctr r0 + +next_tlb_setup: + addi r0, r11, 3 + rlwinm r0, r0, 16, 4, 15 // Compute esel + rlwinm r9, r11, 28, 0, 3 // Compute [ER]PN + oris r0, r0, (MAS0_TLBSEL(1))@h + mtspr SPRN_MAS0,r0 + mtspr SPRN_MAS1,r10 + mtspr SPRN_MAS2,r9 + ori r9, r9, (MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r9 + tlbwe + addi r11, r11, 1 + bdnz+ next_tlb_setup + +/* 7. Jump to our 1:1 mapping */ + li r6, 0 + +#else + #error You need to specify the mapping or not use this at all. +#endif + + lis r7,MSR_KERNEL@h + ori r7,r7,MSR_KERNEL@l + bl 1f /* Find our address */ +1: mflr r9 + rlwimi r6,r9,0,20,31 + addi r6,r6,(2f - 1b) + add r6, r6, r25 + mtspr SPRN_SRR0,r6 + mtspr SPRN_SRR1,r7 + rfi /* start execution out of TLB1[0] entry */ + +/* 8. Clear out the temp mapping */ +2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ + mtspr SPRN_MAS0,r7 + tlbre + mfspr r8,SPRN_MAS1 + rlwinm r8,r8,0,2,0 /* clear IPROT */ + mtspr SPRN_MAS1,r8 + tlbwe + /* Invalidate TLB1 */ + li r9,0x0c + tlbivax 0,r9 + TLBSYNC diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index e025e89fe93e..98c4b29a56f4 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -33,6 +33,7 @@ #include <asm/asm-offsets.h> #include <asm/ptrace.h> #include <asm/bug.h> +#include <asm/kvm_book3s_asm.h> /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ #define LOAD_BAT(n, reg, RA, RB) \ @@ -303,6 +304,7 @@ __secondary_hold_acknowledge: */ #define EXCEPTION(n, label, hdlr, xfer) \ . = n; \ + DO_KVM n; \ label: \ EXCEPTION_PROLOG; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ @@ -358,6 +360,7 @@ i##n: \ * -- paulus. */ . = 0x200 + DO_KVM 0x200 mtspr SPRN_SPRG_SCRATCH0,r10 mtspr SPRN_SPRG_SCRATCH1,r11 mfcr r10 @@ -381,6 +384,7 @@ i##n: \ /* Data access exception. */ . = 0x300 + DO_KVM 0x300 DataAccess: EXCEPTION_PROLOG mfspr r10,SPRN_DSISR @@ -397,6 +401,7 @@ DataAccess: /* Instruction access exception. */ . = 0x400 + DO_KVM 0x400 InstructionAccess: EXCEPTION_PROLOG andis. r0,r9,0x4000 /* no pte found? */ @@ -413,6 +418,7 @@ InstructionAccess: /* Alignment exception */ . = 0x600 + DO_KVM 0x600 Alignment: EXCEPTION_PROLOG mfspr r4,SPRN_DAR @@ -427,6 +433,7 @@ Alignment: /* Floating-point unavailable */ . = 0x800 + DO_KVM 0x800 FPUnavailable: BEGIN_FTR_SECTION /* @@ -450,6 +457,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE) /* System call */ . = 0xc00 + DO_KVM 0xc00 SystemCall: EXCEPTION_PROLOG EXC_XFER_EE_LITE(0xc00, DoSyscall) @@ -467,9 +475,11 @@ SystemCall: * by executing an altivec instruction. */ . = 0xf00 + DO_KVM 0xf00 b PerformanceMonitor . = 0xf20 + DO_KVM 0xf20 b AltiVecUnavailable /* @@ -882,6 +892,10 @@ __secondary_start: RFI #endif /* CONFIG_SMP */ +#ifdef CONFIG_KVM_BOOK3S_HANDLER +#include "../kvm/book3s_rmhandlers.S" +#endif + /* * Those generic dummy functions are kept for CPUs not * included in CONFIG_6xx diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index bed9a29ee383..844a44b64472 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -37,7 +37,7 @@ #include <asm/firmware.h> #include <asm/page_64.h> #include <asm/irqflags.h> -#include <asm/kvm_book3s_64_asm.h> +#include <asm/kvm_book3s_asm.h> /* The physical memory is layed out such that the secondary processor * spin code sits at 0x0000...0x00ff. On server, the vectors follow @@ -169,7 +169,7 @@ exception_marker: /* KVM trampoline code needs to be close to the interrupt handlers */ #ifdef CONFIG_KVM_BOOK3S_64_HANDLER -#include "../kvm/book3s_64_rmhandlers.S" +#include "../kvm/book3s_rmhandlers.S" #endif _GLOBAL(generic_secondary_thread_init) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index edd4a57fd29e..4faeba247854 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -94,204 +94,10 @@ _ENTRY(_start); */ _ENTRY(__early_start) -/* 1. Find the index of the entry we're executing in */ - bl invstr /* Find our address */ -invstr: mflr r6 /* Make it accessible */ - mfmsr r7 - rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ - mfspr r7, SPRN_PID0 - slwi r7,r7,16 - or r7,r7,r4 - mtspr SPRN_MAS6,r7 - tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ - mfspr r7,SPRN_MAS1 - andis. r7,r7,MAS1_VALID@h - bne match_TLB - - mfspr r7,SPRN_MMUCFG - rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ - cmpwi r7,3 - bne match_TLB /* skip if NPIDS != 3 */ - - mfspr r7,SPRN_PID1 - slwi r7,r7,16 - or r7,r7,r4 - mtspr SPRN_MAS6,r7 - tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ - mfspr r7,SPRN_MAS1 - andis. r7,r7,MAS1_VALID@h - bne match_TLB - mfspr r7, SPRN_PID2 - slwi r7,r7,16 - or r7,r7,r4 - mtspr SPRN_MAS6,r7 - tlbsx 0,r6 /* Fall through, we had to match */ - -match_TLB: - mfspr r7,SPRN_MAS0 - rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ - - mfspr r7,SPRN_MAS1 /* Insure IPROT set */ - oris r7,r7,MAS1_IPROT@h - mtspr SPRN_MAS1,r7 - tlbwe - -/* 2. Invalidate all entries except the entry we're executing in */ - mfspr r9,SPRN_TLB1CFG - andi. r9,r9,0xfff - li r6,0 /* Set Entry counter to 0 */ -1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ - rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ - mtspr SPRN_MAS0,r7 - tlbre - mfspr r7,SPRN_MAS1 - rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ - cmpw r3,r6 - beq skpinv /* Dont update the current execution TLB */ - mtspr SPRN_MAS1,r7 - tlbwe - isync -skpinv: addi r6,r6,1 /* Increment */ - cmpw r6,r9 /* Are we done? */ - bne 1b /* If not, repeat */ - - /* Invalidate TLB0 */ - li r6,0x04 - tlbivax 0,r6 - TLBSYNC - /* Invalidate TLB1 */ - li r6,0x0c - tlbivax 0,r6 - TLBSYNC - -/* 3. Setup a temp mapping and jump to it */ - andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ - addi r5, r5, 0x1 - lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ - rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ - mtspr SPRN_MAS0,r7 - tlbre - - /* grab and fixup the RPN */ - mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ - rlwinm r6,r6,25,27,31 - li r8,-1 - addi r6,r6,10 - slw r6,r8,r6 /* convert to mask */ - - bl 1f /* Find our address */ -1: mflr r7 - - mfspr r8,SPRN_MAS3 -#ifdef CONFIG_PHYS_64BIT - mfspr r23,SPRN_MAS7 -#endif - and r8,r6,r8 - subfic r9,r6,-4096 - and r9,r9,r7 - - or r25,r8,r9 - ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR) - - /* Just modify the entry ID and EPN for the temp mapping */ - lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ - rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ - mtspr SPRN_MAS0,r7 - xori r6,r4,1 /* Setup TMP mapping in the other Address space */ - slwi r6,r6,12 - oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h - ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l - mtspr SPRN_MAS1,r6 - mfspr r6,SPRN_MAS2 - li r7,0 /* temp EPN = 0 */ - rlwimi r7,r6,0,20,31 - mtspr SPRN_MAS2,r7 - mtspr SPRN_MAS3,r8 - tlbwe - - xori r6,r4,1 - slwi r6,r6,5 /* setup new context with other address space */ - bl 1f /* Find our address */ -1: mflr r9 - rlwimi r7,r9,0,20,31 - addi r7,r7,(2f - 1b) - mtspr SPRN_SRR0,r7 - mtspr SPRN_SRR1,r6 - rfi -2: -/* 4. Clear out PIDs & Search info */ - li r6,0 - mtspr SPRN_MAS6,r6 - mtspr SPRN_PID0,r6 - - mfspr r7,SPRN_MMUCFG - rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */ - cmpwi r7,3 - bne 2f /* skip if NPIDS != 3 */ - mtspr SPRN_PID1,r6 - mtspr SPRN_PID2,r6 - -/* 5. Invalidate mapping we started in */ -2: - lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ - rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ - mtspr SPRN_MAS0,r7 - tlbre - mfspr r6,SPRN_MAS1 - rlwinm r6,r6,0,2,0 /* clear IPROT */ - mtspr SPRN_MAS1,r6 - tlbwe - /* Invalidate TLB1 */ - li r9,0x0c - tlbivax 0,r9 - TLBSYNC - -/* The mapping only needs to be cache-coherent on SMP */ -#ifdef CONFIG_SMP -#define M_IF_SMP MAS2_M -#else -#define M_IF_SMP 0 -#endif - -/* 6. Setup KERNELBASE mapping in TLB1[0] */ - lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ - mtspr SPRN_MAS0,r6 - lis r6,(MAS1_VALID|MAS1_IPROT)@h - ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l - mtspr SPRN_MAS1,r6 - lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h - ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l - mtspr SPRN_MAS2,r6 - mtspr SPRN_MAS3,r8 - tlbwe - -/* 7. Jump to KERNELBASE mapping */ - lis r6,(KERNELBASE & ~0xfff)@h - ori r6,r6,(KERNELBASE & ~0xfff)@l - lis r7,MSR_KERNEL@h - ori r7,r7,MSR_KERNEL@l - bl 1f /* Find our address */ -1: mflr r9 - rlwimi r6,r9,0,20,31 - addi r6,r6,(2f - 1b) - mtspr SPRN_SRR0,r6 - mtspr SPRN_SRR1,r7 - rfi /* start execution out of TLB1[0] entry */ - -/* 8. Clear out the temp mapping */ -2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ - rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ - mtspr SPRN_MAS0,r7 - tlbre - mfspr r8,SPRN_MAS1 - rlwinm r8,r8,0,2,0 /* clear IPROT */ - mtspr SPRN_MAS1,r8 - tlbwe - /* Invalidate TLB1 */ - li r9,0x0c - tlbivax 0,r9 - TLBSYNC +#define ENTRY_MAPPING_BOOT_SETUP +#include "fsl_booke_entry_mapping.S" +#undef ENTRY_MAPPING_BOOT_SETUP /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index 71cf280da184..21266abfbda6 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -140,14 +140,14 @@ static struct dma_map_ops ibmebus_dma_ops = { static int ibmebus_match_path(struct device *dev, void *data) { - struct device_node *dn = to_of_device(dev)->node; + struct device_node *dn = to_of_device(dev)->dev.of_node; return (dn->full_name && (strcasecmp((char *)data, dn->full_name) == 0)); } static int ibmebus_match_node(struct device *dev, void *data) { - return to_of_device(dev)->node == data; + return to_of_device(dev)->dev.of_node == data; } static int ibmebus_create_device(struct device_node *dn) @@ -202,7 +202,7 @@ static int ibmebus_create_devices(const struct of_device_id *matches) int ibmebus_register_driver(struct of_platform_driver *drv) { /* If the driver uses devices that ibmebus doesn't know, add them */ - ibmebus_create_devices(drv->match_table); + ibmebus_create_devices(drv->driver.of_match_table); return of_register_driver(drv, &ibmebus_bus_type); } diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c index c533525ca56a..bc47352deb1f 100644 --- a/arch/powerpc/kernel/kprobes.c +++ b/arch/powerpc/kernel/kprobes.c @@ -378,17 +378,6 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, * single-stepped a copy of the instruction. The address of this * copy is p->ainsn.insn. */ -static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs) -{ - int ret; - unsigned int insn = *p->ainsn.insn; - - regs->nip = (unsigned long)p->addr; - ret = emulate_step(regs, insn); - if (ret == 0) - regs->nip = (unsigned long)p->addr + 4; -} - static int __kprobes post_kprobe_handler(struct pt_regs *regs) { struct kprobe *cur = kprobe_running(); @@ -406,7 +395,8 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs) cur->post_handler(cur, regs, 0); } - resume_execution(cur, regs); + /* Adjust nip to after the single-stepped instruction */ + regs->nip = (unsigned long)cur->addr + 4; regs->msr |= kcb->kprobe_saved_msr; /*Restore back the original saved kprobes variables and continue. */ diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 8043d1b73cf0..dc66d52dcff5 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -711,6 +711,22 @@ relocate_new_kernel: /* r4 = reboot_code_buffer */ /* r5 = start_address */ +#ifdef CONFIG_FSL_BOOKE + + mr r29, r3 + mr r30, r4 + mr r31, r5 + +#define ENTRY_MAPPING_KEXEC_SETUP +#include "fsl_booke_entry_mapping.S" +#undef ENTRY_MAPPING_KEXEC_SETUP + + mr r3, r29 + mr r4, r30 + mr r5, r31 + + li r0, 0 +#else li r0, 0 /* @@ -727,6 +743,7 @@ relocate_new_kernel: rfi 1: +#endif /* from this point address translation is turned off */ /* and interrupts are disabled */ diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c index a359cb08e900..df78e0236a02 100644 --- a/arch/powerpc/kernel/of_device.c +++ b/arch/powerpc/kernel/of_device.c @@ -13,7 +13,7 @@ static void of_device_make_bus_id(struct of_device *dev) { static atomic_t bus_no_reg_magic; - struct device_node *node = dev->node; + struct device_node *node = dev->dev.of_node; const u32 *reg; u64 addr; int magic; @@ -69,11 +69,10 @@ struct of_device *of_device_alloc(struct device_node *np, if (!dev) return NULL; - dev->node = of_node_get(np); - dev->dev.dma_mask = &dev->dma_mask; + dev->dev.of_node = of_node_get(np); + dev->dev.dma_mask = &dev->archdata.dma_mask; dev->dev.parent = parent; dev->dev.release = of_release_dev; - dev->dev.archdata.of_node = np; if (bus_id) dev_set_name(&dev->dev, "%s", bus_id); @@ -95,17 +94,17 @@ int of_device_uevent(struct device *dev, struct kobj_uevent_env *env) ofdev = to_of_device(dev); - if (add_uevent_var(env, "OF_NAME=%s", ofdev->node->name)) + if (add_uevent_var(env, "OF_NAME=%s", ofdev->dev.of_node->name)) return -ENOMEM; - if (add_uevent_var(env, "OF_TYPE=%s", ofdev->node->type)) + if (add_uevent_var(env, "OF_TYPE=%s", ofdev->dev.of_node->type)) return -ENOMEM; /* Since the compatible field can contain pretty much anything * it's not really legal to split it out with commas. We split it * up using a number of environment variables instead. */ - compat = of_get_property(ofdev->node, "compatible", &cplen); + compat = of_get_property(ofdev->dev.of_node, "compatible", &cplen); while (compat && *compat && cplen > 0) { if (add_uevent_var(env, "OF_COMPATIBLE_%d=%s", seen, compat)) return -ENOMEM; diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c index 6c1dfc3ff8bc..487a98851ba6 100644 --- a/arch/powerpc/kernel/of_platform.c +++ b/arch/powerpc/kernel/of_platform.c @@ -74,7 +74,7 @@ struct of_device* of_platform_device_create(struct device_node *np, if (!dev) return NULL; - dev->dma_mask = 0xffffffffUL; + dev->archdata.dma_mask = 0xffffffffUL; dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); dev->dev.bus = &of_platform_bus_type; @@ -195,7 +195,7 @@ EXPORT_SYMBOL(of_platform_bus_probe); static int of_dev_node_match(struct device *dev, void *data) { - return to_of_device(dev)->node == data; + return to_of_device(dev)->dev.of_node == data; } struct of_device *of_find_device_by_node(struct device_node *np) @@ -213,7 +213,7 @@ EXPORT_SYMBOL(of_find_device_by_node); static int of_dev_phandle_match(struct device *dev, void *data) { phandle *ph = data; - return to_of_device(dev)->node->phandle == *ph; + return to_of_device(dev)->dev.of_node->phandle == *ph; } struct of_device *of_find_device_by_phandle(phandle ph) @@ -246,10 +246,10 @@ static int __devinit of_pci_phb_probe(struct of_device *dev, if (ppc_md.pci_setup_phb == NULL) return -ENODEV; - printk(KERN_INFO "Setting up PCI bus %s\n", dev->node->full_name); + pr_info("Setting up PCI bus %s\n", dev->dev.of_node->full_name); /* Alloc and setup PHB data structure */ - phb = pcibios_alloc_controller(dev->node); + phb = pcibios_alloc_controller(dev->dev.of_node); if (!phb) return -ENODEV; @@ -263,19 +263,19 @@ static int __devinit of_pci_phb_probe(struct of_device *dev, } /* Process "ranges" property */ - pci_process_bridge_OF_ranges(phb, dev->node, 0); + pci_process_bridge_OF_ranges(phb, dev->dev.of_node, 0); /* Init pci_dn data structures */ pci_devs_phb_init_dynamic(phb); /* Register devices with EEH */ #ifdef CONFIG_EEH - if (dev->node->child) - eeh_add_device_tree_early(dev->node); + if (dev->dev.of_node->child) + eeh_add_device_tree_early(dev->dev.of_node); #endif /* CONFIG_EEH */ /* Scan the bus */ - pcibios_scan_phb(phb, dev->node); + pcibios_scan_phb(phb, dev->dev.of_node); if (phb->bus == NULL) return -ENXIO; @@ -306,10 +306,11 @@ static struct of_device_id of_pci_phb_ids[] = { }; static struct of_platform_driver of_pci_phb_driver = { - .match_table = of_pci_phb_ids, .probe = of_pci_phb_probe, .driver = { .name = "of-pci", + .owner = THIS_MODULE, + .of_match_table = of_pci_phb_ids, }, }; diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 0c0567e58409..5b38f6ae2b29 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -1097,8 +1097,8 @@ void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) if (dev->is_added) continue; - /* Setup OF node pointer in archdata */ - sd->of_node = pci_device_to_OF_node(dev); + /* Setup OF node pointer in the device */ + dev->dev.of_node = pci_device_to_OF_node(dev); /* Fixup NUMA node as it may not be setup yet by the generic * code and is needed by the DMA init @@ -1309,6 +1309,7 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus) printk(KERN_WARNING "PCI: Cannot allocate resource region " "%d of PCI bridge %d, will remap\n", i, bus->number); clear_resource: + res->start = res->end = 0; res->flags = 0; } diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c index ab3e392ac63c..3b4dcc82a4c1 100644 --- a/arch/powerpc/kernel/ppc_ksyms.c +++ b/arch/powerpc/kernel/ppc_ksyms.c @@ -101,6 +101,10 @@ EXPORT_SYMBOL(pci_dram_offset); EXPORT_SYMBOL(start_thread); EXPORT_SYMBOL(kernel_thread); +#ifdef CONFIG_PPC_FPU +EXPORT_SYMBOL_GPL(cvt_df); +EXPORT_SYMBOL_GPL(cvt_fd); +#endif EXPORT_SYMBOL(giveup_fpu); #ifdef CONFIG_ALTIVEC EXPORT_SYMBOL(giveup_altivec); diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S new file mode 100644 index 000000000000..11a39307dd71 --- /dev/null +++ b/arch/powerpc/kernel/swsusp_booke.S @@ -0,0 +1,193 @@ +/* + * Based on swsusp_32.S, modified for FSL BookE by + * Anton Vorontsov <avorontsov@ru.mvista.com> + * Copyright (c) 2009-2010 MontaVista Software, LLC. + */ + +#include <linux/threads.h> +#include <asm/processor.h> +#include <asm/page.h> +#include <asm/cputable.h> +#include <asm/thread_info.h> +#include <asm/ppc_asm.h> +#include <asm/asm-offsets.h> +#include <asm/mmu.h> + +/* + * Structure for storing CPU registers on the save area. + */ +#define SL_SP 0 +#define SL_PC 4 +#define SL_MSR 8 +#define SL_TCR 0xc +#define SL_SPRG0 0x10 +#define SL_SPRG1 0x14 +#define SL_SPRG2 0x18 +#define SL_SPRG3 0x1c +#define SL_SPRG4 0x20 +#define SL_SPRG5 0x24 +#define SL_SPRG6 0x28 +#define SL_SPRG7 0x2c +#define SL_TBU 0x30 +#define SL_TBL 0x34 +#define SL_R2 0x38 +#define SL_CR 0x3c +#define SL_LR 0x40 +#define SL_R12 0x44 /* r12 to r31 */ +#define SL_SIZE (SL_R12 + 80) + + .section .data + .align 5 + +_GLOBAL(swsusp_save_area) + .space SL_SIZE + + + .section .text + .align 5 + +_GLOBAL(swsusp_arch_suspend) + lis r11,swsusp_save_area@h + ori r11,r11,swsusp_save_area@l + + mflr r0 + stw r0,SL_LR(r11) + mfcr r0 + stw r0,SL_CR(r11) + stw r1,SL_SP(r11) + stw r2,SL_R2(r11) + stmw r12,SL_R12(r11) + + /* Save MSR & TCR */ + mfmsr r4 + stw r4,SL_MSR(r11) + mfspr r4,SPRN_TCR + stw r4,SL_TCR(r11) + + /* Get a stable timebase and save it */ +1: mfspr r4,SPRN_TBRU + stw r4,SL_TBU(r11) + mfspr r5,SPRN_TBRL + stw r5,SL_TBL(r11) + mfspr r3,SPRN_TBRU + cmpw r3,r4 + bne 1b + + /* Save SPRGs */ + mfsprg r4,0 + stw r4,SL_SPRG0(r11) + mfsprg r4,1 + stw r4,SL_SPRG1(r11) + mfsprg r4,2 + stw r4,SL_SPRG2(r11) + mfsprg r4,3 + stw r4,SL_SPRG3(r11) + mfsprg r4,4 + stw r4,SL_SPRG4(r11) + mfsprg r4,5 + stw r4,SL_SPRG5(r11) + mfsprg r4,6 + stw r4,SL_SPRG6(r11) + mfsprg r4,7 + stw r4,SL_SPRG7(r11) + + /* Call the low level suspend stuff (we should probably have made + * a stackframe... + */ + bl swsusp_save + + /* Restore LR from the save area */ + lis r11,swsusp_save_area@h + ori r11,r11,swsusp_save_area@l + lwz r0,SL_LR(r11) + mtlr r0 + + blr + +_GLOBAL(swsusp_arch_resume) + sync + + /* Load ptr the list of pages to copy in r3 */ + lis r11,(restore_pblist)@h + ori r11,r11,restore_pblist@l + lwz r3,0(r11) + + /* Copy the pages. This is a very basic implementation, to + * be replaced by something more cache efficient */ +1: + li r0,256 + mtctr r0 + lwz r5,pbe_address(r3) /* source */ + lwz r6,pbe_orig_address(r3) /* destination */ +2: + lwz r8,0(r5) + lwz r9,4(r5) + lwz r10,8(r5) + lwz r11,12(r5) + addi r5,r5,16 + stw r8,0(r6) + stw r9,4(r6) + stw r10,8(r6) + stw r11,12(r6) + addi r6,r6,16 + bdnz 2b + lwz r3,pbe_next(r3) + cmpwi 0,r3,0 + bne 1b + + bl flush_dcache_L1 + bl flush_instruction_cache + + lis r11,swsusp_save_area@h + ori r11,r11,swsusp_save_area@l + + lwz r4,SL_SPRG0(r11) + mtsprg 0,r4 + lwz r4,SL_SPRG1(r11) + mtsprg 1,r4 + lwz r4,SL_SPRG2(r11) + mtsprg 2,r4 + lwz r4,SL_SPRG3(r11) + mtsprg 3,r4 + lwz r4,SL_SPRG4(r11) + mtsprg 4,r4 + lwz r4,SL_SPRG5(r11) + mtsprg 5,r4 + lwz r4,SL_SPRG6(r11) + mtsprg 6,r4 + lwz r4,SL_SPRG7(r11) + mtsprg 7,r4 + + /* restore the MSR */ + lwz r3,SL_MSR(r11) + mtmsr r3 + + /* Restore TB */ + li r3,0 + mtspr SPRN_TBWL,r3 + lwz r3,SL_TBU(r11) + lwz r4,SL_TBL(r11) + mtspr SPRN_TBWU,r3 + mtspr SPRN_TBWL,r4 + + /* Restore TCR and clear any pending bits in TSR. */ + lwz r4,SL_TCR(r11) + mtspr SPRN_TCR,r4 + lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h + mtspr SPRN_TSR,r4 + + /* Kick decrementer */ + li r0,1 + mtdec r0 + + /* Restore the callee-saved registers and return */ + lwz r0,SL_CR(r11) + mtcr r0 + lwz r2,SL_R2(r11) + lmw r12,SL_R12(r11) + lwz r1,SL_SP(r11) + lwz r0,SL_LR(r11) + mtlr r0 + + li r3,0 + blr diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 3031fc712ad0..25fc33984c2b 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -1,5 +1,6 @@ /* * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -305,7 +306,7 @@ static inline int check_io_access(struct pt_regs *regs) #ifndef CONFIG_FSL_BOOKE #define get_mc_reason(regs) ((regs)->dsisr) #else -#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) +#define get_mc_reason(regs) (mfspr(SPRN_MCSR)) #endif #define REASON_FP ESR_FP #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) @@ -421,6 +422,91 @@ int machine_check_47x(struct pt_regs *regs) return 0; } #elif defined(CONFIG_E500) +int machine_check_e500mc(struct pt_regs *regs) +{ + unsigned long mcsr = mfspr(SPRN_MCSR); + unsigned long reason = mcsr; + int recoverable = 1; + + printk("Machine check in kernel mode.\n"); + printk("Caused by (from MCSR=%lx): ", reason); + + if (reason & MCSR_MCP) + printk("Machine Check Signal\n"); + + if (reason & MCSR_ICPERR) { + printk("Instruction Cache Parity Error\n"); + + /* + * This is recoverable by invalidating the i-cache. + */ + mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); + while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) + ; + + /* + * This will generally be accompanied by an instruction + * fetch error report -- only treat MCSR_IF as fatal + * if it wasn't due to an L1 parity error. + */ + reason &= ~MCSR_IF; + } + + if (reason & MCSR_DCPERR_MC) { + printk("Data Cache Parity Error\n"); + recoverable = 0; + } + + if (reason & MCSR_L2MMU_MHIT) { + printk("Hit on multiple TLB entries\n"); + recoverable = 0; + } + + if (reason & MCSR_NMI) + printk("Non-maskable interrupt\n"); + + if (reason & MCSR_IF) { + printk("Instruction Fetch Error Report\n"); + recoverable = 0; + } + + if (reason & MCSR_LD) { + printk("Load Error Report\n"); + recoverable = 0; + } + + if (reason & MCSR_ST) { + printk("Store Error Report\n"); + recoverable = 0; + } + + if (reason & MCSR_LDG) { + printk("Guarded Load Error Report\n"); + recoverable = 0; + } + + if (reason & MCSR_TLBSYNC) + printk("Simultaneous tlbsync operations\n"); + + if (reason & MCSR_BSL2_ERR) { + printk("Level 2 Cache Error\n"); + recoverable = 0; + } + + if (reason & MCSR_MAV) { + u64 addr; + + addr = mfspr(SPRN_MCAR); + addr |= (u64)mfspr(SPRN_MCARU) << 32; + + printk("Machine Check %s Address: %#llx\n", + reason & MCSR_MEA ? "Effective" : "Physical", addr); + } + + mtspr(SPRN_MCSR, mcsr); + return mfspr(SPRN_MCSR) == 0 && recoverable; +} + int machine_check_e500(struct pt_regs *regs) { unsigned long reason = get_mc_reason(regs); diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index 9ce7b62dc3a4..00b9436f7652 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -707,7 +707,7 @@ static int vio_cmo_bus_probe(struct vio_dev *viodev) * Check to see that device has a DMA window and configure * entitlement for the device. */ - if (of_get_property(viodev->dev.archdata.of_node, + if (of_get_property(viodev->dev.of_node, "ibm,my-dma-window", NULL)) { /* Check that the driver is CMO enabled and get desired DMA */ if (!viodrv->get_desired_dma) { @@ -1054,7 +1054,7 @@ static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev) if (firmware_has_feature(FW_FEATURE_ISERIES)) return vio_build_iommu_table_iseries(dev); - dma_window = of_get_property(dev->dev.archdata.of_node, + dma_window = of_get_property(dev->dev.of_node, "ibm,my-dma-window", NULL); if (!dma_window) return NULL; @@ -1063,7 +1063,7 @@ static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev) if (tbl == NULL) return NULL; - of_parse_dma_window(dev->dev.archdata.of_node, dma_window, + of_parse_dma_window(dev->dev.of_node, dma_window, &tbl->it_index, &offset, &size); /* TCE table size - measured in tce entries */ @@ -1091,7 +1091,7 @@ static const struct vio_device_id *vio_match_device( { while (ids->type[0] != '\0') { if ((strncmp(dev->type, ids->type, strlen(ids->type)) == 0) && - of_device_is_compatible(dev->dev.archdata.of_node, + of_device_is_compatible(dev->dev.of_node, ids->compat)) return ids; ids++; @@ -1184,7 +1184,7 @@ EXPORT_SYMBOL(vio_unregister_driver); static void __devinit vio_dev_release(struct device *dev) { /* XXX should free TCE table */ - of_node_put(dev->archdata.of_node); + of_node_put(dev->of_node); kfree(to_vio_dev(dev)); } @@ -1235,7 +1235,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node) if (unit_address != NULL) viodev->unit_address = *unit_address; } - viodev->dev.archdata.of_node = of_node_get(of_node); + viodev->dev.of_node = of_node_get(of_node); if (firmware_has_feature(FW_FEATURE_CMO)) vio_cmo_set_dma_ops(viodev); @@ -1320,7 +1320,7 @@ static ssize_t name_show(struct device *dev, static ssize_t devspec_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct device_node *of_node = dev->archdata.of_node; + struct device_node *of_node = dev->of_node; return sprintf(buf, "%s\n", of_node ? of_node->full_name : "none"); } @@ -1332,7 +1332,7 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, struct device_node *dn; const char *cp; - dn = dev->archdata.of_node; + dn = dev->of_node; if (!dn) return -ENODEV; cp = of_get_property(dn, "compatible", NULL); @@ -1370,7 +1370,7 @@ static int vio_hotplug(struct device *dev, struct kobj_uevent_env *env) struct device_node *dn; const char *cp; - dn = dev->archdata.of_node; + dn = dev->of_node; if (!dn) return -ENODEV; cp = of_get_property(dn, "compatible", NULL); @@ -1402,7 +1402,7 @@ static struct bus_type vio_bus_type = { */ const void *vio_get_attribute(struct vio_dev *vdev, char *which, int *length) { - return of_get_property(vdev->dev.archdata.of_node, which, length); + return of_get_property(vdev->dev.of_node, which, length); } EXPORT_SYMBOL(vio_get_attribute); diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index dcd01c82e701..8a0deefac08d 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -223,19 +223,17 @@ SECTIONS #endif /* The initial task and kernel stack */ - .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) { - INIT_TASK_DATA(THREAD_SIZE) - } + INIT_TASK_DATA_SECTION(THREAD_SIZE) - .data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) { + .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) { PAGE_ALIGNED_DATA(PAGE_SIZE) } - .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) { + .data..cacheline_aligned : AT(ADDR(.data..cacheline_aligned) - LOAD_OFFSET) { CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) } - .data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) { + .data..read_mostly : AT(ADDR(.data..read_mostly) - LOAD_OFFSET) { READ_MOSTLY_DATA(L1_CACHE_BYTES) } diff --git a/arch/powerpc/kvm/44x.c b/arch/powerpc/kvm/44x.c index 689a57c2ac80..73c0a3f64ed1 100644 --- a/arch/powerpc/kvm/44x.c +++ b/arch/powerpc/kvm/44x.c @@ -147,7 +147,7 @@ static int __init kvmppc_44x_init(void) if (r) return r; - return kvm_init(NULL, sizeof(struct kvmppc_vcpu_44x), THIS_MODULE); + return kvm_init(NULL, sizeof(struct kvmppc_vcpu_44x), 0, THIS_MODULE); } static void __exit kvmppc_44x_exit(void) diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig index 60624cc9f4d4..b7baff78f90c 100644 --- a/arch/powerpc/kvm/Kconfig +++ b/arch/powerpc/kvm/Kconfig @@ -22,12 +22,34 @@ config KVM select ANON_INODES select KVM_MMIO +config KVM_BOOK3S_HANDLER + bool + +config KVM_BOOK3S_32_HANDLER + bool + select KVM_BOOK3S_HANDLER + config KVM_BOOK3S_64_HANDLER bool + select KVM_BOOK3S_HANDLER + +config KVM_BOOK3S_32 + tristate "KVM support for PowerPC book3s_32 processors" + depends on EXPERIMENTAL && PPC_BOOK3S_32 && !SMP && !PTE_64BIT + select KVM + select KVM_BOOK3S_32_HANDLER + ---help--- + Support running unmodified book3s_32 guest kernels + in virtual machines on book3s_32 host processors. + + This module provides access to the hardware capabilities through + a character device node named /dev/kvm. + + If unsure, say N. config KVM_BOOK3S_64 tristate "KVM support for PowerPC book3s_64 processors" - depends on EXPERIMENTAL && PPC64 + depends on EXPERIMENTAL && PPC_BOOK3S_64 select KVM select KVM_BOOK3S_64_HANDLER ---help--- diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile index 56484d652377..ff436066bf77 100644 --- a/arch/powerpc/kvm/Makefile +++ b/arch/powerpc/kvm/Makefile @@ -14,7 +14,7 @@ CFLAGS_emulate.o := -I. common-objs-y += powerpc.o emulate.o obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o -obj-$(CONFIG_KVM_BOOK3S_64_HANDLER) += book3s_64_exports.o +obj-$(CONFIG_KVM_BOOK3S_HANDLER) += book3s_exports.o AFLAGS_booke_interrupts.o := -I$(obj) @@ -40,17 +40,31 @@ kvm-objs-$(CONFIG_KVM_E500) := $(kvm-e500-objs) kvm-book3s_64-objs := \ $(common-objs-y) \ + fpu.o \ + book3s_paired_singles.o \ book3s.o \ - book3s_64_emulate.o \ - book3s_64_interrupts.o \ + book3s_emulate.o \ + book3s_interrupts.o \ book3s_64_mmu_host.o \ book3s_64_mmu.o \ book3s_32_mmu.o kvm-objs-$(CONFIG_KVM_BOOK3S_64) := $(kvm-book3s_64-objs) +kvm-book3s_32-objs := \ + $(common-objs-y) \ + fpu.o \ + book3s_paired_singles.o \ + book3s.o \ + book3s_emulate.o \ + book3s_interrupts.o \ + book3s_32_mmu_host.o \ + book3s_32_mmu.o +kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs) + kvm-objs := $(kvm-objs-m) $(kvm-objs-y) obj-$(CONFIG_KVM_440) += kvm.o obj-$(CONFIG_KVM_E500) += kvm.o obj-$(CONFIG_KVM_BOOK3S_64) += kvm.o +obj-$(CONFIG_KVM_BOOK3S_32) += kvm.o diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c index 604af29b71ed..b998abf1a63d 100644 --- a/arch/powerpc/kvm/book3s.c +++ b/arch/powerpc/kvm/book3s.c @@ -16,6 +16,7 @@ #include <linux/kvm_host.h> #include <linux/err.h> +#include <linux/slab.h> #include <asm/reg.h> #include <asm/cputable.h> @@ -29,6 +30,7 @@ #include <linux/gfp.h> #include <linux/sched.h> #include <linux/vmalloc.h> +#include <linux/highmem.h> #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU @@ -36,7 +38,15 @@ /* #define EXIT_DEBUG_SIMPLE */ /* #define DEBUG_EXT */ -static void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr); +static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, + ulong msr); + +/* Some compatibility defines */ +#ifdef CONFIG_PPC_BOOK3S_32 +#define MSR_USER32 MSR_USER +#define MSR_USER64 MSR_USER +#define HW_PAGE_SIZE PAGE_SIZE +#endif struct kvm_stats_debugfs_item debugfs_entries[] = { { "exits", VCPU_STAT(sum_exits) }, @@ -69,18 +79,26 @@ void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu) void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - memcpy(get_paca()->kvm_slb, to_book3s(vcpu)->slb_shadow, sizeof(get_paca()->kvm_slb)); - memcpy(&get_paca()->shadow_vcpu, &to_book3s(vcpu)->shadow_vcpu, +#ifdef CONFIG_PPC_BOOK3S_64 + memcpy(to_svcpu(vcpu)->slb, to_book3s(vcpu)->slb_shadow, sizeof(to_svcpu(vcpu)->slb)); + memcpy(&get_paca()->shadow_vcpu, to_book3s(vcpu)->shadow_vcpu, sizeof(get_paca()->shadow_vcpu)); - get_paca()->kvm_slb_max = to_book3s(vcpu)->slb_shadow_max; + to_svcpu(vcpu)->slb_max = to_book3s(vcpu)->slb_shadow_max; +#endif + +#ifdef CONFIG_PPC_BOOK3S_32 + current->thread.kvm_shadow_vcpu = to_book3s(vcpu)->shadow_vcpu; +#endif } void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) { - memcpy(to_book3s(vcpu)->slb_shadow, get_paca()->kvm_slb, sizeof(get_paca()->kvm_slb)); - memcpy(&to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu, +#ifdef CONFIG_PPC_BOOK3S_64 + memcpy(to_book3s(vcpu)->slb_shadow, to_svcpu(vcpu)->slb, sizeof(to_svcpu(vcpu)->slb)); + memcpy(to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu, sizeof(get_paca()->shadow_vcpu)); - to_book3s(vcpu)->slb_shadow_max = get_paca()->kvm_slb_max; + to_book3s(vcpu)->slb_shadow_max = to_svcpu(vcpu)->slb_max; +#endif kvmppc_giveup_ext(vcpu, MSR_FP); kvmppc_giveup_ext(vcpu, MSR_VEC); @@ -131,18 +149,22 @@ void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr) } } - if (((vcpu->arch.msr & (MSR_IR|MSR_DR)) != (old_msr & (MSR_IR|MSR_DR))) || - (vcpu->arch.msr & MSR_PR) != (old_msr & MSR_PR)) { + if ((vcpu->arch.msr & (MSR_PR|MSR_IR|MSR_DR)) != + (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { kvmppc_mmu_flush_segments(vcpu); - kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc); + kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); } + + /* Preload FPU if it's enabled */ + if (vcpu->arch.msr & MSR_FP) + kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); } void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags) { - vcpu->arch.srr0 = vcpu->arch.pc; + vcpu->arch.srr0 = kvmppc_get_pc(vcpu); vcpu->arch.srr1 = vcpu->arch.msr | flags; - vcpu->arch.pc = to_book3s(vcpu)->hior + vec; + kvmppc_set_pc(vcpu, to_book3s(vcpu)->hior + vec); vcpu->arch.mmu.reset_msr(vcpu); } @@ -218,6 +240,12 @@ void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL); } +void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, + struct kvm_interrupt *irq) +{ + kvmppc_book3s_dequeue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL); +} + int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) { int deliver = 1; @@ -302,7 +330,7 @@ void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu) printk(KERN_EMERG "KVM: Check pending: %lx\n", vcpu->arch.pending_exceptions); #endif priority = __ffs(*pending); - while (priority <= (sizeof(unsigned int) * 8)) { + while (priority < BOOK3S_IRQPRIO_MAX) { if (kvmppc_book3s_irqprio_deliver(vcpu, priority) && (priority != BOOK3S_IRQPRIO_DECREMENTER)) { /* DEC interrupts get cleared by mtdec */ @@ -318,13 +346,18 @@ void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu) void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr) { + u32 host_pvr; + vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; vcpu->arch.pvr = pvr; +#ifdef CONFIG_PPC_BOOK3S_64 if ((pvr >= 0x330000) && (pvr < 0x70330000)) { kvmppc_mmu_book3s_64_init(vcpu); to_book3s(vcpu)->hior = 0xfff00000; to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; - } else { + } else +#endif + { kvmppc_mmu_book3s_32_init(vcpu); to_book3s(vcpu)->hior = 0; to_book3s(vcpu)->msr_mask = 0xffffffffULL; @@ -337,6 +370,32 @@ void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr) !strcmp(cur_cpu_spec->platform, "ppc970")) vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; + /* Cell performs badly if MSR_FEx are set. So let's hope nobody + really needs them in a VM on Cell and force disable them. */ + if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) + to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); + +#ifdef CONFIG_PPC_BOOK3S_32 + /* 32 bit Book3S always has 32 byte dcbz */ + vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; +#endif + + /* On some CPUs we can execute paired single operations natively */ + asm ( "mfpvr %0" : "=r"(host_pvr)); + switch (host_pvr) { + case 0x00080200: /* lonestar 2.0 */ + case 0x00088202: /* lonestar 2.2 */ + case 0x70000100: /* gekko 1.0 */ + case 0x00080100: /* gekko 2.0 */ + case 0x00083203: /* gekko 2.3a */ + case 0x00083213: /* gekko 2.3b */ + case 0x00083204: /* gekko 2.4 */ + case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ + case 0x00087200: /* broadway */ + vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; + /* Enable HID2.PSE - in case we need it later */ + mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); + } } /* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To @@ -350,34 +409,29 @@ void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr) */ static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) { - bool touched = false; - hva_t hpage; + struct page *hpage; + u64 hpage_offset; u32 *page; int i; - hpage = gfn_to_hva(vcpu->kvm, pte->raddr >> PAGE_SHIFT); - if (kvm_is_error_hva(hpage)) + hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT); + if (is_error_page(hpage)) return; - hpage |= pte->raddr & ~PAGE_MASK; - hpage &= ~0xFFFULL; - - page = vmalloc(HW_PAGE_SIZE); - - if (copy_from_user(page, (void __user *)hpage, HW_PAGE_SIZE)) - goto out; + hpage_offset = pte->raddr & ~PAGE_MASK; + hpage_offset &= ~0xFFFULL; + hpage_offset /= 4; - for (i=0; i < HW_PAGE_SIZE / 4; i++) - if ((page[i] & 0xff0007ff) == INS_DCBZ) { - page[i] &= 0xfffffff7; // reserved instruction, so we trap - touched = true; - } + get_page(hpage); + page = kmap_atomic(hpage, KM_USER0); - if (touched) - copy_to_user((void __user *)hpage, page, HW_PAGE_SIZE); + /* patch dcbz into reserved instruction, so we trap */ + for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) + if ((page[i] & 0xff0007ff) == INS_DCBZ) + page[i] &= 0xfffffff7; -out: - vfree(page); + kunmap_atomic(page, KM_USER0); + put_page(hpage); } static int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, bool data, @@ -391,15 +445,7 @@ static int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, bool data, } else { pte->eaddr = eaddr; pte->raddr = eaddr & 0xffffffff; - pte->vpage = eaddr >> 12; - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - pte->vpage |= VSID_REAL; - case MSR_DR: - pte->vpage |= VSID_REAL_DR; - case MSR_IR: - pte->vpage |= VSID_REAL_IR; - } + pte->vpage = VSID_REAL | eaddr >> 12; pte->may_read = true; pte->may_write = true; pte->may_execute = true; @@ -434,55 +480,55 @@ err: return kvmppc_bad_hva(); } -int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr) +int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, + bool data) { struct kvmppc_pte pte; - hva_t hva = eaddr; vcpu->stat.st++; - if (kvmppc_xlate(vcpu, eaddr, false, &pte)) - goto err; + if (kvmppc_xlate(vcpu, *eaddr, data, &pte)) + return -ENOENT; - hva = kvmppc_pte_to_hva(vcpu, &pte, false); - if (kvm_is_error_hva(hva)) - goto err; + *eaddr = pte.raddr; - if (copy_to_user((void __user *)hva, ptr, size)) { - printk(KERN_INFO "kvmppc_st at 0x%lx failed\n", hva); - goto err; - } + if (!pte.may_write) + return -EPERM; - return 0; + if (kvm_write_guest(vcpu->kvm, pte.raddr, ptr, size)) + return EMULATE_DO_MMIO; -err: - return -ENOENT; + return EMULATE_DONE; } -int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr, +int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data) { struct kvmppc_pte pte; - hva_t hva = eaddr; + hva_t hva = *eaddr; vcpu->stat.ld++; - if (kvmppc_xlate(vcpu, eaddr, data, &pte)) - goto err; + if (kvmppc_xlate(vcpu, *eaddr, data, &pte)) + goto nopte; + + *eaddr = pte.raddr; hva = kvmppc_pte_to_hva(vcpu, &pte, true); if (kvm_is_error_hva(hva)) - goto err; + goto mmio; if (copy_from_user(ptr, (void __user *)hva, size)) { printk(KERN_INFO "kvmppc_ld at 0x%lx failed\n", hva); - goto err; + goto mmio; } - return 0; + return EMULATE_DONE; -err: +nopte: return -ENOENT; +mmio: + return EMULATE_DO_MMIO; } static int kvmppc_visible_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) @@ -499,12 +545,11 @@ int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, int page_found = 0; struct kvmppc_pte pte; bool is_mmio = false; + bool dr = (vcpu->arch.msr & MSR_DR) ? true : false; + bool ir = (vcpu->arch.msr & MSR_IR) ? true : false; + u64 vsid; - if ( vec == BOOK3S_INTERRUPT_DATA_STORAGE ) { - relocated = (vcpu->arch.msr & MSR_DR); - } else { - relocated = (vcpu->arch.msr & MSR_IR); - } + relocated = data ? dr : ir; /* Resolve real address if translation turned on */ if (relocated) { @@ -516,14 +561,25 @@ int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, pte.raddr = eaddr & 0xffffffff; pte.eaddr = eaddr; pte.vpage = eaddr >> 12; - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - pte.vpage |= VSID_REAL; - case MSR_DR: - pte.vpage |= VSID_REAL_DR; - case MSR_IR: - pte.vpage |= VSID_REAL_IR; - } + } + + switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { + case 0: + pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); + break; + case MSR_DR: + case MSR_IR: + vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); + + if ((vcpu->arch.msr & (MSR_DR|MSR_IR)) == MSR_DR) + pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); + else + pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); + pte.vpage |= vsid; + + if (vsid == -1) + page_found = -EINVAL; + break; } if (vcpu->arch.mmu.is_dcbz32(vcpu) && @@ -538,20 +594,20 @@ int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, if (page_found == -ENOENT) { /* Page not found in guest PTE entries */ - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr; - vcpu->arch.msr |= (vcpu->arch.shadow_srr1 & 0x00000000f8000000ULL); + vcpu->arch.dear = kvmppc_get_fault_dar(vcpu); + to_book3s(vcpu)->dsisr = to_svcpu(vcpu)->fault_dsisr; + vcpu->arch.msr |= (to_svcpu(vcpu)->shadow_srr1 & 0x00000000f8000000ULL); kvmppc_book3s_queue_irqprio(vcpu, vec); } else if (page_found == -EPERM) { /* Storage protection */ - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr & ~DSISR_NOHPTE; + vcpu->arch.dear = kvmppc_get_fault_dar(vcpu); + to_book3s(vcpu)->dsisr = to_svcpu(vcpu)->fault_dsisr & ~DSISR_NOHPTE; to_book3s(vcpu)->dsisr |= DSISR_PROTFAULT; - vcpu->arch.msr |= (vcpu->arch.shadow_srr1 & 0x00000000f8000000ULL); + vcpu->arch.msr |= (to_svcpu(vcpu)->shadow_srr1 & 0x00000000f8000000ULL); kvmppc_book3s_queue_irqprio(vcpu, vec); } else if (page_found == -EINVAL) { /* Page not found in guest SLB */ - vcpu->arch.dear = vcpu->arch.fault_dear; + vcpu->arch.dear = kvmppc_get_fault_dar(vcpu); kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); } else if (!is_mmio && kvmppc_visible_gfn(vcpu, pte.raddr >> PAGE_SHIFT)) { @@ -583,11 +639,13 @@ static inline int get_fpr_index(int i) } /* Give up external provider (FPU, Altivec, VSX) */ -static void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) +void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) { struct thread_struct *t = ¤t->thread; u64 *vcpu_fpr = vcpu->arch.fpr; +#ifdef CONFIG_VSX u64 *vcpu_vsx = vcpu->arch.vsr; +#endif u64 *thread_fpr = (u64*)t->fpr; int i; @@ -629,21 +687,65 @@ static void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) kvmppc_recalc_shadow_msr(vcpu); } +static int kvmppc_read_inst(struct kvm_vcpu *vcpu) +{ + ulong srr0 = kvmppc_get_pc(vcpu); + u32 last_inst = kvmppc_get_last_inst(vcpu); + int ret; + + ret = kvmppc_ld(vcpu, &srr0, sizeof(u32), &last_inst, false); + if (ret == -ENOENT) { + vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 33, 33, 1); + vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 34, 36, 0); + vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 42, 47, 0); + kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_INST_STORAGE); + return EMULATE_AGAIN; + } + + return EMULATE_DONE; +} + +static int kvmppc_check_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr) +{ + + /* Need to do paired single emulation? */ + if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)) + return EMULATE_DONE; + + /* Read out the instruction */ + if (kvmppc_read_inst(vcpu) == EMULATE_DONE) + /* Need to emulate */ + return EMULATE_FAIL; + + return EMULATE_AGAIN; +} + /* Handle external providers (FPU, Altivec, VSX) */ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr) { struct thread_struct *t = ¤t->thread; u64 *vcpu_fpr = vcpu->arch.fpr; +#ifdef CONFIG_VSX u64 *vcpu_vsx = vcpu->arch.vsr; +#endif u64 *thread_fpr = (u64*)t->fpr; int i; + /* When we have paired singles, we emulate in software */ + if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) + return RESUME_GUEST; + if (!(vcpu->arch.msr & msr)) { kvmppc_book3s_queue_irqprio(vcpu, exit_nr); return RESUME_GUEST; } + /* We already own the ext */ + if (vcpu->arch.guest_owned_ext & msr) { + return RESUME_GUEST; + } + #ifdef DEBUG_EXT printk(KERN_INFO "Loading up ext 0x%lx\n", msr); #endif @@ -696,21 +798,33 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, run->ready_for_interrupt_injection = 1; #ifdef EXIT_DEBUG printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | dec=0x%x | msr=0x%lx\n", - exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear, - kvmppc_get_dec(vcpu), vcpu->arch.msr); + exit_nr, kvmppc_get_pc(vcpu), kvmppc_get_fault_dar(vcpu), + kvmppc_get_dec(vcpu), to_svcpu(vcpu)->shadow_srr1); #elif defined (EXIT_DEBUG_SIMPLE) if ((exit_nr != 0x900) && (exit_nr != 0x500)) printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | msr=0x%lx\n", - exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear, + exit_nr, kvmppc_get_pc(vcpu), kvmppc_get_fault_dar(vcpu), vcpu->arch.msr); #endif kvm_resched(vcpu); switch (exit_nr) { case BOOK3S_INTERRUPT_INST_STORAGE: vcpu->stat.pf_instruc++; + +#ifdef CONFIG_PPC_BOOK3S_32 + /* We set segments as unused segments when invalidating them. So + * treat the respective fault as segment fault. */ + if (to_svcpu(vcpu)->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT] + == SR_INVALID) { + kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); + r = RESUME_GUEST; + break; + } +#endif + /* only care about PTEG not found errors, but leave NX alone */ - if (vcpu->arch.shadow_srr1 & 0x40000000) { - r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.pc, exit_nr); + if (to_svcpu(vcpu)->shadow_srr1 & 0x40000000) { + r = kvmppc_handle_pagefault(run, vcpu, kvmppc_get_pc(vcpu), exit_nr); vcpu->stat.sp_instruc++; } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { @@ -719,37 +833,52 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, * so we can't use the NX bit inside the guest. Let's cross our fingers, * that no guest that needs the dcbz hack does NX. */ - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL); + kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); + r = RESUME_GUEST; } else { - vcpu->arch.msr |= vcpu->arch.shadow_srr1 & 0x58000000; + vcpu->arch.msr |= to_svcpu(vcpu)->shadow_srr1 & 0x58000000; kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL); + kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); r = RESUME_GUEST; } break; case BOOK3S_INTERRUPT_DATA_STORAGE: + { + ulong dar = kvmppc_get_fault_dar(vcpu); vcpu->stat.pf_storage++; + +#ifdef CONFIG_PPC_BOOK3S_32 + /* We set segments as unused segments when invalidating them. So + * treat the respective fault as segment fault. */ + if ((to_svcpu(vcpu)->sr[dar >> SID_SHIFT]) == SR_INVALID) { + kvmppc_mmu_map_segment(vcpu, dar); + r = RESUME_GUEST; + break; + } +#endif + /* The only case we need to handle is missing shadow PTEs */ - if (vcpu->arch.fault_dsisr & DSISR_NOHPTE) { - r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.fault_dear, exit_nr); + if (to_svcpu(vcpu)->fault_dsisr & DSISR_NOHPTE) { + r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr); } else { - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr; + vcpu->arch.dear = dar; + to_book3s(vcpu)->dsisr = to_svcpu(vcpu)->fault_dsisr; kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.dear, ~0xFFFULL); + kvmppc_mmu_pte_flush(vcpu, vcpu->arch.dear, ~0xFFFUL); r = RESUME_GUEST; } break; + } case BOOK3S_INTERRUPT_DATA_SEGMENT: - if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.fault_dear) < 0) { - vcpu->arch.dear = vcpu->arch.fault_dear; + if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { + vcpu->arch.dear = kvmppc_get_fault_dar(vcpu); kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_SEGMENT); } r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_INST_SEGMENT: - if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc) < 0) { + if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_INST_SEGMENT); } @@ -764,18 +893,22 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, vcpu->stat.ext_intr_exits++; r = RESUME_GUEST; break; + case BOOK3S_INTERRUPT_PERFMON: + r = RESUME_GUEST; + break; case BOOK3S_INTERRUPT_PROGRAM: { enum emulation_result er; ulong flags; - flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; +program_interrupt: + flags = to_svcpu(vcpu)->shadow_srr1 & 0x1f0000ull; if (vcpu->arch.msr & MSR_PR) { #ifdef EXIT_DEBUG - printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", vcpu->arch.pc, vcpu->arch.last_inst); + printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu)); #endif - if ((vcpu->arch.last_inst & 0xff0007ff) != + if ((kvmppc_get_last_inst(vcpu) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) { kvmppc_core_queue_program(vcpu, flags); r = RESUME_GUEST; @@ -789,33 +922,80 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, case EMULATE_DONE: r = RESUME_GUEST_NV; break; + case EMULATE_AGAIN: + r = RESUME_GUEST; + break; case EMULATE_FAIL: printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", - __func__, vcpu->arch.pc, vcpu->arch.last_inst); + __func__, kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu)); kvmppc_core_queue_program(vcpu, flags); r = RESUME_GUEST; break; + case EMULATE_DO_MMIO: + run->exit_reason = KVM_EXIT_MMIO; + r = RESUME_HOST_NV; + break; default: BUG(); } break; } case BOOK3S_INTERRUPT_SYSCALL: -#ifdef EXIT_DEBUG - printk(KERN_INFO "Syscall Nr %d\n", (int)kvmppc_get_gpr(vcpu, 0)); -#endif - vcpu->stat.syscall_exits++; - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - r = RESUME_GUEST; + // XXX make user settable + if (vcpu->arch.osi_enabled && + (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && + (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { + u64 *gprs = run->osi.gprs; + int i; + + run->exit_reason = KVM_EXIT_OSI; + for (i = 0; i < 32; i++) + gprs[i] = kvmppc_get_gpr(vcpu, i); + vcpu->arch.osi_needed = 1; + r = RESUME_HOST_NV; + + } else { + vcpu->stat.syscall_exits++; + kvmppc_book3s_queue_irqprio(vcpu, exit_nr); + r = RESUME_GUEST; + } break; case BOOK3S_INTERRUPT_FP_UNAVAIL: - r = kvmppc_handle_ext(vcpu, exit_nr, MSR_FP); - break; case BOOK3S_INTERRUPT_ALTIVEC: - r = kvmppc_handle_ext(vcpu, exit_nr, MSR_VEC); - break; case BOOK3S_INTERRUPT_VSX: - r = kvmppc_handle_ext(vcpu, exit_nr, MSR_VSX); + { + int ext_msr = 0; + + switch (exit_nr) { + case BOOK3S_INTERRUPT_FP_UNAVAIL: ext_msr = MSR_FP; break; + case BOOK3S_INTERRUPT_ALTIVEC: ext_msr = MSR_VEC; break; + case BOOK3S_INTERRUPT_VSX: ext_msr = MSR_VSX; break; + } + + switch (kvmppc_check_ext(vcpu, exit_nr)) { + case EMULATE_DONE: + /* everything ok - let's enable the ext */ + r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); + break; + case EMULATE_FAIL: + /* we need to emulate this instruction */ + goto program_interrupt; + break; + default: + /* nothing to worry about - go again */ + break; + } + break; + } + case BOOK3S_INTERRUPT_ALIGNMENT: + if (kvmppc_read_inst(vcpu) == EMULATE_DONE) { + to_book3s(vcpu)->dsisr = kvmppc_alignment_dsisr(vcpu, + kvmppc_get_last_inst(vcpu)); + vcpu->arch.dear = kvmppc_alignment_dar(vcpu, + kvmppc_get_last_inst(vcpu)); + kvmppc_book3s_queue_irqprio(vcpu, exit_nr); + } + r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_MACHINE_CHECK: case BOOK3S_INTERRUPT_TRACE: @@ -825,7 +1005,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, default: /* Ugh - bork here! What did we get? */ printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", - exit_nr, vcpu->arch.pc, vcpu->arch.shadow_srr1); + exit_nr, kvmppc_get_pc(vcpu), to_svcpu(vcpu)->shadow_srr1); r = RESUME_HOST; BUG(); break; @@ -852,7 +1032,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, } #ifdef EXIT_DEBUG - printk(KERN_EMERG "KVM exit: vcpu=0x%p pc=0x%lx r=0x%x\n", vcpu, vcpu->arch.pc, r); + printk(KERN_EMERG "KVM exit: vcpu=0x%p pc=0x%lx r=0x%x\n", vcpu, kvmppc_get_pc(vcpu), r); #endif return r; @@ -867,10 +1047,12 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; - regs->pc = vcpu->arch.pc; + vcpu_load(vcpu); + + regs->pc = kvmppc_get_pc(vcpu); regs->cr = kvmppc_get_cr(vcpu); - regs->ctr = vcpu->arch.ctr; - regs->lr = vcpu->arch.lr; + regs->ctr = kvmppc_get_ctr(vcpu); + regs->lr = kvmppc_get_lr(vcpu); regs->xer = kvmppc_get_xer(vcpu); regs->msr = vcpu->arch.msr; regs->srr0 = vcpu->arch.srr0; @@ -887,6 +1069,8 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) regs->gpr[i] = kvmppc_get_gpr(vcpu, i); + vcpu_put(vcpu); + return 0; } @@ -894,10 +1078,12 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; - vcpu->arch.pc = regs->pc; + vcpu_load(vcpu); + + kvmppc_set_pc(vcpu, regs->pc); kvmppc_set_cr(vcpu, regs->cr); - vcpu->arch.ctr = regs->ctr; - vcpu->arch.lr = regs->lr; + kvmppc_set_ctr(vcpu, regs->ctr); + kvmppc_set_lr(vcpu, regs->lr); kvmppc_set_xer(vcpu, regs->xer); kvmppc_set_msr(vcpu, regs->msr); vcpu->arch.srr0 = regs->srr0; @@ -913,6 +1099,8 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) kvmppc_set_gpr(vcpu, i, regs->gpr[i]); + vcpu_put(vcpu); + return 0; } @@ -922,6 +1110,8 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); int i; + vcpu_load(vcpu); + sregs->pvr = vcpu->arch.pvr; sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; @@ -940,6 +1130,9 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; } } + + vcpu_put(vcpu); + return 0; } @@ -949,6 +1142,8 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); int i; + vcpu_load(vcpu); + kvmppc_set_pvr(vcpu, sregs->pvr); vcpu3s->sdr1 = sregs->u.s.sdr1; @@ -975,6 +1170,9 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, /* Flush the MMU after messing with the segments */ kvmppc_mmu_pte_flush(vcpu, 0, 0); + + vcpu_put(vcpu); + return 0; } @@ -1042,24 +1240,33 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) { struct kvmppc_vcpu_book3s *vcpu_book3s; struct kvm_vcpu *vcpu; - int err; + int err = -ENOMEM; - vcpu_book3s = (struct kvmppc_vcpu_book3s *)__get_free_pages( GFP_KERNEL | __GFP_ZERO, - get_order(sizeof(struct kvmppc_vcpu_book3s))); - if (!vcpu_book3s) { - err = -ENOMEM; + vcpu_book3s = vmalloc(sizeof(struct kvmppc_vcpu_book3s)); + if (!vcpu_book3s) goto out; - } + + memset(vcpu_book3s, 0, sizeof(struct kvmppc_vcpu_book3s)); + + vcpu_book3s->shadow_vcpu = (struct kvmppc_book3s_shadow_vcpu *) + kzalloc(sizeof(*vcpu_book3s->shadow_vcpu), GFP_KERNEL); + if (!vcpu_book3s->shadow_vcpu) + goto free_vcpu; vcpu = &vcpu_book3s->vcpu; err = kvm_vcpu_init(vcpu, kvm, id); if (err) - goto free_vcpu; + goto free_shadow_vcpu; vcpu->arch.host_retip = kvm_return_point; vcpu->arch.host_msr = mfmsr(); +#ifdef CONFIG_PPC_BOOK3S_64 /* default to book3s_64 (970fx) */ vcpu->arch.pvr = 0x3C0301; +#else + /* default to book3s_32 (750) */ + vcpu->arch.pvr = 0x84202; +#endif kvmppc_set_pvr(vcpu, vcpu->arch.pvr); vcpu_book3s->slb_nr = 64; @@ -1067,23 +1274,24 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) vcpu->arch.trampoline_lowmem = kvmppc_trampoline_lowmem; vcpu->arch.trampoline_enter = kvmppc_trampoline_enter; vcpu->arch.highmem_handler = (ulong)kvmppc_handler_highmem; +#ifdef CONFIG_PPC_BOOK3S_64 vcpu->arch.rmcall = *(ulong*)kvmppc_rmcall; +#else + vcpu->arch.rmcall = (ulong)kvmppc_rmcall; +#endif vcpu->arch.shadow_msr = MSR_USER64; - err = __init_new_context(); + err = kvmppc_mmu_init(vcpu); if (err < 0) - goto free_vcpu; - vcpu_book3s->context_id = err; - - vcpu_book3s->vsid_max = ((vcpu_book3s->context_id + 1) << USER_ESID_BITS) - 1; - vcpu_book3s->vsid_first = vcpu_book3s->context_id << USER_ESID_BITS; - vcpu_book3s->vsid_next = vcpu_book3s->vsid_first; + goto free_shadow_vcpu; return vcpu; +free_shadow_vcpu: + kfree(vcpu_book3s->shadow_vcpu); free_vcpu: - free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s))); + vfree(vcpu_book3s); out: return ERR_PTR(err); } @@ -1092,9 +1300,9 @@ void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) { struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - __destroy_context(vcpu_book3s->context_id); kvm_vcpu_uninit(vcpu); - free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s))); + kfree(vcpu_book3s->shadow_vcpu); + vfree(vcpu_book3s); } extern int __kvmppc_vcpu_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu); @@ -1102,8 +1310,12 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) { int ret; struct thread_struct ext_bkp; +#ifdef CONFIG_ALTIVEC bool save_vec = current->thread.used_vr; +#endif +#ifdef CONFIG_VSX bool save_vsx = current->thread.used_vsr; +#endif ulong ext_msr; /* No need to go into the guest when all we do is going out */ @@ -1144,6 +1356,10 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) /* XXX we get called with irq disabled - change that! */ local_irq_enable(); + /* Preload FPU if it's enabled */ + if (vcpu->arch.msr & MSR_FP) + kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); + ret = __kvmppc_vcpu_entry(kvm_run, vcpu); local_irq_disable(); @@ -1179,7 +1395,8 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) static int kvmppc_book3s_init(void) { - return kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), THIS_MODULE); + return kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), 0, + THIS_MODULE); } static void kvmppc_book3s_exit(void) diff --git a/arch/powerpc/kvm/book3s_32_mmu.c b/arch/powerpc/kvm/book3s_32_mmu.c index faf99f20d993..0b10503c8a4a 100644 --- a/arch/powerpc/kvm/book3s_32_mmu.c +++ b/arch/powerpc/kvm/book3s_32_mmu.c @@ -37,7 +37,7 @@ #define dprintk(X...) do { } while(0) #endif -#ifdef DEBUG_PTE +#ifdef DEBUG_MMU_PTE #define dprintk_pte(X...) printk(KERN_INFO X) #else #define dprintk_pte(X...) do { } while(0) @@ -45,6 +45,9 @@ #define PTEG_FLAG_ACCESSED 0x00000100 #define PTEG_FLAG_DIRTY 0x00000080 +#ifndef SID_SHIFT +#define SID_SHIFT 28 +#endif static inline bool check_debug_ip(struct kvm_vcpu *vcpu) { @@ -57,6 +60,8 @@ static inline bool check_debug_ip(struct kvm_vcpu *vcpu) static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data); +static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid, + u64 *vsid); static struct kvmppc_sr *find_sr(struct kvmppc_vcpu_book3s *vcpu_book3s, gva_t eaddr) { @@ -66,13 +71,14 @@ static struct kvmppc_sr *find_sr(struct kvmppc_vcpu_book3s *vcpu_book3s, gva_t e static u64 kvmppc_mmu_book3s_32_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr, bool data) { - struct kvmppc_sr *sre = find_sr(to_book3s(vcpu), eaddr); + u64 vsid; struct kvmppc_pte pte; if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data)) return pte.vpage; - return (((u64)eaddr >> 12) & 0xffff) | (((u64)sre->vsid) << 16); + kvmppc_mmu_book3s_32_esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); + return (((u64)eaddr >> 12) & 0xffff) | (vsid << 16); } static void kvmppc_mmu_book3s_32_reset_msr(struct kvm_vcpu *vcpu) @@ -142,8 +148,13 @@ static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr, bat->bepi_mask); } if ((eaddr & bat->bepi_mask) == bat->bepi) { + u64 vsid; + kvmppc_mmu_book3s_32_esid_to_vsid(vcpu, + eaddr >> SID_SHIFT, &vsid); + vsid <<= 16; + pte->vpage = (((u64)eaddr >> 12) & 0xffff) | vsid; + pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask); - pte->vpage = (eaddr >> 12) | VSID_BAT; pte->may_read = bat->pp; pte->may_write = bat->pp > 1; pte->may_execute = true; @@ -172,7 +183,7 @@ static int kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_sr *sre; hva_t ptegp; u32 pteg[16]; - u64 ptem = 0; + u32 ptem = 0; int i; int found = 0; @@ -302,6 +313,7 @@ static void kvmppc_mmu_book3s_32_mtsrin(struct kvm_vcpu *vcpu, u32 srnum, /* And then put in the new SR */ sre->raw = value; sre->vsid = (value & 0x0fffffff); + sre->valid = (value & 0x80000000) ? false : true; sre->Ks = (value & 0x40000000) ? true : false; sre->Kp = (value & 0x20000000) ? true : false; sre->nx = (value & 0x10000000) ? true : false; @@ -312,36 +324,48 @@ static void kvmppc_mmu_book3s_32_mtsrin(struct kvm_vcpu *vcpu, u32 srnum, static void kvmppc_mmu_book3s_32_tlbie(struct kvm_vcpu *vcpu, ulong ea, bool large) { - kvmppc_mmu_pte_flush(vcpu, ea, ~0xFFFULL); + kvmppc_mmu_pte_flush(vcpu, ea, 0x0FFFF000); } -static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid, +static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid, u64 *vsid) { + ulong ea = esid << SID_SHIFT; + struct kvmppc_sr *sr; + u64 gvsid = esid; + + if (vcpu->arch.msr & (MSR_DR|MSR_IR)) { + sr = find_sr(to_book3s(vcpu), ea); + if (sr->valid) + gvsid = sr->vsid; + } + /* In case we only have one of MSR_IR or MSR_DR set, let's put that in the real-mode context (and hope RM doesn't access high memory) */ switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { case 0: - *vsid = (VSID_REAL >> 16) | esid; + *vsid = VSID_REAL | esid; break; case MSR_IR: - *vsid = (VSID_REAL_IR >> 16) | esid; + *vsid = VSID_REAL_IR | gvsid; break; case MSR_DR: - *vsid = (VSID_REAL_DR >> 16) | esid; + *vsid = VSID_REAL_DR | gvsid; break; case MSR_DR|MSR_IR: - { - ulong ea; - ea = esid << SID_SHIFT; - *vsid = find_sr(to_book3s(vcpu), ea)->vsid; + if (!sr->valid) + return -1; + + *vsid = sr->vsid; break; - } default: BUG(); } + if (vcpu->arch.msr & MSR_PR) + *vsid |= VSID_PR; + return 0; } diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c new file mode 100644 index 000000000000..0bb66005338f --- /dev/null +++ b/arch/powerpc/kvm/book3s_32_mmu_host.c @@ -0,0 +1,483 @@ +/* + * Copyright (C) 2010 SUSE Linux Products GmbH. All rights reserved. + * + * Authors: + * Alexander Graf <agraf@suse.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kvm_host.h> + +#include <asm/kvm_ppc.h> +#include <asm/kvm_book3s.h> +#include <asm/mmu-hash32.h> +#include <asm/machdep.h> +#include <asm/mmu_context.h> +#include <asm/hw_irq.h> + +/* #define DEBUG_MMU */ +/* #define DEBUG_SR */ + +#ifdef DEBUG_MMU +#define dprintk_mmu(a, ...) printk(KERN_INFO a, __VA_ARGS__) +#else +#define dprintk_mmu(a, ...) do { } while(0) +#endif + +#ifdef DEBUG_SR +#define dprintk_sr(a, ...) printk(KERN_INFO a, __VA_ARGS__) +#else +#define dprintk_sr(a, ...) do { } while(0) +#endif + +#if PAGE_SHIFT != 12 +#error Unknown page size +#endif + +#ifdef CONFIG_SMP +#error XXX need to grab mmu_hash_lock +#endif + +#ifdef CONFIG_PTE_64BIT +#error Only 32 bit pages are supported for now +#endif + +static ulong htab; +static u32 htabmask; + +static void invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte) +{ + volatile u32 *pteg; + + dprintk_mmu("KVM: Flushing SPTE: 0x%llx (0x%llx) -> 0x%llx\n", + pte->pte.eaddr, pte->pte.vpage, pte->host_va); + + pteg = (u32*)pte->slot; + + pteg[0] = 0; + asm volatile ("sync"); + asm volatile ("tlbie %0" : : "r" (pte->pte.eaddr) : "memory"); + asm volatile ("sync"); + asm volatile ("tlbsync"); + + pte->host_va = 0; + + if (pte->pte.may_write) + kvm_release_pfn_dirty(pte->pfn); + else + kvm_release_pfn_clean(pte->pfn); +} + +void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask) +{ + int i; + + dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%x & 0x%x\n", + vcpu->arch.hpte_cache_offset, guest_ea, ea_mask); + BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); + + guest_ea &= ea_mask; + for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { + struct hpte_cache *pte; + + pte = &vcpu->arch.hpte_cache[i]; + if (!pte->host_va) + continue; + + if ((pte->pte.eaddr & ea_mask) == guest_ea) { + invalidate_pte(vcpu, pte); + } + } + + /* Doing a complete flush -> start from scratch */ + if (!ea_mask) + vcpu->arch.hpte_cache_offset = 0; +} + +void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask) +{ + int i; + + dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n", + vcpu->arch.hpte_cache_offset, guest_vp, vp_mask); + BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); + + guest_vp &= vp_mask; + for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { + struct hpte_cache *pte; + + pte = &vcpu->arch.hpte_cache[i]; + if (!pte->host_va) + continue; + + if ((pte->pte.vpage & vp_mask) == guest_vp) { + invalidate_pte(vcpu, pte); + } + } +} + +void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end) +{ + int i; + + dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n", + vcpu->arch.hpte_cache_offset, pa_start, pa_end); + BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); + + for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { + struct hpte_cache *pte; + + pte = &vcpu->arch.hpte_cache[i]; + if (!pte->host_va) + continue; + + if ((pte->pte.raddr >= pa_start) && + (pte->pte.raddr < pa_end)) { + invalidate_pte(vcpu, pte); + } + } +} + +struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data) +{ + int i; + u64 guest_vp; + + guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false); + for (i=0; i<vcpu->arch.hpte_cache_offset; i++) { + struct hpte_cache *pte; + + pte = &vcpu->arch.hpte_cache[i]; + if (!pte->host_va) + continue; + + if (pte->pte.vpage == guest_vp) + return &pte->pte; + } + + return NULL; +} + +static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM) + kvmppc_mmu_pte_flush(vcpu, 0, 0); + + return vcpu->arch.hpte_cache_offset++; +} + +/* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using + * a hash, so we don't waste cycles on looping */ +static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid) +{ + return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^ + ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK)); +} + + +static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid) +{ + struct kvmppc_sid_map *map; + u16 sid_map_mask; + + if (vcpu->arch.msr & MSR_PR) + gvsid |= VSID_PR; + + sid_map_mask = kvmppc_sid_hash(vcpu, gvsid); + map = &to_book3s(vcpu)->sid_map[sid_map_mask]; + if (map->guest_vsid == gvsid) { + dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n", + gvsid, map->host_vsid); + return map; + } + + map = &to_book3s(vcpu)->sid_map[SID_MAP_MASK - sid_map_mask]; + if (map->guest_vsid == gvsid) { + dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n", + gvsid, map->host_vsid); + return map; + } + + dprintk_sr("SR: Searching 0x%llx -> not found\n", gvsid); + return NULL; +} + +static u32 *kvmppc_mmu_get_pteg(struct kvm_vcpu *vcpu, u32 vsid, u32 eaddr, + bool primary) +{ + u32 page, hash; + ulong pteg = htab; + + page = (eaddr & ~ESID_MASK) >> 12; + + hash = ((vsid ^ page) << 6); + if (!primary) + hash = ~hash; + + hash &= htabmask; + + pteg |= hash; + + dprintk_mmu("htab: %lx | hash: %x | htabmask: %x | pteg: %lx\n", + htab, hash, htabmask, pteg); + + return (u32*)pteg; +} + +extern char etext[]; + +int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) +{ + pfn_t hpaddr; + u64 va; + u64 vsid; + struct kvmppc_sid_map *map; + volatile u32 *pteg; + u32 eaddr = orig_pte->eaddr; + u32 pteg0, pteg1; + register int rr = 0; + bool primary = false; + bool evict = false; + int hpte_id; + struct hpte_cache *pte; + + /* Get host physical address for gpa */ + hpaddr = gfn_to_pfn(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT); + if (kvm_is_error_hva(hpaddr)) { + printk(KERN_INFO "Couldn't get guest page for gfn %lx!\n", + orig_pte->eaddr); + return -EINVAL; + } + hpaddr <<= PAGE_SHIFT; + + /* and write the mapping ea -> hpa into the pt */ + vcpu->arch.mmu.esid_to_vsid(vcpu, orig_pte->eaddr >> SID_SHIFT, &vsid); + map = find_sid_vsid(vcpu, vsid); + if (!map) { + kvmppc_mmu_map_segment(vcpu, eaddr); + map = find_sid_vsid(vcpu, vsid); + } + BUG_ON(!map); + + vsid = map->host_vsid; + va = (vsid << SID_SHIFT) | (eaddr & ~ESID_MASK); + +next_pteg: + if (rr == 16) { + primary = !primary; + evict = true; + rr = 0; + } + + pteg = kvmppc_mmu_get_pteg(vcpu, vsid, eaddr, primary); + + /* not evicting yet */ + if (!evict && (pteg[rr] & PTE_V)) { + rr += 2; + goto next_pteg; + } + + dprintk_mmu("KVM: old PTEG: %p (%d)\n", pteg, rr); + dprintk_mmu("KVM: %08x - %08x\n", pteg[0], pteg[1]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[2], pteg[3]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[4], pteg[5]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[6], pteg[7]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[8], pteg[9]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[10], pteg[11]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[12], pteg[13]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[14], pteg[15]); + + pteg0 = ((eaddr & 0x0fffffff) >> 22) | (vsid << 7) | PTE_V | + (primary ? 0 : PTE_SEC); + pteg1 = hpaddr | PTE_M | PTE_R | PTE_C; + + if (orig_pte->may_write) { + pteg1 |= PP_RWRW; + mark_page_dirty(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT); + } else { + pteg1 |= PP_RWRX; + } + + local_irq_disable(); + + if (pteg[rr]) { + pteg[rr] = 0; + asm volatile ("sync"); + } + pteg[rr + 1] = pteg1; + pteg[rr] = pteg0; + asm volatile ("sync"); + + local_irq_enable(); + + dprintk_mmu("KVM: new PTEG: %p\n", pteg); + dprintk_mmu("KVM: %08x - %08x\n", pteg[0], pteg[1]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[2], pteg[3]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[4], pteg[5]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[6], pteg[7]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[8], pteg[9]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[10], pteg[11]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[12], pteg[13]); + dprintk_mmu("KVM: %08x - %08x\n", pteg[14], pteg[15]); + + + /* Now tell our Shadow PTE code about the new page */ + + hpte_id = kvmppc_mmu_hpte_cache_next(vcpu); + pte = &vcpu->arch.hpte_cache[hpte_id]; + + dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n", + orig_pte->may_write ? 'w' : '-', + orig_pte->may_execute ? 'x' : '-', + orig_pte->eaddr, (ulong)pteg, va, + orig_pte->vpage, hpaddr); + + pte->slot = (ulong)&pteg[rr]; + pte->host_va = va; + pte->pte = *orig_pte; + pte->pfn = hpaddr >> PAGE_SHIFT; + + return 0; +} + +static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid) +{ + struct kvmppc_sid_map *map; + struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); + u16 sid_map_mask; + static int backwards_map = 0; + + if (vcpu->arch.msr & MSR_PR) + gvsid |= VSID_PR; + + /* We might get collisions that trap in preceding order, so let's + map them differently */ + + sid_map_mask = kvmppc_sid_hash(vcpu, gvsid); + if (backwards_map) + sid_map_mask = SID_MAP_MASK - sid_map_mask; + + map = &to_book3s(vcpu)->sid_map[sid_map_mask]; + + /* Make sure we're taking the other map next time */ + backwards_map = !backwards_map; + + /* Uh-oh ... out of mappings. Let's flush! */ + if (vcpu_book3s->vsid_next >= vcpu_book3s->vsid_max) { + vcpu_book3s->vsid_next = vcpu_book3s->vsid_first; + memset(vcpu_book3s->sid_map, 0, + sizeof(struct kvmppc_sid_map) * SID_MAP_NUM); + kvmppc_mmu_pte_flush(vcpu, 0, 0); + kvmppc_mmu_flush_segments(vcpu); + } + map->host_vsid = vcpu_book3s->vsid_next; + + /* Would have to be 111 to be completely aligned with the rest of + Linux, but that is just way too little space! */ + vcpu_book3s->vsid_next+=1; + + map->guest_vsid = gvsid; + map->valid = true; + + return map; +} + +int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr) +{ + u32 esid = eaddr >> SID_SHIFT; + u64 gvsid; + u32 sr; + struct kvmppc_sid_map *map; + struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu); + + if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) { + /* Invalidate an entry */ + svcpu->sr[esid] = SR_INVALID; + return -ENOENT; + } + + map = find_sid_vsid(vcpu, gvsid); + if (!map) + map = create_sid_map(vcpu, gvsid); + + map->guest_esid = esid; + sr = map->host_vsid | SR_KP; + svcpu->sr[esid] = sr; + + dprintk_sr("MMU: mtsr %d, 0x%x\n", esid, sr); + + return 0; +} + +void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu) +{ + int i; + struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu); + + dprintk_sr("MMU: flushing all segments (%d)\n", ARRAY_SIZE(svcpu->sr)); + for (i = 0; i < ARRAY_SIZE(svcpu->sr); i++) + svcpu->sr[i] = SR_INVALID; +} + +void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu) +{ + kvmppc_mmu_pte_flush(vcpu, 0, 0); + preempt_disable(); + __destroy_context(to_book3s(vcpu)->context_id); + preempt_enable(); +} + +/* From mm/mmu_context_hash32.c */ +#define CTX_TO_VSID(ctx) (((ctx) * (897 * 16)) & 0xffffff) + +int kvmppc_mmu_init(struct kvm_vcpu *vcpu) +{ + struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); + int err; + ulong sdr1; + + err = __init_new_context(); + if (err < 0) + return -1; + vcpu3s->context_id = err; + + vcpu3s->vsid_max = CTX_TO_VSID(vcpu3s->context_id + 1) - 1; + vcpu3s->vsid_first = CTX_TO_VSID(vcpu3s->context_id); + +#if 0 /* XXX still doesn't guarantee uniqueness */ + /* We could collide with the Linux vsid space because the vsid + * wraps around at 24 bits. We're safe if we do our own space + * though, so let's always set the highest bit. */ + + vcpu3s->vsid_max |= 0x00800000; + vcpu3s->vsid_first |= 0x00800000; +#endif + BUG_ON(vcpu3s->vsid_max < vcpu3s->vsid_first); + + vcpu3s->vsid_next = vcpu3s->vsid_first; + + /* Remember where the HTAB is */ + asm ( "mfsdr1 %0" : "=r"(sdr1) ); + htabmask = ((sdr1 & 0x1FF) << 16) | 0xFFC0; + htab = (ulong)__va(sdr1 & 0xffff0000); + + return 0; +} diff --git a/arch/powerpc/kvm/book3s_32_sr.S b/arch/powerpc/kvm/book3s_32_sr.S new file mode 100644 index 000000000000..3608471ad2d8 --- /dev/null +++ b/arch/powerpc/kvm/book3s_32_sr.S @@ -0,0 +1,143 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright SUSE Linux Products GmbH 2009 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +/****************************************************************************** + * * + * Entry code * + * * + *****************************************************************************/ + +.macro LOAD_GUEST_SEGMENTS + + /* Required state: + * + * MSR = ~IR|DR + * R1 = host R1 + * R2 = host R2 + * R3 = shadow vcpu + * all other volatile GPRS = free + * SVCPU[CR] = guest CR + * SVCPU[XER] = guest XER + * SVCPU[CTR] = guest CTR + * SVCPU[LR] = guest LR + */ + +#define XCHG_SR(n) lwz r9, (SVCPU_SR+(n*4))(r3); \ + mtsr n, r9 + + XCHG_SR(0) + XCHG_SR(1) + XCHG_SR(2) + XCHG_SR(3) + XCHG_SR(4) + XCHG_SR(5) + XCHG_SR(6) + XCHG_SR(7) + XCHG_SR(8) + XCHG_SR(9) + XCHG_SR(10) + XCHG_SR(11) + XCHG_SR(12) + XCHG_SR(13) + XCHG_SR(14) + XCHG_SR(15) + + /* Clear BATs. */ + +#define KVM_KILL_BAT(n, reg) \ + mtspr SPRN_IBAT##n##U,reg; \ + mtspr SPRN_IBAT##n##L,reg; \ + mtspr SPRN_DBAT##n##U,reg; \ + mtspr SPRN_DBAT##n##L,reg; \ + + li r9, 0 + KVM_KILL_BAT(0, r9) + KVM_KILL_BAT(1, r9) + KVM_KILL_BAT(2, r9) + KVM_KILL_BAT(3, r9) + +.endm + +/****************************************************************************** + * * + * Exit code * + * * + *****************************************************************************/ + +.macro LOAD_HOST_SEGMENTS + + /* Register usage at this point: + * + * R1 = host R1 + * R2 = host R2 + * R12 = exit handler id + * R13 = shadow vcpu - SHADOW_VCPU_OFF + * SVCPU.* = guest * + * SVCPU[CR] = guest CR + * SVCPU[XER] = guest XER + * SVCPU[CTR] = guest CTR + * SVCPU[LR] = guest LR + * + */ + + /* Restore BATs */ + + /* We only overwrite the upper part, so we only restoree + the upper part. */ +#define KVM_LOAD_BAT(n, reg, RA, RB) \ + lwz RA,(n*16)+0(reg); \ + lwz RB,(n*16)+4(reg); \ + mtspr SPRN_IBAT##n##U,RA; \ + mtspr SPRN_IBAT##n##L,RB; \ + lwz RA,(n*16)+8(reg); \ + lwz RB,(n*16)+12(reg); \ + mtspr SPRN_DBAT##n##U,RA; \ + mtspr SPRN_DBAT##n##L,RB; \ + + lis r9, BATS@ha + addi r9, r9, BATS@l + tophys(r9, r9) + KVM_LOAD_BAT(0, r9, r10, r11) + KVM_LOAD_BAT(1, r9, r10, r11) + KVM_LOAD_BAT(2, r9, r10, r11) + KVM_LOAD_BAT(3, r9, r10, r11) + + /* Restore Segment Registers */ + + /* 0xc - 0xf */ + + li r0, 4 + mtctr r0 + LOAD_REG_IMMEDIATE(r3, 0x20000000 | (0x111 * 0xc)) + lis r4, 0xc000 +3: mtsrin r3, r4 + addi r3, r3, 0x111 /* increment VSID */ + addis r4, r4, 0x1000 /* address of next segment */ + bdnz 3b + + /* 0x0 - 0xb */ + + /* 'current->mm' needs to be in r4 */ + tophys(r4, r2) + lwz r4, MM(r4) + tophys(r4, r4) + /* This only clobbers r0, r3, r4 and r5 */ + bl switch_mmu_context + +.endm diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index 512dcff77554..4025ea26b3c1 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -232,7 +232,7 @@ do_second: } dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx " - "-> 0x%llx\n", + "-> 0x%lx\n", eaddr, avpn, gpte->vpage, gpte->raddr); found = true; break; @@ -383,7 +383,7 @@ static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu) if (vcpu->arch.msr & MSR_IR) { kvmppc_mmu_flush_segments(vcpu); - kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc); + kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); } } @@ -439,37 +439,43 @@ static void kvmppc_mmu_book3s_64_tlbie(struct kvm_vcpu *vcpu, ulong va, kvmppc_mmu_pte_vflush(vcpu, va >> 12, mask); } -static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid, +static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid, u64 *vsid) { + ulong ea = esid << SID_SHIFT; + struct kvmppc_slb *slb; + u64 gvsid = esid; + + if (vcpu->arch.msr & (MSR_DR|MSR_IR)) { + slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), ea); + if (slb) + gvsid = slb->vsid; + } + switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { case 0: - *vsid = (VSID_REAL >> 16) | esid; + *vsid = VSID_REAL | esid; break; case MSR_IR: - *vsid = (VSID_REAL_IR >> 16) | esid; + *vsid = VSID_REAL_IR | gvsid; break; case MSR_DR: - *vsid = (VSID_REAL_DR >> 16) | esid; + *vsid = VSID_REAL_DR | gvsid; break; case MSR_DR|MSR_IR: - { - ulong ea; - struct kvmppc_slb *slb; - ea = esid << SID_SHIFT; - slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), ea); - if (slb) - *vsid = slb->vsid; - else + if (!slb) return -ENOENT; + *vsid = gvsid; break; - } default: BUG(); break; } + if (vcpu->arch.msr & MSR_PR) + *vsid |= VSID_PR; + return 0; } diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c index f2899b297ffd..e4b5744977f6 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_host.c +++ b/arch/powerpc/kvm/book3s_64_mmu_host.c @@ -48,21 +48,25 @@ static void invalidate_pte(struct hpte_cache *pte) { - dprintk_mmu("KVM: Flushing SPT %d: 0x%llx (0x%llx) -> 0x%llx\n", - i, pte->pte.eaddr, pte->pte.vpage, pte->host_va); + dprintk_mmu("KVM: Flushing SPT: 0x%lx (0x%llx) -> 0x%llx\n", + pte->pte.eaddr, pte->pte.vpage, pte->host_va); ppc_md.hpte_invalidate(pte->slot, pte->host_va, MMU_PAGE_4K, MMU_SEGSIZE_256M, false); pte->host_va = 0; - kvm_release_pfn_dirty(pte->pfn); + + if (pte->pte.may_write) + kvm_release_pfn_dirty(pte->pfn); + else + kvm_release_pfn_clean(pte->pfn); } -void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 guest_ea, u64 ea_mask) +void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask) { int i; - dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%llx & 0x%llx\n", + dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%lx & 0x%lx\n", vcpu->arch.hpte_cache_offset, guest_ea, ea_mask); BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); @@ -106,12 +110,12 @@ void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask) } } -void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end) +void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end) { int i; - dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n", - vcpu->arch.hpte_cache_offset, guest_pa, pa_mask); + dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%lx & 0x%lx\n", + vcpu->arch.hpte_cache_offset, pa_start, pa_end); BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { @@ -182,7 +186,7 @@ static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid) sid_map_mask = kvmppc_sid_hash(vcpu, gvsid); map = &to_book3s(vcpu)->sid_map[sid_map_mask]; if (map->guest_vsid == gvsid) { - dprintk_slb("SLB: Searching 0x%llx -> 0x%llx\n", + dprintk_slb("SLB: Searching: 0x%llx -> 0x%llx\n", gvsid, map->host_vsid); return map; } @@ -194,7 +198,8 @@ static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid) return map; } - dprintk_slb("SLB: Searching 0x%llx -> not found\n", gvsid); + dprintk_slb("SLB: Searching %d/%d: 0x%llx -> not found\n", + sid_map_mask, SID_MAP_MASK - sid_map_mask, gvsid); return NULL; } @@ -212,7 +217,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) /* Get host physical address for gpa */ hpaddr = gfn_to_pfn(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT); if (kvm_is_error_hva(hpaddr)) { - printk(KERN_INFO "Couldn't get guest page for gfn %llx!\n", orig_pte->eaddr); + printk(KERN_INFO "Couldn't get guest page for gfn %lx!\n", orig_pte->eaddr); return -EINVAL; } hpaddr <<= PAGE_SHIFT; @@ -227,10 +232,16 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) vcpu->arch.mmu.esid_to_vsid(vcpu, orig_pte->eaddr >> SID_SHIFT, &vsid); map = find_sid_vsid(vcpu, vsid); if (!map) { - kvmppc_mmu_map_segment(vcpu, orig_pte->eaddr); + ret = kvmppc_mmu_map_segment(vcpu, orig_pte->eaddr); + WARN_ON(ret < 0); map = find_sid_vsid(vcpu, vsid); } - BUG_ON(!map); + if (!map) { + printk(KERN_ERR "KVM: Segment map for 0x%llx (0x%lx) failed\n", + vsid, orig_pte->eaddr); + WARN_ON(true); + return -EINVAL; + } vsid = map->host_vsid; va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M); @@ -257,26 +268,26 @@ map_again: if (ret < 0) { /* If we couldn't map a primary PTE, try a secondary */ -#ifdef USE_SECONDARY hash = ~hash; + vflags ^= HPTE_V_SECONDARY; attempt++; - if (attempt % 2) - vflags = HPTE_V_SECONDARY; - else - vflags = 0; -#else - attempt = 2; -#endif goto map_again; } else { int hpte_id = kvmppc_mmu_hpte_cache_next(vcpu); struct hpte_cache *pte = &vcpu->arch.hpte_cache[hpte_id]; - dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%lx (0x%llx) -> %lx\n", + dprintk_mmu("KVM: %c%c Map 0x%lx: [%lx] 0x%lx (0x%llx) -> %lx\n", ((rflags & HPTE_R_PP) == 3) ? '-' : 'w', (rflags & HPTE_R_N) ? '-' : 'x', orig_pte->eaddr, hpteg, va, orig_pte->vpage, hpaddr); + /* The ppc_md code may give us a secondary entry even though we + asked for a primary. Fix up. */ + if ((ret & _PTEIDX_SECONDARY) && !(vflags & HPTE_V_SECONDARY)) { + hash = ~hash; + hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); + } + pte->slot = hpteg + (ret & 7); pte->host_va = va; pte->pte = *orig_pte; @@ -321,6 +332,9 @@ static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid) map->guest_vsid = gvsid; map->valid = true; + dprintk_slb("SLB: New mapping at %d: 0x%llx -> 0x%llx\n", + sid_map_mask, gvsid, map->host_vsid); + return map; } @@ -331,14 +345,14 @@ static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid) int found_inval = -1; int r; - if (!get_paca()->kvm_slb_max) - get_paca()->kvm_slb_max = 1; + if (!to_svcpu(vcpu)->slb_max) + to_svcpu(vcpu)->slb_max = 1; /* Are we overwriting? */ - for (i = 1; i < get_paca()->kvm_slb_max; i++) { - if (!(get_paca()->kvm_slb[i].esid & SLB_ESID_V)) + for (i = 1; i < to_svcpu(vcpu)->slb_max; i++) { + if (!(to_svcpu(vcpu)->slb[i].esid & SLB_ESID_V)) found_inval = i; - else if ((get_paca()->kvm_slb[i].esid & ESID_MASK) == esid) + else if ((to_svcpu(vcpu)->slb[i].esid & ESID_MASK) == esid) return i; } @@ -352,11 +366,11 @@ static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid) max_slb_size = mmu_slb_size; /* Overflowing -> purge */ - if ((get_paca()->kvm_slb_max) == max_slb_size) + if ((to_svcpu(vcpu)->slb_max) == max_slb_size) kvmppc_mmu_flush_segments(vcpu); - r = get_paca()->kvm_slb_max; - get_paca()->kvm_slb_max++; + r = to_svcpu(vcpu)->slb_max; + to_svcpu(vcpu)->slb_max++; return r; } @@ -374,7 +388,7 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr) if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) { /* Invalidate an entry */ - get_paca()->kvm_slb[slb_index].esid = 0; + to_svcpu(vcpu)->slb[slb_index].esid = 0; return -ENOENT; } @@ -388,8 +402,8 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr) slb_vsid &= ~SLB_VSID_KP; slb_esid |= slb_index; - get_paca()->kvm_slb[slb_index].esid = slb_esid; - get_paca()->kvm_slb[slb_index].vsid = slb_vsid; + to_svcpu(vcpu)->slb[slb_index].esid = slb_esid; + to_svcpu(vcpu)->slb[slb_index].vsid = slb_vsid; dprintk_slb("slbmte %#llx, %#llx\n", slb_vsid, slb_esid); @@ -398,11 +412,29 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr) void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu) { - get_paca()->kvm_slb_max = 1; - get_paca()->kvm_slb[0].esid = 0; + to_svcpu(vcpu)->slb_max = 1; + to_svcpu(vcpu)->slb[0].esid = 0; } void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu) { kvmppc_mmu_pte_flush(vcpu, 0, 0); + __destroy_context(to_book3s(vcpu)->context_id); +} + +int kvmppc_mmu_init(struct kvm_vcpu *vcpu) +{ + struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); + int err; + + err = __init_new_context(); + if (err < 0) + return -1; + vcpu3s->context_id = err; + + vcpu3s->vsid_max = ((vcpu3s->context_id + 1) << USER_ESID_BITS) - 1; + vcpu3s->vsid_first = vcpu3s->context_id << USER_ESID_BITS; + vcpu3s->vsid_next = vcpu3s->vsid_first; + + return 0; } diff --git a/arch/powerpc/kvm/book3s_64_slb.S b/arch/powerpc/kvm/book3s_64_slb.S index 35b762722187..04e7d3bbfe8b 100644 --- a/arch/powerpc/kvm/book3s_64_slb.S +++ b/arch/powerpc/kvm/book3s_64_slb.S @@ -44,8 +44,7 @@ slb_exit_skip_ ## num: * * *****************************************************************************/ -.global kvmppc_handler_trampoline_enter -kvmppc_handler_trampoline_enter: +.macro LOAD_GUEST_SEGMENTS /* Required state: * @@ -53,20 +52,14 @@ kvmppc_handler_trampoline_enter: * R13 = PACA * R1 = host R1 * R2 = host R2 - * R9 = guest IP - * R10 = guest MSR - * all other GPRS = free - * PACA[KVM_CR] = guest CR - * PACA[KVM_XER] = guest XER + * R3 = shadow vcpu + * all other volatile GPRS = free + * SVCPU[CR] = guest CR + * SVCPU[XER] = guest XER + * SVCPU[CTR] = guest CTR + * SVCPU[LR] = guest LR */ - mtsrr0 r9 - mtsrr1 r10 - - /* Activate guest mode, so faults get handled by KVM */ - li r11, KVM_GUEST_MODE_GUEST - stb r11, PACA_KVM_IN_GUEST(r13) - /* Remove LPAR shadow entries */ #if SLB_NUM_BOLTED == 3 @@ -101,14 +94,14 @@ kvmppc_handler_trampoline_enter: /* Fill SLB with our shadow */ - lbz r12, PACA_KVM_SLB_MAX(r13) + lbz r12, SVCPU_SLB_MAX(r3) mulli r12, r12, 16 - addi r12, r12, PACA_KVM_SLB - add r12, r12, r13 + addi r12, r12, SVCPU_SLB + add r12, r12, r3 /* for (r11 = kvm_slb; r11 < kvm_slb + kvm_slb_size; r11+=slb_entry) */ - li r11, PACA_KVM_SLB - add r11, r11, r13 + li r11, SVCPU_SLB + add r11, r11, r3 slb_loop_enter: @@ -127,34 +120,7 @@ slb_loop_enter_skip: slb_do_enter: - /* Enter guest */ - - ld r0, (PACA_KVM_R0)(r13) - ld r1, (PACA_KVM_R1)(r13) - ld r2, (PACA_KVM_R2)(r13) - ld r3, (PACA_KVM_R3)(r13) - ld r4, (PACA_KVM_R4)(r13) - ld r5, (PACA_KVM_R5)(r13) - ld r6, (PACA_KVM_R6)(r13) - ld r7, (PACA_KVM_R7)(r13) - ld r8, (PACA_KVM_R8)(r13) - ld r9, (PACA_KVM_R9)(r13) - ld r10, (PACA_KVM_R10)(r13) - ld r12, (PACA_KVM_R12)(r13) - - lwz r11, (PACA_KVM_CR)(r13) - mtcr r11 - - ld r11, (PACA_KVM_XER)(r13) - mtxer r11 - - ld r11, (PACA_KVM_R11)(r13) - ld r13, (PACA_KVM_R13)(r13) - - RFI -kvmppc_handler_trampoline_enter_end: - - +.endm /****************************************************************************** * * @@ -162,99 +128,22 @@ kvmppc_handler_trampoline_enter_end: * * *****************************************************************************/ -.global kvmppc_handler_trampoline_exit -kvmppc_handler_trampoline_exit: +.macro LOAD_HOST_SEGMENTS /* Register usage at this point: * - * SPRG_SCRATCH0 = guest R13 - * R12 = exit handler id - * R13 = PACA - * PACA.KVM.SCRATCH0 = guest R12 - * PACA.KVM.SCRATCH1 = guest CR + * R1 = host R1 + * R2 = host R2 + * R12 = exit handler id + * R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64] + * SVCPU.* = guest * + * SVCPU[CR] = guest CR + * SVCPU[XER] = guest XER + * SVCPU[CTR] = guest CTR + * SVCPU[LR] = guest LR * */ - /* Save registers */ - - std r0, PACA_KVM_R0(r13) - std r1, PACA_KVM_R1(r13) - std r2, PACA_KVM_R2(r13) - std r3, PACA_KVM_R3(r13) - std r4, PACA_KVM_R4(r13) - std r5, PACA_KVM_R5(r13) - std r6, PACA_KVM_R6(r13) - std r7, PACA_KVM_R7(r13) - std r8, PACA_KVM_R8(r13) - std r9, PACA_KVM_R9(r13) - std r10, PACA_KVM_R10(r13) - std r11, PACA_KVM_R11(r13) - - /* Restore R1/R2 so we can handle faults */ - ld r1, PACA_KVM_HOST_R1(r13) - ld r2, PACA_KVM_HOST_R2(r13) - - /* Save guest PC and MSR in GPRs */ - mfsrr0 r3 - mfsrr1 r4 - - /* Get scratch'ed off registers */ - mfspr r9, SPRN_SPRG_SCRATCH0 - std r9, PACA_KVM_R13(r13) - - ld r8, PACA_KVM_SCRATCH0(r13) - std r8, PACA_KVM_R12(r13) - - lwz r7, PACA_KVM_SCRATCH1(r13) - stw r7, PACA_KVM_CR(r13) - - /* Save more register state */ - - mfxer r6 - stw r6, PACA_KVM_XER(r13) - - mfdar r5 - mfdsisr r6 - - /* - * In order for us to easily get the last instruction, - * we got the #vmexit at, we exploit the fact that the - * virtual layout is still the same here, so we can just - * ld from the guest's PC address - */ - - /* We only load the last instruction when it's safe */ - cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE - beq ld_last_inst - cmpwi r12, BOOK3S_INTERRUPT_PROGRAM - beq ld_last_inst - - b no_ld_last_inst - -ld_last_inst: - /* Save off the guest instruction we're at */ - - /* Set guest mode to 'jump over instruction' so if lwz faults - * we'll just continue at the next IP. */ - li r9, KVM_GUEST_MODE_SKIP - stb r9, PACA_KVM_IN_GUEST(r13) - - /* 1) enable paging for data */ - mfmsr r9 - ori r11, r9, MSR_DR /* Enable paging for data */ - mtmsr r11 - /* 2) fetch the instruction */ - li r0, KVM_INST_FETCH_FAILED /* In case lwz faults */ - lwz r0, 0(r3) - /* 3) disable paging again */ - mtmsr r9 - -no_ld_last_inst: - - /* Unset guest mode */ - li r9, KVM_GUEST_MODE_NONE - stb r9, PACA_KVM_IN_GUEST(r13) - /* Restore bolted entries from the shadow and fix it along the way */ /* We don't store anything in entry 0, so we don't need to take care of it */ @@ -275,28 +164,4 @@ no_ld_last_inst: slb_do_exit: - /* Register usage at this point: - * - * R0 = guest last inst - * R1 = host R1 - * R2 = host R2 - * R3 = guest PC - * R4 = guest MSR - * R5 = guest DAR - * R6 = guest DSISR - * R12 = exit handler id - * R13 = PACA - * PACA.KVM.* = guest * - * - */ - - /* RFI into the highmem handler */ - mfmsr r7 - ori r7, r7, MSR_IR|MSR_DR|MSR_RI /* Enable paging */ - mtsrr1 r7 - ld r8, PACA_KVM_VMHANDLER(r13) /* Highmem handler address */ - mtsrr0 r8 - - RFI -kvmppc_handler_trampoline_exit_end: - +.endm diff --git a/arch/powerpc/kvm/book3s_64_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 2b0ee7e040c9..c85f906038ce 100644 --- a/arch/powerpc/kvm/book3s_64_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -28,13 +28,16 @@ #define OP_31_XOP_MFMSR 83 #define OP_31_XOP_MTMSR 146 #define OP_31_XOP_MTMSRD 178 +#define OP_31_XOP_MTSR 210 #define OP_31_XOP_MTSRIN 242 #define OP_31_XOP_TLBIEL 274 #define OP_31_XOP_TLBIE 306 #define OP_31_XOP_SLBMTE 402 #define OP_31_XOP_SLBIE 434 #define OP_31_XOP_SLBIA 498 +#define OP_31_XOP_MFSR 595 #define OP_31_XOP_MFSRIN 659 +#define OP_31_XOP_DCBA 758 #define OP_31_XOP_SLBMFEV 851 #define OP_31_XOP_EIOIO 854 #define OP_31_XOP_SLBMFEE 915 @@ -42,6 +45,24 @@ /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 +#define OP_LFS 48 +#define OP_LFD 50 +#define OP_STFS 52 +#define OP_STFD 54 + +#define SPRN_GQR0 912 +#define SPRN_GQR1 913 +#define SPRN_GQR2 914 +#define SPRN_GQR3 915 +#define SPRN_GQR4 916 +#define SPRN_GQR5 917 +#define SPRN_GQR6 918 +#define SPRN_GQR7 919 + +/* Book3S_32 defines mfsrin(v) - but that messes up our abstract + * function pointers, so let's just disable the define. */ +#undef mfsrin + int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int inst, int *advance) { @@ -52,7 +73,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, switch (get_xop(inst)) { case OP_19_XOP_RFID: case OP_19_XOP_RFI: - vcpu->arch.pc = vcpu->arch.srr0; + kvmppc_set_pc(vcpu, vcpu->arch.srr0); kvmppc_set_msr(vcpu, vcpu->arch.srr1); *advance = 0; break; @@ -80,6 +101,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, case OP_31_XOP_MTMSR: kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst))); break; + case OP_31_XOP_MFSR: + { + int srnum; + + srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32); + if (vcpu->arch.mmu.mfsrin) { + u32 sr; + sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); + kvmppc_set_gpr(vcpu, get_rt(inst), sr); + } + break; + } case OP_31_XOP_MFSRIN: { int srnum; @@ -92,6 +125,11 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, } break; } + case OP_31_XOP_MTSR: + vcpu->arch.mmu.mtsrin(vcpu, + (inst >> 16) & 0xf, + kvmppc_get_gpr(vcpu, get_rs(inst))); + break; case OP_31_XOP_MTSRIN: vcpu->arch.mmu.mtsrin(vcpu, (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf, @@ -150,12 +188,17 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, kvmppc_set_gpr(vcpu, get_rt(inst), t); } break; + case OP_31_XOP_DCBA: + /* Gets treated as NOP */ + break; case OP_31_XOP_DCBZ: { ulong rb = kvmppc_get_gpr(vcpu, get_rb(inst)); ulong ra = 0; - ulong addr; + ulong addr, vaddr; u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + u32 dsisr; + int r; if (get_ra(inst)) ra = kvmppc_get_gpr(vcpu, get_ra(inst)); @@ -163,15 +206,25 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, addr = (ra + rb) & ~31ULL; if (!(vcpu->arch.msr & MSR_SF)) addr &= 0xffffffff; + vaddr = addr; + + r = kvmppc_st(vcpu, &addr, 32, zeros, true); + if ((r == -ENOENT) || (r == -EPERM)) { + *advance = 0; + vcpu->arch.dear = vaddr; + to_svcpu(vcpu)->fault_dar = vaddr; + + dsisr = DSISR_ISSTORE; + if (r == -ENOENT) + dsisr |= DSISR_NOHPTE; + else if (r == -EPERM) + dsisr |= DSISR_PROTFAULT; + + to_book3s(vcpu)->dsisr = dsisr; + to_svcpu(vcpu)->fault_dsisr = dsisr; - if (kvmppc_st(vcpu, addr, 32, zeros)) { - vcpu->arch.dear = addr; - vcpu->arch.fault_dear = addr; - to_book3s(vcpu)->dsisr = DSISR_PROTFAULT | - DSISR_ISSTORE; kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE); - kvmppc_mmu_pte_flush(vcpu, addr, ~0xFFFULL); } break; @@ -184,6 +237,9 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, emulated = EMULATE_FAIL; } + if (emulated == EMULATE_FAIL) + emulated = kvmppc_emulate_paired_single(run, vcpu); + return emulated; } @@ -207,6 +263,34 @@ void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper, } } +static u32 kvmppc_read_bat(struct kvm_vcpu *vcpu, int sprn) +{ + struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); + struct kvmppc_bat *bat; + + switch (sprn) { + case SPRN_IBAT0U ... SPRN_IBAT3L: + bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2]; + break; + case SPRN_IBAT4U ... SPRN_IBAT7L: + bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)]; + break; + case SPRN_DBAT0U ... SPRN_DBAT3L: + bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2]; + break; + case SPRN_DBAT4U ... SPRN_DBAT7L: + bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)]; + break; + default: + BUG(); + } + + if (sprn % 2) + return bat->raw >> 32; + else + return bat->raw; +} + static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u32 val) { struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); @@ -217,13 +301,13 @@ static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u32 val) bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2]; break; case SPRN_IBAT4U ... SPRN_IBAT7L: - bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT4U) / 2]; + bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)]; break; case SPRN_DBAT0U ... SPRN_DBAT3L: bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2]; break; case SPRN_DBAT4U ... SPRN_DBAT7L: - bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT4U) / 2]; + bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)]; break; default: BUG(); @@ -258,6 +342,7 @@ int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) /* BAT writes happen so rarely that we're ok to flush * everything here */ kvmppc_mmu_pte_flush(vcpu, 0, 0); + kvmppc_mmu_flush_segments(vcpu); break; case SPRN_HID0: to_book3s(vcpu)->hid[0] = spr_val; @@ -268,7 +353,32 @@ int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) case SPRN_HID2: to_book3s(vcpu)->hid[2] = spr_val; break; + case SPRN_HID2_GEKKO: + to_book3s(vcpu)->hid[2] = spr_val; + /* HID2.PSE controls paired single on gekko */ + switch (vcpu->arch.pvr) { + case 0x00080200: /* lonestar 2.0 */ + case 0x00088202: /* lonestar 2.2 */ + case 0x70000100: /* gekko 1.0 */ + case 0x00080100: /* gekko 2.0 */ + case 0x00083203: /* gekko 2.3a */ + case 0x00083213: /* gekko 2.3b */ + case 0x00083204: /* gekko 2.4 */ + case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ + case 0x00087200: /* broadway */ + if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) { + /* Native paired singles */ + } else if (spr_val & (1 << 29)) { /* HID2.PSE */ + vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE; + kvmppc_giveup_ext(vcpu, MSR_FP); + } else { + vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE; + } + break; + } + break; case SPRN_HID4: + case SPRN_HID4_GEKKO: to_book3s(vcpu)->hid[4] = spr_val; break; case SPRN_HID5: @@ -278,12 +388,30 @@ int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) (mfmsr() & MSR_HV)) vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; break; + case SPRN_GQR0: + case SPRN_GQR1: + case SPRN_GQR2: + case SPRN_GQR3: + case SPRN_GQR4: + case SPRN_GQR5: + case SPRN_GQR6: + case SPRN_GQR7: + to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val; + break; case SPRN_ICTC: case SPRN_THRM1: case SPRN_THRM2: case SPRN_THRM3: case SPRN_CTRLF: case SPRN_CTRLT: + case SPRN_L2CR: + case SPRN_MMCR0_GEKKO: + case SPRN_MMCR1_GEKKO: + case SPRN_PMC1_GEKKO: + case SPRN_PMC2_GEKKO: + case SPRN_PMC3_GEKKO: + case SPRN_PMC4_GEKKO: + case SPRN_WPAR_GEKKO: break; default: printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn); @@ -301,6 +429,12 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) int emulated = EMULATE_DONE; switch (sprn) { + case SPRN_IBAT0U ... SPRN_IBAT3L: + case SPRN_IBAT4U ... SPRN_IBAT7L: + case SPRN_DBAT0U ... SPRN_DBAT3L: + case SPRN_DBAT4U ... SPRN_DBAT7L: + kvmppc_set_gpr(vcpu, rt, kvmppc_read_bat(vcpu, sprn)); + break; case SPRN_SDR1: kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->sdr1); break; @@ -320,19 +454,40 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[1]); break; case SPRN_HID2: + case SPRN_HID2_GEKKO: kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[2]); break; case SPRN_HID4: + case SPRN_HID4_GEKKO: kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[4]); break; case SPRN_HID5: kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[5]); break; + case SPRN_GQR0: + case SPRN_GQR1: + case SPRN_GQR2: + case SPRN_GQR3: + case SPRN_GQR4: + case SPRN_GQR5: + case SPRN_GQR6: + case SPRN_GQR7: + kvmppc_set_gpr(vcpu, rt, + to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]); + break; case SPRN_THRM1: case SPRN_THRM2: case SPRN_THRM3: case SPRN_CTRLF: case SPRN_CTRLT: + case SPRN_L2CR: + case SPRN_MMCR0_GEKKO: + case SPRN_MMCR1_GEKKO: + case SPRN_PMC1_GEKKO: + case SPRN_PMC2_GEKKO: + case SPRN_PMC3_GEKKO: + case SPRN_PMC4_GEKKO: + case SPRN_WPAR_GEKKO: kvmppc_set_gpr(vcpu, rt, 0); break; default: @@ -346,3 +501,73 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) return emulated; } +u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst) +{ + u32 dsisr = 0; + + /* + * This is what the spec says about DSISR bits (not mentioned = 0): + * + * 12:13 [DS] Set to bits 30:31 + * 15:16 [X] Set to bits 29:30 + * 17 [X] Set to bit 25 + * [D/DS] Set to bit 5 + * 18:21 [X] Set to bits 21:24 + * [D/DS] Set to bits 1:4 + * 22:26 Set to bits 6:10 (RT/RS/FRT/FRS) + * 27:31 Set to bits 11:15 (RA) + */ + + switch (get_op(inst)) { + /* D-form */ + case OP_LFS: + case OP_LFD: + case OP_STFD: + case OP_STFS: + dsisr |= (inst >> 12) & 0x4000; /* bit 17 */ + dsisr |= (inst >> 17) & 0x3c00; /* bits 18:21 */ + break; + /* X-form */ + case 31: + dsisr |= (inst << 14) & 0x18000; /* bits 15:16 */ + dsisr |= (inst << 8) & 0x04000; /* bit 17 */ + dsisr |= (inst << 3) & 0x03c00; /* bits 18:21 */ + break; + default: + printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); + break; + } + + dsisr |= (inst >> 16) & 0x03ff; /* bits 22:31 */ + + return dsisr; +} + +ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst) +{ + ulong dar = 0; + ulong ra; + + switch (get_op(inst)) { + case OP_LFS: + case OP_LFD: + case OP_STFD: + case OP_STFS: + ra = get_ra(inst); + if (ra) + dar = kvmppc_get_gpr(vcpu, ra); + dar += (s32)((s16)inst); + break; + case 31: + ra = get_ra(inst); + if (ra) + dar = kvmppc_get_gpr(vcpu, ra); + dar += kvmppc_get_gpr(vcpu, get_rb(inst)); + break; + default: + printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); + break; + } + + return dar; +} diff --git a/arch/powerpc/kvm/book3s_64_exports.c b/arch/powerpc/kvm/book3s_exports.c index 1dd5a1ddfd0d..1dd5a1ddfd0d 100644 --- a/arch/powerpc/kvm/book3s_64_exports.c +++ b/arch/powerpc/kvm/book3s_exports.c diff --git a/arch/powerpc/kvm/book3s_64_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S index c1584d0cbce8..2f0bc928b08a 100644 --- a/arch/powerpc/kvm/book3s_64_interrupts.S +++ b/arch/powerpc/kvm/book3s_interrupts.S @@ -24,36 +24,56 @@ #include <asm/asm-offsets.h> #include <asm/exception-64s.h> -#define KVMPPC_HANDLE_EXIT .kvmppc_handle_exit -#define ULONG_SIZE 8 -#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) +#if defined(CONFIG_PPC_BOOK3S_64) -.macro DISABLE_INTERRUPTS - mfmsr r0 - rldicl r0,r0,48,1 - rotldi r0,r0,16 - mtmsrd r0,1 -.endm +#define ULONG_SIZE 8 +#define FUNC(name) GLUE(.,name) +#define GET_SHADOW_VCPU(reg) \ + addi reg, r13, PACA_KVM_SVCPU + +#define DISABLE_INTERRUPTS \ + mfmsr r0; \ + rldicl r0,r0,48,1; \ + rotldi r0,r0,16; \ + mtmsrd r0,1; \ + +#elif defined(CONFIG_PPC_BOOK3S_32) + +#define ULONG_SIZE 4 +#define FUNC(name) name + +#define GET_SHADOW_VCPU(reg) \ + lwz reg, (THREAD + THREAD_KVM_SVCPU)(r2) + +#define DISABLE_INTERRUPTS \ + mfmsr r0; \ + rlwinm r0,r0,0,17,15; \ + mtmsr r0; \ + +#endif /* CONFIG_PPC_BOOK3S_XX */ + + +#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) #define VCPU_LOAD_NVGPRS(vcpu) \ - ld r14, VCPU_GPR(r14)(vcpu); \ - ld r15, VCPU_GPR(r15)(vcpu); \ - ld r16, VCPU_GPR(r16)(vcpu); \ - ld r17, VCPU_GPR(r17)(vcpu); \ - ld r18, VCPU_GPR(r18)(vcpu); \ - ld r19, VCPU_GPR(r19)(vcpu); \ - ld r20, VCPU_GPR(r20)(vcpu); \ - ld r21, VCPU_GPR(r21)(vcpu); \ - ld r22, VCPU_GPR(r22)(vcpu); \ - ld r23, VCPU_GPR(r23)(vcpu); \ - ld r24, VCPU_GPR(r24)(vcpu); \ - ld r25, VCPU_GPR(r25)(vcpu); \ - ld r26, VCPU_GPR(r26)(vcpu); \ - ld r27, VCPU_GPR(r27)(vcpu); \ - ld r28, VCPU_GPR(r28)(vcpu); \ - ld r29, VCPU_GPR(r29)(vcpu); \ - ld r30, VCPU_GPR(r30)(vcpu); \ - ld r31, VCPU_GPR(r31)(vcpu); \ + PPC_LL r14, VCPU_GPR(r14)(vcpu); \ + PPC_LL r15, VCPU_GPR(r15)(vcpu); \ + PPC_LL r16, VCPU_GPR(r16)(vcpu); \ + PPC_LL r17, VCPU_GPR(r17)(vcpu); \ + PPC_LL r18, VCPU_GPR(r18)(vcpu); \ + PPC_LL r19, VCPU_GPR(r19)(vcpu); \ + PPC_LL r20, VCPU_GPR(r20)(vcpu); \ + PPC_LL r21, VCPU_GPR(r21)(vcpu); \ + PPC_LL r22, VCPU_GPR(r22)(vcpu); \ + PPC_LL r23, VCPU_GPR(r23)(vcpu); \ + PPC_LL r24, VCPU_GPR(r24)(vcpu); \ + PPC_LL r25, VCPU_GPR(r25)(vcpu); \ + PPC_LL r26, VCPU_GPR(r26)(vcpu); \ + PPC_LL r27, VCPU_GPR(r27)(vcpu); \ + PPC_LL r28, VCPU_GPR(r28)(vcpu); \ + PPC_LL r29, VCPU_GPR(r29)(vcpu); \ + PPC_LL r30, VCPU_GPR(r30)(vcpu); \ + PPC_LL r31, VCPU_GPR(r31)(vcpu); \ /***************************************************************************** * * @@ -69,11 +89,11 @@ _GLOBAL(__kvmppc_vcpu_entry) kvm_start_entry: /* Write correct stack frame */ - mflr r0 - std r0,16(r1) + mflr r0 + PPC_STL r0,PPC_LR_STKOFF(r1) /* Save host state to the stack */ - stdu r1, -SWITCH_FRAME_SIZE(r1) + PPC_STLU r1, -SWITCH_FRAME_SIZE(r1) /* Save r3 (kvm_run) and r4 (vcpu) */ SAVE_2GPRS(3, r1) @@ -82,33 +102,28 @@ kvm_start_entry: SAVE_NVGPRS(r1) /* Save LR */ - std r0, _LINK(r1) + PPC_STL r0, _LINK(r1) /* Load non-volatile guest state from the vcpu */ VCPU_LOAD_NVGPRS(r4) + GET_SHADOW_VCPU(r5) + /* Save R1/R2 in the PACA */ - std r1, PACA_KVM_HOST_R1(r13) - std r2, PACA_KVM_HOST_R2(r13) + PPC_STL r1, SVCPU_HOST_R1(r5) + PPC_STL r2, SVCPU_HOST_R2(r5) /* XXX swap in/out on load? */ - ld r3, VCPU_HIGHMEM_HANDLER(r4) - std r3, PACA_KVM_VMHANDLER(r13) + PPC_LL r3, VCPU_HIGHMEM_HANDLER(r4) + PPC_STL r3, SVCPU_VMHANDLER(r5) kvm_start_lightweight: - ld r9, VCPU_PC(r4) /* r9 = vcpu->arch.pc */ - ld r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */ - - /* Load some guest state in the respective registers */ - ld r5, VCPU_CTR(r4) /* r5 = vcpu->arch.ctr */ - /* will be swapped in by rmcall */ - - ld r3, VCPU_LR(r4) /* r3 = vcpu->arch.lr */ - mtlr r3 /* LR = r3 */ + PPC_LL r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */ DISABLE_INTERRUPTS +#ifdef CONFIG_PPC_BOOK3S_64 /* Some guests may need to have dcbz set to 32 byte length. * * Usually we ensure that by patching the guest's instructions @@ -118,7 +133,7 @@ kvm_start_lightweight: * because that's a lot faster. */ - ld r3, VCPU_HFLAGS(r4) + PPC_LL r3, VCPU_HFLAGS(r4) rldicl. r3, r3, 0, 63 /* CR = ((r3 & 1) == 0) */ beq no_dcbz32_on @@ -128,13 +143,15 @@ kvm_start_lightweight: no_dcbz32_on: - ld r6, VCPU_RMCALL(r4) +#endif /* CONFIG_PPC_BOOK3S_64 */ + + PPC_LL r6, VCPU_RMCALL(r4) mtctr r6 - ld r3, VCPU_TRAMPOLINE_ENTER(r4) + PPC_LL r3, VCPU_TRAMPOLINE_ENTER(r4) LOAD_REG_IMMEDIATE(r4, MSR_KERNEL & ~(MSR_IR | MSR_DR)) - /* Jump to SLB patching handlder and into our guest */ + /* Jump to segment patching handler and into our guest */ bctr /* @@ -149,31 +166,20 @@ kvmppc_handler_highmem: /* * Register usage at this point: * - * R0 = guest last inst - * R1 = host R1 - * R2 = host R2 - * R3 = guest PC - * R4 = guest MSR - * R5 = guest DAR - * R6 = guest DSISR - * R13 = PACA - * PACA.KVM.* = guest * + * R1 = host R1 + * R2 = host R2 + * R12 = exit handler id + * R13 = PACA + * SVCPU.* = guest * * */ /* R7 = vcpu */ - ld r7, GPR4(r1) + PPC_LL r7, GPR4(r1) - /* Now save the guest state */ +#ifdef CONFIG_PPC_BOOK3S_64 - stw r0, VCPU_LAST_INST(r7) - - std r3, VCPU_PC(r7) - std r4, VCPU_SHADOW_SRR1(r7) - std r5, VCPU_FAULT_DEAR(r7) - std r6, VCPU_FAULT_DSISR(r7) - - ld r5, VCPU_HFLAGS(r7) + PPC_LL r5, VCPU_HFLAGS(r7) rldicl. r5, r5, 0, 63 /* CR = ((r5 & 1) == 0) */ beq no_dcbz32_off @@ -184,35 +190,29 @@ kvmppc_handler_highmem: no_dcbz32_off: - std r14, VCPU_GPR(r14)(r7) - std r15, VCPU_GPR(r15)(r7) - std r16, VCPU_GPR(r16)(r7) - std r17, VCPU_GPR(r17)(r7) - std r18, VCPU_GPR(r18)(r7) - std r19, VCPU_GPR(r19)(r7) - std r20, VCPU_GPR(r20)(r7) - std r21, VCPU_GPR(r21)(r7) - std r22, VCPU_GPR(r22)(r7) - std r23, VCPU_GPR(r23)(r7) - std r24, VCPU_GPR(r24)(r7) - std r25, VCPU_GPR(r25)(r7) - std r26, VCPU_GPR(r26)(r7) - std r27, VCPU_GPR(r27)(r7) - std r28, VCPU_GPR(r28)(r7) - std r29, VCPU_GPR(r29)(r7) - std r30, VCPU_GPR(r30)(r7) - std r31, VCPU_GPR(r31)(r7) - - /* Save guest CTR */ - mfctr r5 - std r5, VCPU_CTR(r7) - - /* Save guest LR */ - mflr r5 - std r5, VCPU_LR(r7) +#endif /* CONFIG_PPC_BOOK3S_64 */ + + PPC_STL r14, VCPU_GPR(r14)(r7) + PPC_STL r15, VCPU_GPR(r15)(r7) + PPC_STL r16, VCPU_GPR(r16)(r7) + PPC_STL r17, VCPU_GPR(r17)(r7) + PPC_STL r18, VCPU_GPR(r18)(r7) + PPC_STL r19, VCPU_GPR(r19)(r7) + PPC_STL r20, VCPU_GPR(r20)(r7) + PPC_STL r21, VCPU_GPR(r21)(r7) + PPC_STL r22, VCPU_GPR(r22)(r7) + PPC_STL r23, VCPU_GPR(r23)(r7) + PPC_STL r24, VCPU_GPR(r24)(r7) + PPC_STL r25, VCPU_GPR(r25)(r7) + PPC_STL r26, VCPU_GPR(r26)(r7) + PPC_STL r27, VCPU_GPR(r27)(r7) + PPC_STL r28, VCPU_GPR(r28)(r7) + PPC_STL r29, VCPU_GPR(r29)(r7) + PPC_STL r30, VCPU_GPR(r30)(r7) + PPC_STL r31, VCPU_GPR(r31)(r7) /* Restore host msr -> SRR1 */ - ld r6, VCPU_HOST_MSR(r7) + PPC_LL r6, VCPU_HOST_MSR(r7) /* * For some interrupts, we need to call the real Linux @@ -228,9 +228,12 @@ no_dcbz32_off: beq call_linux_handler cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER beq call_linux_handler + cmpwi r12, BOOK3S_INTERRUPT_PERFMON + beq call_linux_handler /* Back to EE=1 */ mtmsr r6 + sync b kvm_return_point call_linux_handler: @@ -249,14 +252,14 @@ call_linux_handler: */ /* Restore host IP -> SRR0 */ - ld r5, VCPU_HOST_RETIP(r7) + PPC_LL r5, VCPU_HOST_RETIP(r7) /* XXX Better move to a safe function? * What if we get an HTAB flush in between mtsrr0 and mtsrr1? */ mtlr r12 - ld r4, VCPU_TRAMPOLINE_LOWMEM(r7) + PPC_LL r4, VCPU_TRAMPOLINE_LOWMEM(r7) mtsrr0 r4 LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)) mtsrr1 r3 @@ -274,7 +277,7 @@ kvm_return_point: /* Restore r3 (kvm_run) and r4 (vcpu) */ REST_2GPRS(3, r1) - bl KVMPPC_HANDLE_EXIT + bl FUNC(kvmppc_handle_exit) /* If RESUME_GUEST, get back in the loop */ cmpwi r3, RESUME_GUEST @@ -285,7 +288,7 @@ kvm_return_point: kvm_exit_loop: - ld r4, _LINK(r1) + PPC_LL r4, _LINK(r1) mtlr r4 /* Restore non-volatile host registers (r14 - r31) */ @@ -296,8 +299,8 @@ kvm_exit_loop: kvm_loop_heavyweight: - ld r4, _LINK(r1) - std r4, (16 + SWITCH_FRAME_SIZE)(r1) + PPC_LL r4, _LINK(r1) + PPC_STL r4, (PPC_LR_STKOFF + SWITCH_FRAME_SIZE)(r1) /* Load vcpu and cpu_run */ REST_2GPRS(3, r1) @@ -315,4 +318,3 @@ kvm_loop_lightweight: /* Jump back into the beginning of this function */ b kvm_start_lightweight - diff --git a/arch/powerpc/kvm/book3s_paired_singles.c b/arch/powerpc/kvm/book3s_paired_singles.c new file mode 100644 index 000000000000..a9f66abafcb3 --- /dev/null +++ b/arch/powerpc/kvm/book3s_paired_singles.c @@ -0,0 +1,1289 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright Novell Inc 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +#include <asm/kvm.h> +#include <asm/kvm_ppc.h> +#include <asm/disassemble.h> +#include <asm/kvm_book3s.h> +#include <asm/kvm_fpu.h> +#include <asm/reg.h> +#include <asm/cacheflush.h> +#include <linux/vmalloc.h> + +/* #define DEBUG */ + +#ifdef DEBUG +#define dprintk printk +#else +#define dprintk(...) do { } while(0); +#endif + +#define OP_LFS 48 +#define OP_LFSU 49 +#define OP_LFD 50 +#define OP_LFDU 51 +#define OP_STFS 52 +#define OP_STFSU 53 +#define OP_STFD 54 +#define OP_STFDU 55 +#define OP_PSQ_L 56 +#define OP_PSQ_LU 57 +#define OP_PSQ_ST 60 +#define OP_PSQ_STU 61 + +#define OP_31_LFSX 535 +#define OP_31_LFSUX 567 +#define OP_31_LFDX 599 +#define OP_31_LFDUX 631 +#define OP_31_STFSX 663 +#define OP_31_STFSUX 695 +#define OP_31_STFX 727 +#define OP_31_STFUX 759 +#define OP_31_LWIZX 887 +#define OP_31_STFIWX 983 + +#define OP_59_FADDS 21 +#define OP_59_FSUBS 20 +#define OP_59_FSQRTS 22 +#define OP_59_FDIVS 18 +#define OP_59_FRES 24 +#define OP_59_FMULS 25 +#define OP_59_FRSQRTES 26 +#define OP_59_FMSUBS 28 +#define OP_59_FMADDS 29 +#define OP_59_FNMSUBS 30 +#define OP_59_FNMADDS 31 + +#define OP_63_FCMPU 0 +#define OP_63_FCPSGN 8 +#define OP_63_FRSP 12 +#define OP_63_FCTIW 14 +#define OP_63_FCTIWZ 15 +#define OP_63_FDIV 18 +#define OP_63_FADD 21 +#define OP_63_FSQRT 22 +#define OP_63_FSEL 23 +#define OP_63_FRE 24 +#define OP_63_FMUL 25 +#define OP_63_FRSQRTE 26 +#define OP_63_FMSUB 28 +#define OP_63_FMADD 29 +#define OP_63_FNMSUB 30 +#define OP_63_FNMADD 31 +#define OP_63_FCMPO 32 +#define OP_63_MTFSB1 38 // XXX +#define OP_63_FSUB 20 +#define OP_63_FNEG 40 +#define OP_63_MCRFS 64 +#define OP_63_MTFSB0 70 +#define OP_63_FMR 72 +#define OP_63_MTFSFI 134 +#define OP_63_FABS 264 +#define OP_63_MFFS 583 +#define OP_63_MTFSF 711 + +#define OP_4X_PS_CMPU0 0 +#define OP_4X_PSQ_LX 6 +#define OP_4XW_PSQ_STX 7 +#define OP_4A_PS_SUM0 10 +#define OP_4A_PS_SUM1 11 +#define OP_4A_PS_MULS0 12 +#define OP_4A_PS_MULS1 13 +#define OP_4A_PS_MADDS0 14 +#define OP_4A_PS_MADDS1 15 +#define OP_4A_PS_DIV 18 +#define OP_4A_PS_SUB 20 +#define OP_4A_PS_ADD 21 +#define OP_4A_PS_SEL 23 +#define OP_4A_PS_RES 24 +#define OP_4A_PS_MUL 25 +#define OP_4A_PS_RSQRTE 26 +#define OP_4A_PS_MSUB 28 +#define OP_4A_PS_MADD 29 +#define OP_4A_PS_NMSUB 30 +#define OP_4A_PS_NMADD 31 +#define OP_4X_PS_CMPO0 32 +#define OP_4X_PSQ_LUX 38 +#define OP_4XW_PSQ_STUX 39 +#define OP_4X_PS_NEG 40 +#define OP_4X_PS_CMPU1 64 +#define OP_4X_PS_MR 72 +#define OP_4X_PS_CMPO1 96 +#define OP_4X_PS_NABS 136 +#define OP_4X_PS_ABS 264 +#define OP_4X_PS_MERGE00 528 +#define OP_4X_PS_MERGE01 560 +#define OP_4X_PS_MERGE10 592 +#define OP_4X_PS_MERGE11 624 + +#define SCALAR_NONE 0 +#define SCALAR_HIGH (1 << 0) +#define SCALAR_LOW (1 << 1) +#define SCALAR_NO_PS0 (1 << 2) +#define SCALAR_NO_PS1 (1 << 3) + +#define GQR_ST_TYPE_MASK 0x00000007 +#define GQR_ST_TYPE_SHIFT 0 +#define GQR_ST_SCALE_MASK 0x00003f00 +#define GQR_ST_SCALE_SHIFT 8 +#define GQR_LD_TYPE_MASK 0x00070000 +#define GQR_LD_TYPE_SHIFT 16 +#define GQR_LD_SCALE_MASK 0x3f000000 +#define GQR_LD_SCALE_SHIFT 24 + +#define GQR_QUANTIZE_FLOAT 0 +#define GQR_QUANTIZE_U8 4 +#define GQR_QUANTIZE_U16 5 +#define GQR_QUANTIZE_S8 6 +#define GQR_QUANTIZE_S16 7 + +#define FPU_LS_SINGLE 0 +#define FPU_LS_DOUBLE 1 +#define FPU_LS_SINGLE_LOW 2 + +static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt) +{ + struct thread_struct t; + + t.fpscr.val = vcpu->arch.fpscr; + cvt_df((double*)&vcpu->arch.fpr[rt], (float*)&vcpu->arch.qpr[rt], &t); +} + +static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store) +{ + u64 dsisr; + + vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 33, 36, 0); + vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 42, 47, 0); + vcpu->arch.dear = eaddr; + /* Page Fault */ + dsisr = kvmppc_set_field(0, 33, 33, 1); + if (is_store) + to_book3s(vcpu)->dsisr = kvmppc_set_field(dsisr, 38, 38, 1); + kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE); +} + +static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu, + int rs, ulong addr, int ls_type) +{ + int emulated = EMULATE_FAIL; + struct thread_struct t; + int r; + char tmp[8]; + int len = sizeof(u32); + + if (ls_type == FPU_LS_DOUBLE) + len = sizeof(u64); + + t.fpscr.val = vcpu->arch.fpscr; + + /* read from memory */ + r = kvmppc_ld(vcpu, &addr, len, tmp, true); + vcpu->arch.paddr_accessed = addr; + + if (r < 0) { + kvmppc_inject_pf(vcpu, addr, false); + goto done_load; + } else if (r == EMULATE_DO_MMIO) { + emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, len, 1); + goto done_load; + } + + emulated = EMULATE_DONE; + + /* put in registers */ + switch (ls_type) { + case FPU_LS_SINGLE: + cvt_fd((float*)tmp, (double*)&vcpu->arch.fpr[rs], &t); + vcpu->arch.qpr[rs] = *((u32*)tmp); + break; + case FPU_LS_DOUBLE: + vcpu->arch.fpr[rs] = *((u64*)tmp); + break; + } + + dprintk(KERN_INFO "KVM: FPR_LD [0x%llx] at 0x%lx (%d)\n", *(u64*)tmp, + addr, len); + +done_load: + return emulated; +} + +static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu, + int rs, ulong addr, int ls_type) +{ + int emulated = EMULATE_FAIL; + struct thread_struct t; + int r; + char tmp[8]; + u64 val; + int len; + + t.fpscr.val = vcpu->arch.fpscr; + + switch (ls_type) { + case FPU_LS_SINGLE: + cvt_df((double*)&vcpu->arch.fpr[rs], (float*)tmp, &t); + val = *((u32*)tmp); + len = sizeof(u32); + break; + case FPU_LS_SINGLE_LOW: + *((u32*)tmp) = vcpu->arch.fpr[rs]; + val = vcpu->arch.fpr[rs] & 0xffffffff; + len = sizeof(u32); + break; + case FPU_LS_DOUBLE: + *((u64*)tmp) = vcpu->arch.fpr[rs]; + val = vcpu->arch.fpr[rs]; + len = sizeof(u64); + break; + default: + val = 0; + len = 0; + } + + r = kvmppc_st(vcpu, &addr, len, tmp, true); + vcpu->arch.paddr_accessed = addr; + if (r < 0) { + kvmppc_inject_pf(vcpu, addr, true); + } else if (r == EMULATE_DO_MMIO) { + emulated = kvmppc_handle_store(run, vcpu, val, len, 1); + } else { + emulated = EMULATE_DONE; + } + + dprintk(KERN_INFO "KVM: FPR_ST [0x%llx] at 0x%lx (%d)\n", + val, addr, len); + + return emulated; +} + +static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu, + int rs, ulong addr, bool w, int i) +{ + int emulated = EMULATE_FAIL; + struct thread_struct t; + int r; + float one = 1.0; + u32 tmp[2]; + + t.fpscr.val = vcpu->arch.fpscr; + + /* read from memory */ + if (w) { + r = kvmppc_ld(vcpu, &addr, sizeof(u32), tmp, true); + memcpy(&tmp[1], &one, sizeof(u32)); + } else { + r = kvmppc_ld(vcpu, &addr, sizeof(u32) * 2, tmp, true); + } + vcpu->arch.paddr_accessed = addr; + if (r < 0) { + kvmppc_inject_pf(vcpu, addr, false); + goto done_load; + } else if ((r == EMULATE_DO_MMIO) && w) { + emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, 4, 1); + vcpu->arch.qpr[rs] = tmp[1]; + goto done_load; + } else if (r == EMULATE_DO_MMIO) { + emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FQPR | rs, 8, 1); + goto done_load; + } + + emulated = EMULATE_DONE; + + /* put in registers */ + cvt_fd((float*)&tmp[0], (double*)&vcpu->arch.fpr[rs], &t); + vcpu->arch.qpr[rs] = tmp[1]; + + dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0], + tmp[1], addr, w ? 4 : 8); + +done_load: + return emulated; +} + +static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu, + int rs, ulong addr, bool w, int i) +{ + int emulated = EMULATE_FAIL; + struct thread_struct t; + int r; + u32 tmp[2]; + int len = w ? sizeof(u32) : sizeof(u64); + + t.fpscr.val = vcpu->arch.fpscr; + + cvt_df((double*)&vcpu->arch.fpr[rs], (float*)&tmp[0], &t); + tmp[1] = vcpu->arch.qpr[rs]; + + r = kvmppc_st(vcpu, &addr, len, tmp, true); + vcpu->arch.paddr_accessed = addr; + if (r < 0) { + kvmppc_inject_pf(vcpu, addr, true); + } else if ((r == EMULATE_DO_MMIO) && w) { + emulated = kvmppc_handle_store(run, vcpu, tmp[0], 4, 1); + } else if (r == EMULATE_DO_MMIO) { + u64 val = ((u64)tmp[0] << 32) | tmp[1]; + emulated = kvmppc_handle_store(run, vcpu, val, 8, 1); + } else { + emulated = EMULATE_DONE; + } + + dprintk(KERN_INFO "KVM: PSQ_ST [0x%x, 0x%x] at 0x%lx (%d)\n", + tmp[0], tmp[1], addr, len); + + return emulated; +} + +/* + * Cuts out inst bits with ordering according to spec. + * That means the leftmost bit is zero. All given bits are included. + */ +static inline u32 inst_get_field(u32 inst, int msb, int lsb) +{ + return kvmppc_get_field(inst, msb + 32, lsb + 32); +} + +/* + * Replaces inst bits with ordering according to spec. + */ +static inline u32 inst_set_field(u32 inst, int msb, int lsb, int value) +{ + return kvmppc_set_field(inst, msb + 32, lsb + 32, value); +} + +bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst) +{ + if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)) + return false; + + switch (get_op(inst)) { + case OP_PSQ_L: + case OP_PSQ_LU: + case OP_PSQ_ST: + case OP_PSQ_STU: + case OP_LFS: + case OP_LFSU: + case OP_LFD: + case OP_LFDU: + case OP_STFS: + case OP_STFSU: + case OP_STFD: + case OP_STFDU: + return true; + case 4: + /* X form */ + switch (inst_get_field(inst, 21, 30)) { + case OP_4X_PS_CMPU0: + case OP_4X_PSQ_LX: + case OP_4X_PS_CMPO0: + case OP_4X_PSQ_LUX: + case OP_4X_PS_NEG: + case OP_4X_PS_CMPU1: + case OP_4X_PS_MR: + case OP_4X_PS_CMPO1: + case OP_4X_PS_NABS: + case OP_4X_PS_ABS: + case OP_4X_PS_MERGE00: + case OP_4X_PS_MERGE01: + case OP_4X_PS_MERGE10: + case OP_4X_PS_MERGE11: + return true; + } + /* XW form */ + switch (inst_get_field(inst, 25, 30)) { + case OP_4XW_PSQ_STX: + case OP_4XW_PSQ_STUX: + return true; + } + /* A form */ + switch (inst_get_field(inst, 26, 30)) { + case OP_4A_PS_SUM1: + case OP_4A_PS_SUM0: + case OP_4A_PS_MULS0: + case OP_4A_PS_MULS1: + case OP_4A_PS_MADDS0: + case OP_4A_PS_MADDS1: + case OP_4A_PS_DIV: + case OP_4A_PS_SUB: + case OP_4A_PS_ADD: + case OP_4A_PS_SEL: + case OP_4A_PS_RES: + case OP_4A_PS_MUL: + case OP_4A_PS_RSQRTE: + case OP_4A_PS_MSUB: + case OP_4A_PS_MADD: + case OP_4A_PS_NMSUB: + case OP_4A_PS_NMADD: + return true; + } + break; + case 59: + switch (inst_get_field(inst, 21, 30)) { + case OP_59_FADDS: + case OP_59_FSUBS: + case OP_59_FDIVS: + case OP_59_FRES: + case OP_59_FRSQRTES: + return true; + } + switch (inst_get_field(inst, 26, 30)) { + case OP_59_FMULS: + case OP_59_FMSUBS: + case OP_59_FMADDS: + case OP_59_FNMSUBS: + case OP_59_FNMADDS: + return true; + } + break; + case 63: + switch (inst_get_field(inst, 21, 30)) { + case OP_63_MTFSB0: + case OP_63_MTFSB1: + case OP_63_MTFSF: + case OP_63_MTFSFI: + case OP_63_MCRFS: + case OP_63_MFFS: + case OP_63_FCMPU: + case OP_63_FCMPO: + case OP_63_FNEG: + case OP_63_FMR: + case OP_63_FABS: + case OP_63_FRSP: + case OP_63_FDIV: + case OP_63_FADD: + case OP_63_FSUB: + case OP_63_FCTIW: + case OP_63_FCTIWZ: + case OP_63_FRSQRTE: + case OP_63_FCPSGN: + return true; + } + switch (inst_get_field(inst, 26, 30)) { + case OP_63_FMUL: + case OP_63_FSEL: + case OP_63_FMSUB: + case OP_63_FMADD: + case OP_63_FNMSUB: + case OP_63_FNMADD: + return true; + } + break; + case 31: + switch (inst_get_field(inst, 21, 30)) { + case OP_31_LFSX: + case OP_31_LFSUX: + case OP_31_LFDX: + case OP_31_LFDUX: + case OP_31_STFSX: + case OP_31_STFSUX: + case OP_31_STFX: + case OP_31_STFUX: + case OP_31_STFIWX: + return true; + } + break; + } + + return false; +} + +static int get_d_signext(u32 inst) +{ + int d = inst & 0x8ff; + + if (d & 0x800) + return -(d & 0x7ff); + + return (d & 0x7ff); +} + +static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc, + int reg_out, int reg_in1, int reg_in2, + int reg_in3, int scalar, + void (*func)(struct thread_struct *t, + u32 *dst, u32 *src1, + u32 *src2, u32 *src3)) +{ + u32 *qpr = vcpu->arch.qpr; + u64 *fpr = vcpu->arch.fpr; + u32 ps0_out; + u32 ps0_in1, ps0_in2, ps0_in3; + u32 ps1_in1, ps1_in2, ps1_in3; + struct thread_struct t; + t.fpscr.val = vcpu->arch.fpscr; + + /* RC */ + WARN_ON(rc); + + /* PS0 */ + cvt_df((double*)&fpr[reg_in1], (float*)&ps0_in1, &t); + cvt_df((double*)&fpr[reg_in2], (float*)&ps0_in2, &t); + cvt_df((double*)&fpr[reg_in3], (float*)&ps0_in3, &t); + + if (scalar & SCALAR_LOW) + ps0_in2 = qpr[reg_in2]; + + func(&t, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3); + + dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n", + ps0_in1, ps0_in2, ps0_in3, ps0_out); + + if (!(scalar & SCALAR_NO_PS0)) + cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t); + + /* PS1 */ + ps1_in1 = qpr[reg_in1]; + ps1_in2 = qpr[reg_in2]; + ps1_in3 = qpr[reg_in3]; + + if (scalar & SCALAR_HIGH) + ps1_in2 = ps0_in2; + + if (!(scalar & SCALAR_NO_PS1)) + func(&t, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3); + + dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n", + ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]); + + return EMULATE_DONE; +} + +static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc, + int reg_out, int reg_in1, int reg_in2, + int scalar, + void (*func)(struct thread_struct *t, + u32 *dst, u32 *src1, + u32 *src2)) +{ + u32 *qpr = vcpu->arch.qpr; + u64 *fpr = vcpu->arch.fpr; + u32 ps0_out; + u32 ps0_in1, ps0_in2; + u32 ps1_out; + u32 ps1_in1, ps1_in2; + struct thread_struct t; + t.fpscr.val = vcpu->arch.fpscr; + + /* RC */ + WARN_ON(rc); + + /* PS0 */ + cvt_df((double*)&fpr[reg_in1], (float*)&ps0_in1, &t); + + if (scalar & SCALAR_LOW) + ps0_in2 = qpr[reg_in2]; + else + cvt_df((double*)&fpr[reg_in2], (float*)&ps0_in2, &t); + + func(&t, &ps0_out, &ps0_in1, &ps0_in2); + + if (!(scalar & SCALAR_NO_PS0)) { + dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n", + ps0_in1, ps0_in2, ps0_out); + + cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t); + } + + /* PS1 */ + ps1_in1 = qpr[reg_in1]; + ps1_in2 = qpr[reg_in2]; + + if (scalar & SCALAR_HIGH) + ps1_in2 = ps0_in2; + + func(&t, &ps1_out, &ps1_in1, &ps1_in2); + + if (!(scalar & SCALAR_NO_PS1)) { + qpr[reg_out] = ps1_out; + + dprintk(KERN_INFO "PS2 ps1 -> f(0x%x, 0x%x) = 0x%x\n", + ps1_in1, ps1_in2, qpr[reg_out]); + } + + return EMULATE_DONE; +} + +static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc, + int reg_out, int reg_in, + void (*func)(struct thread_struct *t, + u32 *dst, u32 *src1)) +{ + u32 *qpr = vcpu->arch.qpr; + u64 *fpr = vcpu->arch.fpr; + u32 ps0_out, ps0_in; + u32 ps1_in; + struct thread_struct t; + t.fpscr.val = vcpu->arch.fpscr; + + /* RC */ + WARN_ON(rc); + + /* PS0 */ + cvt_df((double*)&fpr[reg_in], (float*)&ps0_in, &t); + func(&t, &ps0_out, &ps0_in); + + dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n", + ps0_in, ps0_out); + + cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t); + + /* PS1 */ + ps1_in = qpr[reg_in]; + func(&t, &qpr[reg_out], &ps1_in); + + dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n", + ps1_in, qpr[reg_out]); + + return EMULATE_DONE; +} + +int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu) +{ + u32 inst = kvmppc_get_last_inst(vcpu); + enum emulation_result emulated = EMULATE_DONE; + + int ax_rd = inst_get_field(inst, 6, 10); + int ax_ra = inst_get_field(inst, 11, 15); + int ax_rb = inst_get_field(inst, 16, 20); + int ax_rc = inst_get_field(inst, 21, 25); + short full_d = inst_get_field(inst, 16, 31); + + u64 *fpr_d = &vcpu->arch.fpr[ax_rd]; + u64 *fpr_a = &vcpu->arch.fpr[ax_ra]; + u64 *fpr_b = &vcpu->arch.fpr[ax_rb]; + u64 *fpr_c = &vcpu->arch.fpr[ax_rc]; + + bool rcomp = (inst & 1) ? true : false; + u32 cr = kvmppc_get_cr(vcpu); + struct thread_struct t; +#ifdef DEBUG + int i; +#endif + + t.fpscr.val = vcpu->arch.fpscr; + + if (!kvmppc_inst_is_paired_single(vcpu, inst)) + return EMULATE_FAIL; + + if (!(vcpu->arch.msr & MSR_FP)) { + kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL); + return EMULATE_AGAIN; + } + + kvmppc_giveup_ext(vcpu, MSR_FP); + preempt_disable(); + enable_kernel_fp(); + /* Do we need to clear FE0 / FE1 here? Don't think so. */ + +#ifdef DEBUG + for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) { + u32 f; + cvt_df((double*)&vcpu->arch.fpr[i], (float*)&f, &t); + dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx QPR[%d] = 0x%x\n", + i, f, vcpu->arch.fpr[i], i, vcpu->arch.qpr[i]); + } +#endif + + switch (get_op(inst)) { + case OP_PSQ_L: + { + ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0; + bool w = inst_get_field(inst, 16, 16) ? true : false; + int i = inst_get_field(inst, 17, 19); + + addr += get_d_signext(inst); + emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i); + break; + } + case OP_PSQ_LU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra); + bool w = inst_get_field(inst, 16, 16) ? true : false; + int i = inst_get_field(inst, 17, 19); + + addr += get_d_signext(inst); + emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_PSQ_ST: + { + ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0; + bool w = inst_get_field(inst, 16, 16) ? true : false; + int i = inst_get_field(inst, 17, 19); + + addr += get_d_signext(inst); + emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i); + break; + } + case OP_PSQ_STU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra); + bool w = inst_get_field(inst, 16, 16) ? true : false; + int i = inst_get_field(inst, 17, 19); + + addr += get_d_signext(inst); + emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case 4: + /* X form */ + switch (inst_get_field(inst, 21, 30)) { + case OP_4X_PS_CMPU0: + /* XXX */ + emulated = EMULATE_FAIL; + break; + case OP_4X_PSQ_LX: + { + ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0; + bool w = inst_get_field(inst, 21, 21) ? true : false; + int i = inst_get_field(inst, 22, 24); + + addr += kvmppc_get_gpr(vcpu, ax_rb); + emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i); + break; + } + case OP_4X_PS_CMPO0: + /* XXX */ + emulated = EMULATE_FAIL; + break; + case OP_4X_PSQ_LUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra); + bool w = inst_get_field(inst, 21, 21) ? true : false; + int i = inst_get_field(inst, 22, 24); + + addr += kvmppc_get_gpr(vcpu, ax_rb); + emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_4X_PS_NEG: + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb]; + vcpu->arch.fpr[ax_rd] ^= 0x8000000000000000ULL; + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + vcpu->arch.qpr[ax_rd] ^= 0x80000000; + break; + case OP_4X_PS_CMPU1: + /* XXX */ + emulated = EMULATE_FAIL; + break; + case OP_4X_PS_MR: + WARN_ON(rcomp); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb]; + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + break; + case OP_4X_PS_CMPO1: + /* XXX */ + emulated = EMULATE_FAIL; + break; + case OP_4X_PS_NABS: + WARN_ON(rcomp); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb]; + vcpu->arch.fpr[ax_rd] |= 0x8000000000000000ULL; + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + vcpu->arch.qpr[ax_rd] |= 0x80000000; + break; + case OP_4X_PS_ABS: + WARN_ON(rcomp); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb]; + vcpu->arch.fpr[ax_rd] &= ~0x8000000000000000ULL; + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + vcpu->arch.qpr[ax_rd] &= ~0x80000000; + break; + case OP_4X_PS_MERGE00: + WARN_ON(rcomp); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra]; + /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */ + cvt_df((double*)&vcpu->arch.fpr[ax_rb], + (float*)&vcpu->arch.qpr[ax_rd], &t); + break; + case OP_4X_PS_MERGE01: + WARN_ON(rcomp); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra]; + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + break; + case OP_4X_PS_MERGE10: + WARN_ON(rcomp); + /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */ + cvt_fd((float*)&vcpu->arch.qpr[ax_ra], + (double*)&vcpu->arch.fpr[ax_rd], &t); + /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */ + cvt_df((double*)&vcpu->arch.fpr[ax_rb], + (float*)&vcpu->arch.qpr[ax_rd], &t); + break; + case OP_4X_PS_MERGE11: + WARN_ON(rcomp); + /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */ + cvt_fd((float*)&vcpu->arch.qpr[ax_ra], + (double*)&vcpu->arch.fpr[ax_rd], &t); + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb]; + break; + } + /* XW form */ + switch (inst_get_field(inst, 25, 30)) { + case OP_4XW_PSQ_STX: + { + ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0; + bool w = inst_get_field(inst, 21, 21) ? true : false; + int i = inst_get_field(inst, 22, 24); + + addr += kvmppc_get_gpr(vcpu, ax_rb); + emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i); + break; + } + case OP_4XW_PSQ_STUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra); + bool w = inst_get_field(inst, 21, 21) ? true : false; + int i = inst_get_field(inst, 22, 24); + + addr += kvmppc_get_gpr(vcpu, ax_rb); + emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + } + /* A form */ + switch (inst_get_field(inst, 26, 30)) { + case OP_4A_PS_SUM1: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_rb, ax_ra, SCALAR_NO_PS0 | SCALAR_HIGH, fps_fadds); + vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rc]; + break; + case OP_4A_PS_SUM0: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rb, SCALAR_NO_PS1 | SCALAR_LOW, fps_fadds); + vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rc]; + break; + case OP_4A_PS_MULS0: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, SCALAR_HIGH, fps_fmuls); + break; + case OP_4A_PS_MULS1: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, SCALAR_LOW, fps_fmuls); + break; + case OP_4A_PS_MADDS0: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_HIGH, fps_fmadds); + break; + case OP_4A_PS_MADDS1: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_LOW, fps_fmadds); + break; + case OP_4A_PS_DIV: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rb, SCALAR_NONE, fps_fdivs); + break; + case OP_4A_PS_SUB: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rb, SCALAR_NONE, fps_fsubs); + break; + case OP_4A_PS_ADD: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rb, SCALAR_NONE, fps_fadds); + break; + case OP_4A_PS_SEL: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fsel); + break; + case OP_4A_PS_RES: + emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd, + ax_rb, fps_fres); + break; + case OP_4A_PS_MUL: + emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, SCALAR_NONE, fps_fmuls); + break; + case OP_4A_PS_RSQRTE: + emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd, + ax_rb, fps_frsqrte); + break; + case OP_4A_PS_MSUB: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmsubs); + break; + case OP_4A_PS_MADD: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmadds); + break; + case OP_4A_PS_NMSUB: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmsubs); + break; + case OP_4A_PS_NMADD: + emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd, + ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmadds); + break; + } + break; + + /* Real FPU operations */ + + case OP_LFS: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d; + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr, + FPU_LS_SINGLE); + break; + } + case OP_LFSU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d; + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr, + FPU_LS_SINGLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_LFD: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d; + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr, + FPU_LS_DOUBLE); + break; + } + case OP_LFDU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d; + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr, + FPU_LS_DOUBLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_STFS: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d; + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr, + FPU_LS_SINGLE); + break; + } + case OP_STFSU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d; + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr, + FPU_LS_SINGLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_STFD: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d; + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr, + FPU_LS_DOUBLE); + break; + } + case OP_STFDU: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d; + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr, + FPU_LS_DOUBLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case 31: + switch (inst_get_field(inst, 21, 30)) { + case OP_31_LFSX: + { + ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0; + + addr += kvmppc_get_gpr(vcpu, ax_rb); + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, + addr, FPU_LS_SINGLE); + break; + } + case OP_31_LFSUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, + addr, FPU_LS_SINGLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_31_LFDX: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, + addr, FPU_LS_DOUBLE); + break; + } + case OP_31_LFDUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, + addr, FPU_LS_DOUBLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_31_STFSX: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, + addr, FPU_LS_SINGLE); + break; + } + case OP_31_STFSUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, + addr, FPU_LS_SINGLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_31_STFX: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, + addr, FPU_LS_DOUBLE); + break; + } + case OP_31_STFUX: + { + ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, + addr, FPU_LS_DOUBLE); + + if (emulated == EMULATE_DONE) + kvmppc_set_gpr(vcpu, ax_ra, addr); + break; + } + case OP_31_STFIWX: + { + ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + + kvmppc_get_gpr(vcpu, ax_rb); + + emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, + addr, + FPU_LS_SINGLE_LOW); + break; + } + break; + } + break; + case 59: + switch (inst_get_field(inst, 21, 30)) { + case OP_59_FADDS: + fpd_fadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FSUBS: + fpd_fsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FDIVS: + fpd_fdivs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FRES: + fpd_fres(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FRSQRTES: + fpd_frsqrtes(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + } + switch (inst_get_field(inst, 26, 30)) { + case OP_59_FMULS: + fpd_fmuls(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FMSUBS: + fpd_fmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FMADDS: + fpd_fmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FNMSUBS: + fpd_fnmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_59_FNMADDS: + fpd_fnmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + } + break; + case 63: + switch (inst_get_field(inst, 21, 30)) { + case OP_63_MTFSB0: + case OP_63_MTFSB1: + case OP_63_MCRFS: + case OP_63_MTFSFI: + /* XXX need to implement */ + break; + case OP_63_MFFS: + /* XXX missing CR */ + *fpr_d = vcpu->arch.fpscr; + break; + case OP_63_MTFSF: + /* XXX missing fm bits */ + /* XXX missing CR */ + vcpu->arch.fpscr = *fpr_b; + break; + case OP_63_FCMPU: + { + u32 tmp_cr; + u32 cr0_mask = 0xf0000000; + u32 cr_shift = inst_get_field(inst, 6, 8) * 4; + + fpd_fcmpu(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b); + cr &= ~(cr0_mask >> cr_shift); + cr |= (cr & cr0_mask) >> cr_shift; + break; + } + case OP_63_FCMPO: + { + u32 tmp_cr; + u32 cr0_mask = 0xf0000000; + u32 cr_shift = inst_get_field(inst, 6, 8) * 4; + + fpd_fcmpo(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b); + cr &= ~(cr0_mask >> cr_shift); + cr |= (cr & cr0_mask) >> cr_shift; + break; + } + case OP_63_FNEG: + fpd_fneg(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + break; + case OP_63_FMR: + *fpr_d = *fpr_b; + break; + case OP_63_FABS: + fpd_fabs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + break; + case OP_63_FCPSGN: + fpd_fcpsgn(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + break; + case OP_63_FDIV: + fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + break; + case OP_63_FADD: + fpd_fadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + break; + case OP_63_FSUB: + fpd_fsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b); + break; + case OP_63_FCTIW: + fpd_fctiw(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + break; + case OP_63_FCTIWZ: + fpd_fctiwz(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + break; + case OP_63_FRSP: + fpd_frsp(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + kvmppc_sync_qpr(vcpu, ax_rd); + break; + case OP_63_FRSQRTE: + { + double one = 1.0f; + + /* fD = sqrt(fB) */ + fpd_fsqrt(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b); + /* fD = 1.0f / fD */ + fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, (u64*)&one, fpr_d); + break; + } + } + switch (inst_get_field(inst, 26, 30)) { + case OP_63_FMUL: + fpd_fmul(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c); + break; + case OP_63_FSEL: + fpd_fsel(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + break; + case OP_63_FMSUB: + fpd_fmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + break; + case OP_63_FMADD: + fpd_fmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + break; + case OP_63_FNMSUB: + fpd_fnmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + break; + case OP_63_FNMADD: + fpd_fnmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); + break; + } + break; + } + +#ifdef DEBUG + for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) { + u32 f; + cvt_df((double*)&vcpu->arch.fpr[i], (float*)&f, &t); + dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f); + } +#endif + + if (rcomp) + kvmppc_set_cr(vcpu, cr); + + preempt_enable(); + + return emulated; +} diff --git a/arch/powerpc/kvm/book3s_64_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S index c83c60ad96c5..506d5c316c96 100644 --- a/arch/powerpc/kvm/book3s_64_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_rmhandlers.S @@ -22,7 +22,10 @@ #include <asm/reg.h> #include <asm/page.h> #include <asm/asm-offsets.h> + +#ifdef CONFIG_PPC_BOOK3S_64 #include <asm/exception-64s.h> +#endif /***************************************************************************** * * @@ -30,6 +33,39 @@ * * ****************************************************************************/ +#if defined(CONFIG_PPC_BOOK3S_64) + +#define LOAD_SHADOW_VCPU(reg) \ + mfspr reg, SPRN_SPRG_PACA + +#define SHADOW_VCPU_OFF PACA_KVM_SVCPU +#define MSR_NOIRQ MSR_KERNEL & ~(MSR_IR | MSR_DR) +#define FUNC(name) GLUE(.,name) + +#elif defined(CONFIG_PPC_BOOK3S_32) + +#define LOAD_SHADOW_VCPU(reg) \ + mfspr reg, SPRN_SPRG_THREAD; \ + lwz reg, THREAD_KVM_SVCPU(reg); \ + /* PPC32 can have a NULL pointer - let's check for that */ \ + mtspr SPRN_SPRG_SCRATCH1, r12; /* Save r12 */ \ + mfcr r12; \ + cmpwi reg, 0; \ + bne 1f; \ + mfspr reg, SPRN_SPRG_SCRATCH0; \ + mtcr r12; \ + mfspr r12, SPRN_SPRG_SCRATCH1; \ + b kvmppc_resume_\intno; \ +1:; \ + mtcr r12; \ + mfspr r12, SPRN_SPRG_SCRATCH1; \ + tophys(reg, reg) + +#define SHADOW_VCPU_OFF 0 +#define MSR_NOIRQ MSR_KERNEL +#define FUNC(name) name + +#endif .macro INTERRUPT_TRAMPOLINE intno @@ -42,19 +78,19 @@ kvmppc_trampoline_\intno: * First thing to do is to find out if we're coming * from a KVM guest or a Linux process. * - * To distinguish, we check a magic byte in the PACA + * To distinguish, we check a magic byte in the PACA/current */ - mfspr r13, SPRN_SPRG_PACA /* r13 = PACA */ - std r12, PACA_KVM_SCRATCH0(r13) + LOAD_SHADOW_VCPU(r13) + PPC_STL r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13) mfcr r12 - stw r12, PACA_KVM_SCRATCH1(r13) - lbz r12, PACA_KVM_IN_GUEST(r13) + stw r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13) + lbz r12, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13) cmpwi r12, KVM_GUEST_MODE_NONE bne ..kvmppc_handler_hasmagic_\intno /* No KVM guest? Then jump back to the Linux handler! */ - lwz r12, PACA_KVM_SCRATCH1(r13) + lwz r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13) mtcr r12 - ld r12, PACA_KVM_SCRATCH0(r13) + PPC_LL r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13) mfspr r13, SPRN_SPRG_SCRATCH0 /* r13 = original r13 */ b kvmppc_resume_\intno /* Get back original handler */ @@ -76,9 +112,7 @@ kvmppc_trampoline_\intno: INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSTEM_RESET INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_MACHINE_CHECK INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_STORAGE -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_SEGMENT INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_STORAGE -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_SEGMENT INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_EXTERNAL INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALIGNMENT INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PROGRAM @@ -88,7 +122,14 @@ INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSCALL INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_TRACE INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PERFMON INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALTIVEC + +/* Those are only available on 64 bit machines */ + +#ifdef CONFIG_PPC_BOOK3S_64 +INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_SEGMENT +INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_SEGMENT INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_VSX +#endif /* * Bring us back to the faulting code, but skip the @@ -99,11 +140,11 @@ INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_VSX * * Input Registers: * - * R12 = free - * R13 = PACA - * PACA.KVM.SCRATCH0 = guest R12 - * PACA.KVM.SCRATCH1 = guest CR - * SPRG_SCRATCH0 = guest R13 + * R12 = free + * R13 = Shadow VCPU (PACA) + * SVCPU.SCRATCH0 = guest R12 + * SVCPU.SCRATCH1 = guest CR + * SPRG_SCRATCH0 = guest R13 * */ kvmppc_handler_skip_ins: @@ -114,9 +155,9 @@ kvmppc_handler_skip_ins: mtsrr0 r12 /* Clean up all state */ - lwz r12, PACA_KVM_SCRATCH1(r13) + lwz r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13) mtcr r12 - ld r12, PACA_KVM_SCRATCH0(r13) + PPC_LL r12, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13) mfspr r13, SPRN_SPRG_SCRATCH0 /* And get back into the code */ @@ -147,41 +188,48 @@ kvmppc_handler_lowmem_trampoline_end: * * R3 = function * R4 = MSR - * R5 = CTR + * R5 = scratch register * */ _GLOBAL(kvmppc_rmcall) - mtmsr r4 /* Disable relocation, so mtsrr + LOAD_REG_IMMEDIATE(r5, MSR_NOIRQ) + mtmsr r5 /* Disable relocation and interrupts, so mtsrr doesn't get interrupted */ - mtctr r5 + sync mtsrr0 r3 mtsrr1 r4 RFI +#if defined(CONFIG_PPC_BOOK3S_32) +#define STACK_LR INT_FRAME_SIZE+4 +#elif defined(CONFIG_PPC_BOOK3S_64) +#define STACK_LR _LINK +#endif + /* * Activate current's external feature (FPU/Altivec/VSX) */ -#define define_load_up(what) \ - \ -_GLOBAL(kvmppc_load_up_ ## what); \ - subi r1, r1, INT_FRAME_SIZE; \ - mflr r3; \ - std r3, _LINK(r1); \ - mfmsr r4; \ - std r31, GPR3(r1); \ - mr r31, r4; \ - li r5, MSR_DR; \ - oris r5, r5, MSR_EE@h; \ - andc r4, r4, r5; \ - mtmsr r4; \ - \ - bl .load_up_ ## what; \ - \ - mtmsr r31; \ - ld r3, _LINK(r1); \ - ld r31, GPR3(r1); \ - addi r1, r1, INT_FRAME_SIZE; \ - mtlr r3; \ +#define define_load_up(what) \ + \ +_GLOBAL(kvmppc_load_up_ ## what); \ + PPC_STLU r1, -INT_FRAME_SIZE(r1); \ + mflr r3; \ + PPC_STL r3, STACK_LR(r1); \ + PPC_STL r20, _NIP(r1); \ + mfmsr r20; \ + LOAD_REG_IMMEDIATE(r3, MSR_DR|MSR_EE); \ + andc r3,r20,r3; /* Disable DR,EE */ \ + mtmsr r3; \ + sync; \ + \ + bl FUNC(load_up_ ## what); \ + \ + mtmsr r20; /* Enable DR,EE */ \ + sync; \ + PPC_LL r3, STACK_LR(r1); \ + PPC_LL r20, _NIP(r1); \ + mtlr r3; \ + addi r1, r1, INT_FRAME_SIZE; \ blr define_load_up(fpu) @@ -194,11 +242,10 @@ define_load_up(vsx) .global kvmppc_trampoline_lowmem kvmppc_trampoline_lowmem: - .long kvmppc_handler_lowmem_trampoline - _stext + .long kvmppc_handler_lowmem_trampoline - CONFIG_KERNEL_START .global kvmppc_trampoline_enter kvmppc_trampoline_enter: - .long kvmppc_handler_trampoline_enter - _stext - -#include "book3s_64_slb.S" + .long kvmppc_handler_trampoline_enter - CONFIG_KERNEL_START +#include "book3s_segment.S" diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S new file mode 100644 index 000000000000..7c52ed0b7051 --- /dev/null +++ b/arch/powerpc/kvm/book3s_segment.S @@ -0,0 +1,259 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright SUSE Linux Products GmbH 2010 + * + * Authors: Alexander Graf <agraf@suse.de> + */ + +/* Real mode helpers */ + +#if defined(CONFIG_PPC_BOOK3S_64) + +#define GET_SHADOW_VCPU(reg) \ + addi reg, r13, PACA_KVM_SVCPU + +#elif defined(CONFIG_PPC_BOOK3S_32) + +#define GET_SHADOW_VCPU(reg) \ + tophys(reg, r2); \ + lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \ + tophys(reg, reg) + +#endif + +/* Disable for nested KVM */ +#define USE_QUICK_LAST_INST + + +/* Get helper functions for subarch specific functionality */ + +#if defined(CONFIG_PPC_BOOK3S_64) +#include "book3s_64_slb.S" +#elif defined(CONFIG_PPC_BOOK3S_32) +#include "book3s_32_sr.S" +#endif + +/****************************************************************************** + * * + * Entry code * + * * + *****************************************************************************/ + +.global kvmppc_handler_trampoline_enter +kvmppc_handler_trampoline_enter: + + /* Required state: + * + * MSR = ~IR|DR + * R13 = PACA + * R1 = host R1 + * R2 = host R2 + * R10 = guest MSR + * all other volatile GPRS = free + * SVCPU[CR] = guest CR + * SVCPU[XER] = guest XER + * SVCPU[CTR] = guest CTR + * SVCPU[LR] = guest LR + */ + + /* r3 = shadow vcpu */ + GET_SHADOW_VCPU(r3) + + /* Move SRR0 and SRR1 into the respective regs */ + PPC_LL r9, SVCPU_PC(r3) + mtsrr0 r9 + mtsrr1 r10 + + /* Activate guest mode, so faults get handled by KVM */ + li r11, KVM_GUEST_MODE_GUEST + stb r11, SVCPU_IN_GUEST(r3) + + /* Switch to guest segment. This is subarch specific. */ + LOAD_GUEST_SEGMENTS + + /* Enter guest */ + + PPC_LL r4, (SVCPU_CTR)(r3) + PPC_LL r5, (SVCPU_LR)(r3) + lwz r6, (SVCPU_CR)(r3) + lwz r7, (SVCPU_XER)(r3) + + mtctr r4 + mtlr r5 + mtcr r6 + mtxer r7 + + PPC_LL r0, (SVCPU_R0)(r3) + PPC_LL r1, (SVCPU_R1)(r3) + PPC_LL r2, (SVCPU_R2)(r3) + PPC_LL r4, (SVCPU_R4)(r3) + PPC_LL r5, (SVCPU_R5)(r3) + PPC_LL r6, (SVCPU_R6)(r3) + PPC_LL r7, (SVCPU_R7)(r3) + PPC_LL r8, (SVCPU_R8)(r3) + PPC_LL r9, (SVCPU_R9)(r3) + PPC_LL r10, (SVCPU_R10)(r3) + PPC_LL r11, (SVCPU_R11)(r3) + PPC_LL r12, (SVCPU_R12)(r3) + PPC_LL r13, (SVCPU_R13)(r3) + + PPC_LL r3, (SVCPU_R3)(r3) + + RFI +kvmppc_handler_trampoline_enter_end: + + + +/****************************************************************************** + * * + * Exit code * + * * + *****************************************************************************/ + +.global kvmppc_handler_trampoline_exit +kvmppc_handler_trampoline_exit: + + /* Register usage at this point: + * + * SPRG_SCRATCH0 = guest R13 + * R12 = exit handler id + * R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64] + * SVCPU.SCRATCH0 = guest R12 + * SVCPU.SCRATCH1 = guest CR + * + */ + + /* Save registers */ + + PPC_STL r0, (SHADOW_VCPU_OFF + SVCPU_R0)(r13) + PPC_STL r1, (SHADOW_VCPU_OFF + SVCPU_R1)(r13) + PPC_STL r2, (SHADOW_VCPU_OFF + SVCPU_R2)(r13) + PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_R3)(r13) + PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_R4)(r13) + PPC_STL r5, (SHADOW_VCPU_OFF + SVCPU_R5)(r13) + PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_R6)(r13) + PPC_STL r7, (SHADOW_VCPU_OFF + SVCPU_R7)(r13) + PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R8)(r13) + PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R9)(r13) + PPC_STL r10, (SHADOW_VCPU_OFF + SVCPU_R10)(r13) + PPC_STL r11, (SHADOW_VCPU_OFF + SVCPU_R11)(r13) + + /* Restore R1/R2 so we can handle faults */ + PPC_LL r1, (SHADOW_VCPU_OFF + SVCPU_HOST_R1)(r13) + PPC_LL r2, (SHADOW_VCPU_OFF + SVCPU_HOST_R2)(r13) + + /* Save guest PC and MSR */ + mfsrr0 r3 + mfsrr1 r4 + + PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_PC)(r13) + PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_SHADOW_SRR1)(r13) + + /* Get scratch'ed off registers */ + mfspr r9, SPRN_SPRG_SCRATCH0 + PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13) + lwz r7, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13) + + PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R13)(r13) + PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R12)(r13) + stw r7, (SHADOW_VCPU_OFF + SVCPU_CR)(r13) + + /* Save more register state */ + + mfxer r5 + mfdar r6 + mfdsisr r7 + mfctr r8 + mflr r9 + + stw r5, (SHADOW_VCPU_OFF + SVCPU_XER)(r13) + PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_FAULT_DAR)(r13) + stw r7, (SHADOW_VCPU_OFF + SVCPU_FAULT_DSISR)(r13) + PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_CTR)(r13) + PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_LR)(r13) + + /* + * In order for us to easily get the last instruction, + * we got the #vmexit at, we exploit the fact that the + * virtual layout is still the same here, so we can just + * ld from the guest's PC address + */ + + /* We only load the last instruction when it's safe */ + cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE + beq ld_last_inst + cmpwi r12, BOOK3S_INTERRUPT_PROGRAM + beq ld_last_inst + cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT + beq- ld_last_inst + + b no_ld_last_inst + +ld_last_inst: + /* Save off the guest instruction we're at */ + + /* In case lwz faults */ + li r0, KVM_INST_FETCH_FAILED + +#ifdef USE_QUICK_LAST_INST + + /* Set guest mode to 'jump over instruction' so if lwz faults + * we'll just continue at the next IP. */ + li r9, KVM_GUEST_MODE_SKIP + stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13) + + /* 1) enable paging for data */ + mfmsr r9 + ori r11, r9, MSR_DR /* Enable paging for data */ + mtmsr r11 + sync + /* 2) fetch the instruction */ + lwz r0, 0(r3) + /* 3) disable paging again */ + mtmsr r9 + sync + +#endif + stw r0, (SHADOW_VCPU_OFF + SVCPU_LAST_INST)(r13) + +no_ld_last_inst: + + /* Unset guest mode */ + li r9, KVM_GUEST_MODE_NONE + stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13) + + /* Switch back to host MMU */ + LOAD_HOST_SEGMENTS + + /* Register usage at this point: + * + * R1 = host R1 + * R2 = host R2 + * R12 = exit handler id + * R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64] + * SVCPU.* = guest * + * + */ + + /* RFI into the highmem handler */ + mfmsr r7 + ori r7, r7, MSR_IR|MSR_DR|MSR_RI|MSR_ME /* Enable paging */ + mtsrr1 r7 + /* Load highmem handler address */ + PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_VMHANDLER)(r13) + mtsrr0 r8 + + RFI +kvmppc_handler_trampoline_exit_end: diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 2a3a1953d4bd..a33ab8cc2ccc 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -133,6 +133,12 @@ void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_EXTERNAL); } +void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, + struct kvm_interrupt *irq) +{ + clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); +} + /* Deliver the interrupt of the corresponding priority, if possible. */ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) @@ -479,6 +485,8 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; + vcpu_load(vcpu); + regs->pc = vcpu->arch.pc; regs->cr = kvmppc_get_cr(vcpu); regs->ctr = vcpu->arch.ctr; @@ -499,6 +507,8 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) regs->gpr[i] = kvmppc_get_gpr(vcpu, i); + vcpu_put(vcpu); + return 0; } @@ -506,6 +516,8 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) { int i; + vcpu_load(vcpu); + vcpu->arch.pc = regs->pc; kvmppc_set_cr(vcpu, regs->cr); vcpu->arch.ctr = regs->ctr; @@ -525,6 +537,8 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) kvmppc_set_gpr(vcpu, i, regs->gpr[i]); + vcpu_put(vcpu); + return 0; } @@ -553,7 +567,12 @@ int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, struct kvm_translation *tr) { - return kvmppc_core_vcpu_translate(vcpu, tr); + int r; + + vcpu_load(vcpu); + r = kvmppc_core_vcpu_translate(vcpu, tr); + vcpu_put(vcpu); + return r; } int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c index 669a5c5fc7d7..e8a00b0c4449 100644 --- a/arch/powerpc/kvm/e500.c +++ b/arch/powerpc/kvm/e500.c @@ -161,10 +161,10 @@ static int __init kvmppc_e500_init(void) flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers + max_ivor + kvmppc_handler_len); - return kvm_init(NULL, sizeof(struct kvmppc_vcpu_e500), THIS_MODULE); + return kvm_init(NULL, sizeof(struct kvmppc_vcpu_e500), 0, THIS_MODULE); } -static void __init kvmppc_e500_exit(void) +static void __exit kvmppc_e500_exit(void) { kvmppc_booke_exit(); } diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c index cb72a65f4ecc..4568ec386c2a 100644 --- a/arch/powerpc/kvm/emulate.c +++ b/arch/powerpc/kvm/emulate.c @@ -38,10 +38,12 @@ #define OP_31_XOP_LBZX 87 #define OP_31_XOP_STWX 151 #define OP_31_XOP_STBX 215 +#define OP_31_XOP_LBZUX 119 #define OP_31_XOP_STBUX 247 #define OP_31_XOP_LHZX 279 #define OP_31_XOP_LHZUX 311 #define OP_31_XOP_MFSPR 339 +#define OP_31_XOP_LHAX 343 #define OP_31_XOP_STHX 407 #define OP_31_XOP_STHUX 439 #define OP_31_XOP_MTSPR 467 @@ -62,10 +64,12 @@ #define OP_STBU 39 #define OP_LHZ 40 #define OP_LHZU 41 +#define OP_LHA 42 +#define OP_LHAU 43 #define OP_STH 44 #define OP_STHU 45 -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) { return 1; @@ -82,7 +86,7 @@ void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) unsigned long dec_nsec; pr_debug("mtDEC: %x\n", vcpu->arch.dec); -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S /* mtdec lowers the interrupt line when positive. */ kvmppc_core_dequeue_dec(vcpu); @@ -128,7 +132,7 @@ void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) * from opcode tables in the future. */ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) { - u32 inst = vcpu->arch.last_inst; + u32 inst = kvmppc_get_last_inst(vcpu); u32 ea; int ra; int rb; @@ -143,13 +147,9 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); - /* Try again next time */ - if (inst == KVM_INST_FETCH_FAILED) - return EMULATE_DONE; - switch (get_op(inst)) { case OP_TRAP: -#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S case OP_TRAP_64: kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); #else @@ -171,6 +171,19 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); break; + case OP_31_XOP_LBZUX: + rt = get_rt(inst); + ra = get_ra(inst); + rb = get_rb(inst); + + ea = kvmppc_get_gpr(vcpu, rb); + if (ra) + ea += kvmppc_get_gpr(vcpu, ra); + + emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); + kvmppc_set_gpr(vcpu, ra, ea); + break; + case OP_31_XOP_STWX: rs = get_rs(inst); emulated = kvmppc_handle_store(run, vcpu, @@ -200,6 +213,11 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) kvmppc_set_gpr(vcpu, rs, ea); break; + case OP_31_XOP_LHAX: + rt = get_rt(inst); + emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); + break; + case OP_31_XOP_LHZX: rt = get_rt(inst); emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); @@ -450,6 +468,18 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); break; + case OP_LHA: + rt = get_rt(inst); + emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); + break; + + case OP_LHAU: + ra = get_ra(inst); + rt = get_rt(inst); + emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); + kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); + break; + case OP_STH: rs = get_rs(inst); emulated = kvmppc_handle_store(run, vcpu, @@ -472,7 +502,9 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) if (emulated == EMULATE_FAIL) { emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); - if (emulated == EMULATE_FAIL) { + if (emulated == EMULATE_AGAIN) { + advance = 0; + } else if (emulated == EMULATE_FAIL) { advance = 0; printk(KERN_ERR "Couldn't emulate instruction 0x%08x " "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); @@ -480,10 +512,11 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) } } - trace_kvm_ppc_instr(inst, vcpu->arch.pc, emulated); + trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); + /* Advance past emulated instruction. */ if (advance) - vcpu->arch.pc += 4; /* Advance past emulated instruction. */ + kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); return emulated; } diff --git a/arch/powerpc/kvm/fpu.S b/arch/powerpc/kvm/fpu.S new file mode 100644 index 000000000000..2b340a3eee90 --- /dev/null +++ b/arch/powerpc/kvm/fpu.S @@ -0,0 +1,273 @@ +/* + * FPU helper code to use FPU operations from inside the kernel + * + * Copyright (C) 2010 Alexander Graf (agraf@suse.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include <asm/reg.h> +#include <asm/page.h> +#include <asm/mmu.h> +#include <asm/pgtable.h> +#include <asm/cputable.h> +#include <asm/cache.h> +#include <asm/thread_info.h> +#include <asm/ppc_asm.h> +#include <asm/asm-offsets.h> + +/* Instructions operating on single parameters */ + +/* + * Single operation with one input operand + * + * R3 = (double*)&fpscr + * R4 = (short*)&result + * R5 = (short*)¶m1 + */ +#define FPS_ONE_IN(name) \ +_GLOBAL(fps_ ## name); \ + lfd 0,0(r3); /* load up fpscr value */ \ + MTFSF_L(0); \ + lfs 0,0(r5); \ + \ + name 0,0; \ + \ + stfs 0,0(r4); \ + mffs 0; \ + stfd 0,0(r3); /* save new fpscr value */ \ + blr + +/* + * Single operation with two input operands + * + * R3 = (double*)&fpscr + * R4 = (short*)&result + * R5 = (short*)¶m1 + * R6 = (short*)¶m2 + */ +#define FPS_TWO_IN(name) \ +_GLOBAL(fps_ ## name); \ + lfd 0,0(r3); /* load up fpscr value */ \ + MTFSF_L(0); \ + lfs 0,0(r5); \ + lfs 1,0(r6); \ + \ + name 0,0,1; \ + \ + stfs 0,0(r4); \ + mffs 0; \ + stfd 0,0(r3); /* save new fpscr value */ \ + blr + +/* + * Single operation with three input operands + * + * R3 = (double*)&fpscr + * R4 = (short*)&result + * R5 = (short*)¶m1 + * R6 = (short*)¶m2 + * R7 = (short*)¶m3 + */ +#define FPS_THREE_IN(name) \ +_GLOBAL(fps_ ## name); \ + lfd 0,0(r3); /* load up fpscr value */ \ + MTFSF_L(0); \ + lfs 0,0(r5); \ + lfs 1,0(r6); \ + lfs 2,0(r7); \ + \ + name 0,0,1,2; \ + \ + stfs 0,0(r4); \ + mffs 0; \ + stfd 0,0(r3); /* save new fpscr value */ \ + blr + +FPS_ONE_IN(fres) +FPS_ONE_IN(frsqrte) +FPS_ONE_IN(fsqrts) +FPS_TWO_IN(fadds) +FPS_TWO_IN(fdivs) +FPS_TWO_IN(fmuls) +FPS_TWO_IN(fsubs) +FPS_THREE_IN(fmadds) +FPS_THREE_IN(fmsubs) +FPS_THREE_IN(fnmadds) +FPS_THREE_IN(fnmsubs) +FPS_THREE_IN(fsel) + + +/* Instructions operating on double parameters */ + +/* + * Beginning of double instruction processing + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + * R6 = (double*)¶m1 + * R7 = (double*)¶m2 [load_two] + * R8 = (double*)¶m3 [load_three] + * LR = instruction call function + */ +fpd_load_three: + lfd 2,0(r8) /* load param3 */ +fpd_load_two: + lfd 1,0(r7) /* load param2 */ +fpd_load_one: + lfd 0,0(r6) /* load param1 */ +fpd_load_none: + lfd 3,0(r3) /* load up fpscr value */ + MTFSF_L(3) + lwz r6, 0(r4) /* load cr */ + mtcr r6 + blr + +/* + * End of double instruction processing + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + * LR = caller of instruction call function + */ +fpd_return: + mfcr r6 + stfd 0,0(r5) /* save result */ + mffs 0 + stfd 0,0(r3) /* save new fpscr value */ + stw r6,0(r4) /* save new cr value */ + blr + +/* + * Double operation with no input operand + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + */ +#define FPD_NONE_IN(name) \ +_GLOBAL(fpd_ ## name); \ + mflr r12; \ + bl fpd_load_none; \ + mtlr r12; \ + \ + name. 0; /* call instruction */ \ + b fpd_return + +/* + * Double operation with one input operand + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + * R6 = (double*)¶m1 + */ +#define FPD_ONE_IN(name) \ +_GLOBAL(fpd_ ## name); \ + mflr r12; \ + bl fpd_load_one; \ + mtlr r12; \ + \ + name. 0,0; /* call instruction */ \ + b fpd_return + +/* + * Double operation with two input operands + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + * R6 = (double*)¶m1 + * R7 = (double*)¶m2 + * R8 = (double*)¶m3 + */ +#define FPD_TWO_IN(name) \ +_GLOBAL(fpd_ ## name); \ + mflr r12; \ + bl fpd_load_two; \ + mtlr r12; \ + \ + name. 0,0,1; /* call instruction */ \ + b fpd_return + +/* + * CR Double operation with two input operands + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)¶m1 + * R6 = (double*)¶m2 + * R7 = (double*)¶m3 + */ +#define FPD_TWO_IN_CR(name) \ +_GLOBAL(fpd_ ## name); \ + lfd 1,0(r6); /* load param2 */ \ + lfd 0,0(r5); /* load param1 */ \ + lfd 3,0(r3); /* load up fpscr value */ \ + MTFSF_L(3); \ + lwz r6, 0(r4); /* load cr */ \ + mtcr r6; \ + \ + name 0,0,1; /* call instruction */ \ + mfcr r6; \ + mffs 0; \ + stfd 0,0(r3); /* save new fpscr value */ \ + stw r6,0(r4); /* save new cr value */ \ + blr + +/* + * Double operation with three input operands + * + * R3 = (double*)&fpscr + * R4 = (u32*)&cr + * R5 = (double*)&result + * R6 = (double*)¶m1 + * R7 = (double*)¶m2 + * R8 = (double*)¶m3 + */ +#define FPD_THREE_IN(name) \ +_GLOBAL(fpd_ ## name); \ + mflr r12; \ + bl fpd_load_three; \ + mtlr r12; \ + \ + name. 0,0,1,2; /* call instruction */ \ + b fpd_return + +FPD_ONE_IN(fsqrts) +FPD_ONE_IN(frsqrtes) +FPD_ONE_IN(fres) +FPD_ONE_IN(frsp) +FPD_ONE_IN(fctiw) +FPD_ONE_IN(fctiwz) +FPD_ONE_IN(fsqrt) +FPD_ONE_IN(fre) +FPD_ONE_IN(frsqrte) +FPD_ONE_IN(fneg) +FPD_ONE_IN(fabs) +FPD_TWO_IN(fadds) +FPD_TWO_IN(fsubs) +FPD_TWO_IN(fdivs) +FPD_TWO_IN(fmuls) +FPD_TWO_IN_CR(fcmpu) +FPD_TWO_IN(fcpsgn) +FPD_TWO_IN(fdiv) +FPD_TWO_IN(fadd) +FPD_TWO_IN(fmul) +FPD_TWO_IN_CR(fcmpo) +FPD_TWO_IN(fsub) +FPD_THREE_IN(fmsubs) +FPD_THREE_IN(fmadds) +FPD_THREE_IN(fnmsubs) +FPD_THREE_IN(fnmadds) +FPD_THREE_IN(fsel) +FPD_THREE_IN(fmsub) +FPD_THREE_IN(fmadd) +FPD_THREE_IN(fnmsub) +FPD_THREE_IN(fnmadd) diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index 297fcd2ff7d0..9b8683f39e05 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -70,7 +70,7 @@ int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu) case EMULATE_FAIL: /* XXX Deliver Program interrupt to guest. */ printk(KERN_EMERG "%s: emulation failed (%08x)\n", __func__, - vcpu->arch.last_inst); + kvmppc_get_last_inst(vcpu)); r = RESUME_HOST; break; default: @@ -148,6 +148,10 @@ int kvm_dev_ioctl_check_extension(long ext) switch (ext) { case KVM_CAP_PPC_SEGSTATE: + case KVM_CAP_PPC_PAIRED_SINGLES: + case KVM_CAP_PPC_UNSET_IRQ: + case KVM_CAP_ENABLE_CAP: + case KVM_CAP_PPC_OSI: r = 1; break; case KVM_CAP_COALESCED_MMIO: @@ -193,12 +197,17 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) { struct kvm_vcpu *vcpu; vcpu = kvmppc_core_vcpu_create(kvm, id); - kvmppc_create_vcpu_debugfs(vcpu, id); + if (!IS_ERR(vcpu)) + kvmppc_create_vcpu_debugfs(vcpu, id); return vcpu; } void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) { + /* Make sure we're not using the vcpu anymore */ + hrtimer_cancel(&vcpu->arch.dec_timer); + tasklet_kill(&vcpu->arch.tasklet); + kvmppc_remove_vcpu_debugfs(vcpu); kvmppc_core_vcpu_free(vcpu); } @@ -278,7 +287,7 @@ static void kvmppc_complete_dcr_load(struct kvm_vcpu *vcpu, static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run) { - ulong gpr; + u64 gpr; if (run->mmio.len > sizeof(gpr)) { printk(KERN_ERR "bad MMIO length: %d\n", run->mmio.len); @@ -287,6 +296,7 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu, if (vcpu->arch.mmio_is_bigendian) { switch (run->mmio.len) { + case 8: gpr = *(u64 *)run->mmio.data; break; case 4: gpr = *(u32 *)run->mmio.data; break; case 2: gpr = *(u16 *)run->mmio.data; break; case 1: gpr = *(u8 *)run->mmio.data; break; @@ -300,7 +310,43 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu, } } + if (vcpu->arch.mmio_sign_extend) { + switch (run->mmio.len) { +#ifdef CONFIG_PPC64 + case 4: + gpr = (s64)(s32)gpr; + break; +#endif + case 2: + gpr = (s64)(s16)gpr; + break; + case 1: + gpr = (s64)(s8)gpr; + break; + } + } + kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr); + + switch (vcpu->arch.io_gpr & KVM_REG_EXT_MASK) { + case KVM_REG_GPR: + kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr); + break; + case KVM_REG_FPR: + vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr; + break; +#ifdef CONFIG_PPC_BOOK3S + case KVM_REG_QPR: + vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr; + break; + case KVM_REG_FQPR: + vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr; + vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr; + break; +#endif + default: + BUG(); + } } int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, @@ -319,12 +365,25 @@ int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, vcpu->arch.mmio_is_bigendian = is_bigendian; vcpu->mmio_needed = 1; vcpu->mmio_is_write = 0; + vcpu->arch.mmio_sign_extend = 0; return EMULATE_DO_MMIO; } +/* Same as above, but sign extends */ +int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu, + unsigned int rt, unsigned int bytes, int is_bigendian) +{ + int r; + + r = kvmppc_handle_load(run, vcpu, rt, bytes, is_bigendian); + vcpu->arch.mmio_sign_extend = 1; + + return r; +} + int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, - u32 val, unsigned int bytes, int is_bigendian) + u64 val, unsigned int bytes, int is_bigendian) { void *data = run->mmio.data; @@ -342,6 +401,7 @@ int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, /* Store the value at the lowest bytes in 'data'. */ if (is_bigendian) { switch (bytes) { + case 8: *(u64 *)data = val; break; case 4: *(u32 *)data = val; break; case 2: *(u16 *)data = val; break; case 1: *(u8 *)data = val; break; @@ -376,6 +436,13 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) if (!vcpu->arch.dcr_is_write) kvmppc_complete_dcr_load(vcpu, run); vcpu->arch.dcr_needed = 0; + } else if (vcpu->arch.osi_needed) { + u64 *gprs = run->osi.gprs; + int i; + + for (i = 0; i < 32; i++) + kvmppc_set_gpr(vcpu, i, gprs[i]); + vcpu->arch.osi_needed = 0; } kvmppc_core_deliver_interrupts(vcpu); @@ -396,7 +463,10 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq) { - kvmppc_core_queue_external(vcpu, irq); + if (irq->irq == KVM_INTERRUPT_UNSET) + kvmppc_core_dequeue_external(vcpu, irq); + else + kvmppc_core_queue_external(vcpu, irq); if (waitqueue_active(&vcpu->wq)) { wake_up_interruptible(&vcpu->wq); @@ -406,6 +476,27 @@ int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq) return 0; } +static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, + struct kvm_enable_cap *cap) +{ + int r; + + if (cap->flags) + return -EINVAL; + + switch (cap->cap) { + case KVM_CAP_PPC_OSI: + r = 0; + vcpu->arch.osi_enabled = true; + break; + default: + r = -EINVAL; + break; + } + + return r; +} + int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { @@ -434,6 +525,15 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); break; } + case KVM_ENABLE_CAP: + { + struct kvm_enable_cap cap; + r = -EFAULT; + if (copy_from_user(&cap, argp, sizeof(cap))) + goto out; + r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); + break; + } default: r = -EINVAL; } diff --git a/arch/powerpc/mm/mmu_context_hash32.c b/arch/powerpc/mm/mmu_context_hash32.c index 0dfba2bf7f31..d0ee554e86e4 100644 --- a/arch/powerpc/mm/mmu_context_hash32.c +++ b/arch/powerpc/mm/mmu_context_hash32.c @@ -60,11 +60,7 @@ static unsigned long next_mmu_context; static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; - -/* - * Set up the context for a new address space. - */ -int init_new_context(struct task_struct *t, struct mm_struct *mm) +unsigned long __init_new_context(void) { unsigned long ctx = next_mmu_context; @@ -74,19 +70,38 @@ int init_new_context(struct task_struct *t, struct mm_struct *mm) ctx = 0; } next_mmu_context = (ctx + 1) & LAST_CONTEXT; - mm->context.id = ctx; + + return ctx; +} +EXPORT_SYMBOL_GPL(__init_new_context); + +/* + * Set up the context for a new address space. + */ +int init_new_context(struct task_struct *t, struct mm_struct *mm) +{ + mm->context.id = __init_new_context(); return 0; } /* + * Free a context ID. Make sure to call this with preempt disabled! + */ +void __destroy_context(unsigned long ctx) +{ + clear_bit(ctx, context_map); +} +EXPORT_SYMBOL_GPL(__destroy_context); + +/* * We're finished using the context for an address space. */ void destroy_context(struct mm_struct *mm) { preempt_disable(); if (mm->context.id != NO_CONTEXT) { - clear_bit(mm->context.id, context_map); + __destroy_context(mm->context.id); mm->context.id = NO_CONTEXT; } preempt_enable(); diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c index 2c9e52267292..7fd90d02d8c6 100644 --- a/arch/powerpc/oprofile/op_model_cell.c +++ b/arch/powerpc/oprofile/op_model_cell.c @@ -1077,7 +1077,7 @@ static int calculate_lfsr(int n) index = ENTRIES-1; /* make sure index is valid */ - if ((index > ENTRIES) || (index < 0)) + if ((index >= ENTRIES) || (index < 0)) index = ENTRIES-1; return initial_lfsr[index]; diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index eeba0a70e466..69d668c072ae 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig @@ -171,6 +171,17 @@ config ISS4xx help This option enables support for the IBM ISS simulation environment +config ICON + bool "Icon" + depends on 44x + default n + select PPC44x_SIMPLE + select 440SPe + select PCI + select PPC4xx_PCI_EXPRESS + help + This option enables support for the AMCC PPC440SPe evaluation board. + #config LUAN # bool "Luan" # depends on 44x diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c index e8c23ccaa1fc..5f7a29d7f590 100644 --- a/arch/powerpc/platforms/44x/ppc44x_simple.c +++ b/arch/powerpc/platforms/44x/ppc44x_simple.c @@ -61,7 +61,8 @@ static char *board[] __initdata = { "amcc,redwood", "amcc,sequoia", "amcc,taishan", - "amcc,yosemite" + "amcc,yosemite", + "mosaixtech,icon" }; static int __init ppc44x_probe(void) diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c index b7f518a60f03..707e572b7c40 100644 --- a/arch/powerpc/platforms/512x/mpc512x_shared.c +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c @@ -22,6 +22,7 @@ #include <asm/prom.h> #include <asm/time.h> #include <asm/mpc5121.h> +#include <asm/mpc52xx_psc.h> #include "mpc512x.h" @@ -95,9 +96,86 @@ void __init mpc512x_declare_of_platform_devices(void) } } +#define DEFAULT_FIFO_SIZE 16 + +static unsigned int __init get_fifo_size(struct device_node *np, + char *prop_name) +{ + const unsigned int *fp; + + fp = of_get_property(np, prop_name, NULL); + if (fp) + return *fp; + + pr_warning("no %s property in %s node, defaulting to %d\n", + prop_name, np->full_name, DEFAULT_FIFO_SIZE); + + return DEFAULT_FIFO_SIZE; +} + +#define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ + ((u32)(_base) + sizeof(struct mpc52xx_psc))) + +/* Init PSC FIFO space for TX and RX slices */ +void __init mpc512x_psc_fifo_init(void) +{ + struct device_node *np; + void __iomem *psc; + unsigned int tx_fifo_size; + unsigned int rx_fifo_size; + int fifobase = 0; /* current fifo address in 32 bit words */ + + for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") { + tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); + rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); + + /* size in register is in 4 byte units */ + tx_fifo_size /= 4; + rx_fifo_size /= 4; + if (!tx_fifo_size) + tx_fifo_size = 1; + if (!rx_fifo_size) + rx_fifo_size = 1; + + psc = of_iomap(np, 0); + if (!psc) { + pr_err("%s: Can't map %s device\n", + __func__, np->full_name); + continue; + } + + /* FIFO space is 4KiB, check if requested size is available */ + if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { + pr_err("%s: no fifo space available for %s\n", + __func__, np->full_name); + iounmap(psc); + /* + * chances are that another device requests less + * fifo space, so we continue. + */ + continue; + } + + /* set tx and rx fifo size registers */ + out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); + fifobase += tx_fifo_size; + out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); + fifobase += rx_fifo_size; + + /* reset and enable the slices */ + out_be32(&FIFOC(psc)->txcmd, 0x80); + out_be32(&FIFOC(psc)->txcmd, 0x01); + out_be32(&FIFOC(psc)->rxcmd, 0x80); + out_be32(&FIFOC(psc)->rxcmd, 0x01); + + iounmap(psc); + } +} + void __init mpc512x_init(void) { mpc512x_declare_of_platform_devices(); mpc5121_clk_init(); mpc512x_restart_init(); + mpc512x_psc_fifo_init(); } diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c index fda7c2a18282..ca5305a5bd61 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c @@ -168,7 +168,7 @@ static int __devinit mpc52xx_wkup_gpiochip_probe(struct of_device *ofdev, ofchip->gc.get = mpc52xx_wkup_gpio_get; ofchip->gc.set = mpc52xx_wkup_gpio_set; - ret = of_mm_gpiochip_add(ofdev->node, &chip->mmchip); + ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip); if (ret) return ret; @@ -193,8 +193,11 @@ static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = { }; static struct of_platform_driver mpc52xx_wkup_gpiochip_driver = { - .name = "gpio_wkup", - .match_table = mpc52xx_wkup_gpiochip_match, + .driver = { + .name = "gpio_wkup", + .owner = THIS_MODULE, + .of_match_table = mpc52xx_wkup_gpiochip_match, + }, .probe = mpc52xx_wkup_gpiochip_probe, .remove = mpc52xx_gpiochip_remove, }; @@ -329,7 +332,7 @@ static int __devinit mpc52xx_simple_gpiochip_probe(struct of_device *ofdev, ofchip->gc.get = mpc52xx_simple_gpio_get; ofchip->gc.set = mpc52xx_simple_gpio_set; - ret = of_mm_gpiochip_add(ofdev->node, &chip->mmchip); + ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip); if (ret) return ret; @@ -349,8 +352,11 @@ static const struct of_device_id mpc52xx_simple_gpiochip_match[] = { }; static struct of_platform_driver mpc52xx_simple_gpiochip_driver = { - .name = "gpio", - .match_table = mpc52xx_simple_gpiochip_match, + .driver = { + .name = "gpio", + .owner = THIS_MODULE, + .of_match_table = mpc52xx_simple_gpiochip_match, + }, .probe = mpc52xx_simple_gpiochip_probe, .remove = mpc52xx_gpiochip_remove, }; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index a60ee39d3b78..46c93578cbf0 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -734,8 +734,8 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev, spin_lock_init(&gpt->lock); gpt->dev = &ofdev->dev; - gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->node); - gpt->regs = of_iomap(ofdev->node, 0); + gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); + gpt->regs = of_iomap(ofdev->dev.of_node, 0); if (!gpt->regs) { kfree(gpt); return -ENOMEM; @@ -743,21 +743,21 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev, dev_set_drvdata(&ofdev->dev, gpt); - mpc52xx_gpt_gpio_setup(gpt, ofdev->node); - mpc52xx_gpt_irq_setup(gpt, ofdev->node); + mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node); + mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node); mutex_lock(&mpc52xx_gpt_list_mutex); list_add(&gpt->list, &mpc52xx_gpt_list); mutex_unlock(&mpc52xx_gpt_list_mutex); /* check if this device could be a watchdog */ - if (of_get_property(ofdev->node, "fsl,has-wdt", NULL) || - of_get_property(ofdev->node, "has-wdt", NULL)) { + if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) || + of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) { const u32 *on_boot_wdt; gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; - on_boot_wdt = of_get_property(ofdev->node, "fsl,wdt-on-boot", - NULL); + on_boot_wdt = of_get_property(ofdev->dev.of_node, + "fsl,wdt-on-boot", NULL); if (on_boot_wdt) { dev_info(gpt->dev, "used as watchdog\n"); gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; @@ -784,8 +784,11 @@ static const struct of_device_id mpc52xx_gpt_match[] = { }; static struct of_platform_driver mpc52xx_gpt_driver = { - .name = "mpc52xx-gpt", - .match_table = mpc52xx_gpt_match, + .driver = { + .name = "mpc52xx-gpt", + .owner = THIS_MODULE, + .of_match_table = mpc52xx_gpt_match, + }, .probe = mpc52xx_gpt_probe, .remove = mpc52xx_gpt_remove, }; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c index d4f8be307cd5..e86aec644501 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c @@ -445,14 +445,14 @@ mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match) if (lpbfifo.dev != NULL) return -ENOSPC; - lpbfifo.irq = irq_of_parse_and_map(op->node, 0); + lpbfifo.irq = irq_of_parse_and_map(op->dev.of_node, 0); if (!lpbfifo.irq) return -ENODEV; - if (of_address_to_resource(op->node, 0, &res)) + if (of_address_to_resource(op->dev.of_node, 0, &res)) return -ENODEV; lpbfifo.regs_phys = res.start; - lpbfifo.regs = of_iomap(op->node, 0); + lpbfifo.regs = of_iomap(op->dev.of_node, 0); if (!lpbfifo.regs) return -ENOMEM; @@ -537,9 +537,11 @@ static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = { }; static struct of_platform_driver mpc52xx_lpbfifo_driver = { - .owner = THIS_MODULE, - .name = "mpc52xx-lpbfifo", - .match_table = mpc52xx_lpbfifo_match, + .driver = { + .name = "mpc52xx-lpbfifo", + .owner = THIS_MODULE, + .of_match_table = mpc52xx_lpbfifo_match, + }, .probe = mpc52xx_lpbfifo_probe, .remove = __devexit_p(mpc52xx_lpbfifo_remove), }; diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c index f21555d3395a..9f2e52b36f91 100644 --- a/arch/powerpc/platforms/82xx/ep8248e.c +++ b/arch/powerpc/platforms/82xx/ep8248e.c @@ -119,12 +119,12 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, struct device_node *node; int ret; - node = of_get_parent(ofdev->node); + node = of_get_parent(ofdev->dev.of_node); of_node_put(node); if (node != ep8248e_bcsr_node) return -ENODEV; - ret = of_address_to_resource(ofdev->node, 0, &res); + ret = of_address_to_resource(ofdev->dev.of_node, 0, &res); if (ret) return ret; @@ -142,7 +142,7 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, bus->parent = &ofdev->dev; snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); - ret = of_mdiobus_register(bus, ofdev->node); + ret = of_mdiobus_register(bus, ofdev->dev.of_node); if (ret) goto err_free_irq; @@ -170,8 +170,9 @@ static const struct of_device_id ep8248e_mdio_match[] = { static struct of_platform_driver ep8248e_mdio_driver = { .driver = { .name = "ep8248e-mdio-bitbang", + .owner = THIS_MODULE, + .of_match_table = ep8248e_mdio_match, }, - .match_table = ep8248e_mdio_match, .probe = ep8248e_mdio_probe, .remove = ep8248e_mdio_remove, }; diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c index 43805348b81e..ebe6c3537209 100644 --- a/arch/powerpc/platforms/83xx/suspend.c +++ b/arch/powerpc/platforms/83xx/suspend.c @@ -321,7 +321,7 @@ static struct platform_suspend_ops mpc83xx_suspend_ops = { static int pmc_probe(struct of_device *ofdev, const struct of_device_id *match) { - struct device_node *np = ofdev->node; + struct device_node *np = ofdev->dev.of_node; struct resource res; struct pmc_type *type = match->data; int ret = 0; @@ -423,8 +423,11 @@ static struct of_device_id pmc_match[] = { }; static struct of_platform_driver pmc_driver = { - .name = "mpc83xx-pmc", - .match_table = pmc_match, + .driver = { + .name = "mpc83xx-pmc", + .owner = THIS_MODULE, + .of_match_table = pmc_match, + }, .probe = pmc_probe, .remove = pmc_remove }; diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index f0684c8ac960..8fe87fc61485 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. + * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved. * * Author: Andy Fleming <afleming@freescale.com> * @@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev) * Setup the architecture * */ +#ifdef CONFIG_SMP +extern void __init mpc85xx_smp_init(void); +#endif + static void __init mpc85xx_mds_setup_arch(void) { struct device_node *np; @@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void) } #endif +#ifdef CONFIG_SMP + mpc85xx_smp_init(); +#endif + #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe"); if (!np) { @@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void) BCSR_UCC_RGMII, BCSR_UCC_RTBI); } + } else if (machine_is(p1021_mds)) { +#define BCSR11_ENET_MICRST (0x1 << 5) + /* Reset Micrel PHY */ + clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); + setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); } + iounmap(bcsr_regs); } + + if (machine_is(p1021_mds)) { +#define MPC85xx_PMUXCR_OFFSET 0x60 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE12 0x00000008 + static __be32 __iomem *pmuxcr; + + np = of_find_node_by_name(NULL, "global-utilities"); + + if (np) { + pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET; + + if (!pmuxcr) + printk(KERN_EMERG "Error: Alternate function" + " signal multiplex control register not" + " mapped!\n"); + else + /* P1021 has pins muxed for QE and other functions. To + * enable QE UEC mode, we need to set bit QE0 for UCC1 + * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 + * and QE12 for QE MII management singals in PMUXCR + * register. + */ + setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 | + MPC85xx_PMUXCR_QE3 | + MPC85xx_PMUXCR_QE9 | + MPC85xx_PMUXCR_QE12); + + of_node_put(np); + } + + } #endif /* CONFIG_QUICC_ENGINE */ #ifdef CONFIG_SWIOTLB @@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = { {}, }; +static struct of_device_id p1021_ids[] = { + { .type = "soc", }, + { .compatible = "soc", }, + { .compatible = "simple-bus", }, + { .type = "qe", }, + { .compatible = "fsl,qe", }, + { .compatible = "gianfar", }, + {}, +}; + static int __init mpc85xx_publish_devices(void) { if (machine_is(mpc8568_mds)) @@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void) return 0; } + +static int __init p1021_publish_devices(void) +{ + /* Publish the QE devices */ + of_platform_bus_probe(NULL, p1021_ids, NULL); + + return 0; +} + machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); +machine_device_initcall(p1021_mds, p1021_publish_devices); machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); +machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier); static void __init mpc85xx_mds_pic_init(void) { @@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void) mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | - MPIC_BROKEN_FRR_NIRQS, + MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); of_node_put(np); @@ -380,7 +449,11 @@ static void __init mpc85xx_mds_pic_init(void) if (!np) return; } - qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); + if (machine_is(p1021_mds)) + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, + qe_ic_cascade_high_mpic); + else + qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); of_node_put(np); #endif /* CONFIG_QUICC_ENGINE */ } @@ -426,3 +499,26 @@ define_machine(mpc8569_mds) { .pcibios_fixup_bus = fsl_pcibios_fixup_bus, #endif }; + +static int __init p1021_mds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "fsl,P1021MDS"); + +} + +define_machine(p1021_mds) { + .name = "P1021 MDS", + .probe = p1021_mds_probe, + .setup_arch = mpc85xx_mds_setup_arch, + .init_IRQ = mpc85xx_mds_pic_init, + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif +}; + diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index 8efe48192f3f..6257e5378615 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -345,7 +345,7 @@ static int axon_msi_shutdown(struct of_device *device) static int axon_msi_probe(struct of_device *device, const struct of_device_id *device_id) { - struct device_node *dn = device->node; + struct device_node *dn = device->dev.of_node; struct axon_msic *msic; unsigned int virq; int dcr_base, dcr_len; @@ -447,11 +447,12 @@ static const struct of_device_id axon_msi_device_id[] = { }; static struct of_platform_driver axon_msi_driver = { - .match_table = axon_msi_device_id, .probe = axon_msi_probe, .shutdown = axon_msi_shutdown, - .driver = { - .name = "axon-msi" + .driver = { + .name = "axon-msi", + .owner = THIS_MODULE, + .of_match_table = axon_msi_device_id, }, }; diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c index e3ec4976fae7..4326b737d913 100644 --- a/arch/powerpc/platforms/cell/iommu.c +++ b/arch/powerpc/platforms/cell/iommu.c @@ -545,7 +545,6 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev) { struct iommu_window *window; struct cbe_iommu *iommu; - struct dev_archdata *archdata = &dev->archdata; /* Current implementation uses the first window available in that * node's iommu. We -might- do something smarter later though it may @@ -554,7 +553,7 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev) iommu = cell_iommu_for_node(dev_to_node(dev)); if (iommu == NULL || list_empty(&iommu->windows)) { printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", - archdata->of_node ? archdata->of_node->full_name : "?", + dev->of_node ? dev->of_node->full_name : "?", dev_to_node(dev)); return NULL; } @@ -897,7 +896,7 @@ static u64 cell_iommu_get_fixed_address(struct device *dev) const u32 *ranges = NULL; int i, len, best, naddr, nsize, pna, range_size; - np = of_node_get(dev->archdata.of_node); + np = of_node_get(dev->of_node); while (1) { naddr = of_n_addr_cells(np); nsize = of_n_size_cells(np); @@ -1067,7 +1066,7 @@ static int __init cell_iommu_fixed_mapping_init(void) fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); fsize = lmb_phys_mem_size(); - if ((fbase + fsize) <= 0x800000000) + if ((fbase + fsize) <= 0x800000000ul) hbase = 0; /* use the device tree window */ else { /* If we're over 32 GB we need to cheat. We can't map all of diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c index 5c2808252516..1a40da92154c 100644 --- a/arch/powerpc/platforms/cell/spufs/file.c +++ b/arch/powerpc/platforms/cell/spufs/file.c @@ -1849,8 +1849,7 @@ out: return ret; } -static int spufs_mfc_fsync(struct file *file, struct dentry *dentry, - int datasync) +static int spufs_mfc_fsync(struct file *file, int datasync) { return spufs_mfc_flush(file, NULL); } diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c index fc1b1c42b1dc..e5e5f823d687 100644 --- a/arch/powerpc/platforms/cell/spufs/inode.c +++ b/arch/powerpc/platforms/cell/spufs/inode.c @@ -251,7 +251,7 @@ const struct file_operations spufs_context_fops = { .llseek = dcache_dir_lseek, .read = generic_read_dir, .readdir = dcache_readdir, - .fsync = simple_sync_file, + .fsync = noop_fsync, }; EXPORT_SYMBOL_GPL(spufs_context_fops); diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c index 0f881f64583e..627ee089e75d 100644 --- a/arch/powerpc/platforms/pasemi/gpio_mdio.c +++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c @@ -220,7 +220,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev, const struct of_device_id *match) { struct device *dev = &ofdev->dev; - struct device_node *np = ofdev->node; + struct device_node *np = ofdev->dev.of_node; struct mii_bus *new_bus; struct gpio_priv *priv; const unsigned int *prop; @@ -301,11 +301,12 @@ MODULE_DEVICE_TABLE(of, gpio_mdio_match); static struct of_platform_driver gpio_mdio_driver = { - .match_table = gpio_mdio_match, .probe = gpio_mdio_probe, .remove = gpio_mdio_remove, - .driver = { - .name = "gpio-mdio-bitbang", + .driver = { + .name = "gpio-mdio-bitbang", + .owner = THIS_MODULE, + .of_match_table = gpio_mdio_match, }, }; diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index ac6fdd973291..f372ec1691a3 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c @@ -360,10 +360,10 @@ static int pcmcia_notify(struct notifier_block *nb, unsigned long action, /* We know electra_cf devices will always have of_node set, since * electra_cf is an of_platform driver. */ - if (!parent->archdata.of_node) + if (!parent->of_node) return 0; - if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf")) + if (!of_device_is_compatible(parent->of_node, "electra-cf")) return 0; /* We use the direct ops for localbus */ diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index 6d09f5e3e7e4..23083c397528 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -766,7 +766,7 @@ int ps3_system_bus_device_register(struct ps3_system_bus_device *dev) BUG(); }; - dev->core.archdata.of_node = NULL; + dev->core.of_node = NULL; set_dev_node(&dev->core, 0); pr_debug("%s:%d add %s\n", __func__, __LINE__, dev_name(&dev->core)); diff --git a/arch/powerpc/platforms/pseries/hvCall_inst.c b/arch/powerpc/platforms/pseries/hvCall_inst.c index 1fefae76e295..e19ff021e711 100644 --- a/arch/powerpc/platforms/pseries/hvCall_inst.c +++ b/arch/powerpc/platforms/pseries/hvCall_inst.c @@ -102,7 +102,7 @@ static const struct file_operations hcall_inst_seq_fops = { #define CPU_NAME_BUF_SIZE 32 -static void probe_hcall_entry(unsigned long opcode, unsigned long *args) +static void probe_hcall_entry(void *ignored, unsigned long opcode, unsigned long *args) { struct hcall_stats *h; @@ -114,7 +114,7 @@ static void probe_hcall_entry(unsigned long opcode, unsigned long *args) h->purr_start = mfspr(SPRN_PURR); } -static void probe_hcall_exit(unsigned long opcode, unsigned long retval, +static void probe_hcall_exit(void *ignored, unsigned long opcode, unsigned long retval, unsigned long *retbuf) { struct hcall_stats *h; @@ -140,11 +140,11 @@ static int __init hcall_inst_init(void) if (!firmware_has_feature(FW_FEATURE_LPAR)) return 0; - if (register_trace_hcall_entry(probe_hcall_entry)) + if (register_trace_hcall_entry(probe_hcall_entry, NULL)) return -EINVAL; - if (register_trace_hcall_exit(probe_hcall_exit)) { - unregister_trace_hcall_entry(probe_hcall_entry); + if (register_trace_hcall_exit(probe_hcall_exit, NULL)) { + unregister_trace_hcall_entry(probe_hcall_entry, NULL); return -EINVAL; } diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 1a0000a4b6d6..d26182d42cbf 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -468,7 +468,7 @@ static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); - dn = dev->dev.archdata.of_node; + dn = dev->dev.of_node; /* If we're the direct child of a root bus, then we need to allocate * an iommu table ourselves. The bus setup code should have setup diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c index 88f4ae787832..402d2212162f 100644 --- a/arch/powerpc/sysdev/axonram.c +++ b/arch/powerpc/sysdev/axonram.c @@ -185,7 +185,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id) axon_ram_bank_id++; dev_info(&device->dev, "Found memory controller on %s\n", - device->node->full_name); + device->dev.of_node->full_name); bank = kzalloc(sizeof(struct axon_ram_bank), GFP_KERNEL); if (bank == NULL) { @@ -198,7 +198,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id) bank->device = device; - if (of_address_to_resource(device->node, 0, &resource) != 0) { + if (of_address_to_resource(device->dev.of_node, 0, &resource) != 0) { dev_err(&device->dev, "Cannot access device tree\n"); rc = -EFAULT; goto failed; @@ -253,7 +253,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id) blk_queue_logical_block_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE); add_disk(bank->disk); - bank->irq_id = irq_of_parse_and_map(device->node, 0); + bank->irq_id = irq_of_parse_and_map(device->dev.of_node, 0); if (bank->irq_id == NO_IRQ) { dev_err(&device->dev, "Cannot access ECC interrupt ID\n"); rc = -EFAULT; @@ -327,12 +327,12 @@ static struct of_device_id axon_ram_device_id[] = { }; static struct of_platform_driver axon_ram_driver = { - .match_table = axon_ram_device_id, .probe = axon_ram_probe, .remove = axon_ram_remove, - .driver = { - .owner = THIS_MODULE, - .name = AXON_RAM_MODULE_NAME, + .driver = { + .name = AXON_RAM_MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = axon_ram_device_id, }, }; diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.c b/arch/powerpc/sysdev/bestcomm/bestcomm.c index 378ebd9aac18..a7c5c470af14 100644 --- a/arch/powerpc/sysdev/bestcomm/bestcomm.c +++ b/arch/powerpc/sysdev/bestcomm/bestcomm.c @@ -377,7 +377,7 @@ mpc52xx_bcom_probe(struct of_device *op, const struct of_device_id *match) printk(KERN_INFO "DMA: MPC52xx BestComm driver\n"); /* Get the bestcomm node */ - of_node_get(op->node); + of_node_get(op->dev.of_node); /* Prepare SRAM */ ofn_sram = of_find_matching_node(NULL, mpc52xx_sram_ids); @@ -406,10 +406,10 @@ mpc52xx_bcom_probe(struct of_device *op, const struct of_device_id *match) } /* Save the node */ - bcom_eng->ofnode = op->node; + bcom_eng->ofnode = op->dev.of_node; /* Get, reserve & map io */ - if (of_address_to_resource(op->node, 0, &res_bcom)) { + if (of_address_to_resource(op->dev.of_node, 0, &res_bcom)) { printk(KERN_ERR DRIVER_NAME ": " "Can't get resource\n"); rv = -EINVAL; @@ -453,7 +453,7 @@ error_sramclean: kfree(bcom_eng); bcom_sram_cleanup(); error_ofput: - of_node_put(op->node); + of_node_put(op->dev.of_node); printk(KERN_ERR "DMA: MPC52xx BestComm init failed !\n"); @@ -494,14 +494,12 @@ MODULE_DEVICE_TABLE(of, mpc52xx_bcom_of_match); static struct of_platform_driver mpc52xx_bcom_of_platform_driver = { - .owner = THIS_MODULE, - .name = DRIVER_NAME, - .match_table = mpc52xx_bcom_of_match, .probe = mpc52xx_bcom_probe, .remove = mpc52xx_bcom_remove, - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = mpc52xx_bcom_of_match, }, }; diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 3482e3fd89c0..962c2d8dd8d9 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. * * Author: Tony Li <tony.li@freescale.com> * Jason Jin <Jason.jin@freescale.com> @@ -22,14 +22,20 @@ #include <asm/prom.h> #include <asm/hw_irq.h> #include <asm/ppc-pci.h> +#include <asm/mpic.h> #include "fsl_msi.h" +LIST_HEAD(msi_head); + struct fsl_msi_feature { u32 fsl_pic_ip; u32 msiir_offset; }; -static struct fsl_msi *fsl_msi; +struct fsl_msi_cascade_data { + struct fsl_msi *msi_data; + int index; +}; static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) { @@ -54,10 +60,12 @@ static struct irq_chip fsl_msi_chip = { static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { + struct fsl_msi *msi_data = h->host_data; struct irq_chip *chip = &fsl_msi_chip; irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; + set_irq_chip_data(virq, msi_data); set_irq_chip_and_handler(virq, chip, handle_edge_irq); return 0; @@ -96,11 +104,12 @@ static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) static void fsl_teardown_msi_irqs(struct pci_dev *pdev) { struct msi_desc *entry; - struct fsl_msi *msi_data = fsl_msi; + struct fsl_msi *msi_data; list_for_each_entry(entry, &pdev->msi_list, list) { if (entry->irq == NO_IRQ) continue; + msi_data = get_irq_data(entry->irq); set_irq_msi(entry->irq, NULL); msi_bitmap_free_hwirqs(&msi_data->bitmap, virq_to_hw(entry->irq), 1); @@ -111,9 +120,10 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev) } static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, - struct msi_msg *msg) + struct msi_msg *msg, + struct fsl_msi *fsl_msi_data) { - struct fsl_msi *msi_data = fsl_msi; + struct fsl_msi *msi_data = fsl_msi_data; struct pci_controller *hose = pci_bus_to_host(pdev->bus); u32 base = 0; @@ -130,14 +140,19 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) { - int rc, hwirq; + int rc, hwirq = -ENOMEM; unsigned int virq; struct msi_desc *entry; struct msi_msg msg; - struct fsl_msi *msi_data = fsl_msi; + struct fsl_msi *msi_data; list_for_each_entry(entry, &pdev->msi_list, list) { - hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); + list_for_each_entry(msi_data, &msi_head, list) { + hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); + if (hwirq >= 0) + break; + } + if (hwirq < 0) { rc = hwirq; pr_debug("%s: fail allocating msi interrupt\n", @@ -154,25 +169,31 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) rc = -ENOSPC; goto out_free; } + set_irq_data(virq, msi_data); set_irq_msi(virq, entry); - fsl_compose_msi_msg(pdev, hwirq, &msg); + fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); write_msi_msg(virq, &msg); } return 0; out_free: + /* free by the caller of this function */ return rc; } static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) { unsigned int cascade_irq; - struct fsl_msi *msi_data = fsl_msi; + struct fsl_msi *msi_data; int msir_index = -1; u32 msir_value = 0; u32 intr_index; u32 have_shift = 0; + struct fsl_msi_cascade_data *cascade_data; + + cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq); + msi_data = cascade_data->msi_data; raw_spin_lock(&desc->lock); if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { @@ -187,13 +208,13 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) if (unlikely(desc->status & IRQ_INPROGRESS)) goto unlock; - msir_index = (int)desc->handler_data; + msir_index = cascade_data->index; if (msir_index >= NR_MSI_REG) cascade_irq = NO_IRQ; desc->status |= IRQ_INPROGRESS; - switch (fsl_msi->feature & FSL_PIC_IP_MASK) { + switch (msi_data->feature & FSL_PIC_IP_MASK) { case FSL_PIC_IP_MPIC: msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x10); @@ -229,6 +250,30 @@ unlock: raw_spin_unlock(&desc->lock); } +static int fsl_of_msi_remove(struct of_device *ofdev) +{ + struct fsl_msi *msi = ofdev->dev.platform_data; + int virq, i; + struct fsl_msi_cascade_data *cascade_data; + + if (msi->list.prev != NULL) + list_del(&msi->list); + for (i = 0; i < NR_MSI_REG; i++) { + virq = msi->msi_virqs[i]; + if (virq != NO_IRQ) { + cascade_data = get_irq_data(virq); + kfree(cascade_data); + irq_dispose_mapping(virq); + } + } + if (msi->bitmap.bitmap) + msi_bitmap_free(&msi->bitmap); + iounmap(msi->msi_regs); + kfree(msi); + + return 0; +} + static int __devinit fsl_of_msi_probe(struct of_device *dev, const struct of_device_id *match) { @@ -239,17 +284,20 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev, int virt_msir; const u32 *p; struct fsl_msi_feature *features = match->data; + struct fsl_msi_cascade_data *cascade_data = NULL; + int len; + u32 offset; printk(KERN_DEBUG "Setting up Freescale MSI support\n"); msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); if (!msi) { dev_err(&dev->dev, "No memory for MSI structure\n"); - err = -ENOMEM; - goto error_out; + return -ENOMEM; } + dev->dev.platform_data = msi; - msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR, + msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR, NR_MSI_IRQS, &fsl_msi_host_ops, 0); if (msi->irqhost == NULL) { @@ -259,10 +307,10 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev, } /* Get the MSI reg base */ - err = of_address_to_resource(dev->node, 0, &res); + err = of_address_to_resource(dev->dev.of_node, 0, &res); if (err) { dev_err(&dev->dev, "%s resource error!\n", - dev->node->full_name); + dev->dev.of_node->full_name); goto error_out; } @@ -285,40 +333,60 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev, goto error_out; } - p = of_get_property(dev->node, "interrupts", &count); + p = of_get_property(dev->dev.of_node, "interrupts", &count); if (!p) { dev_err(&dev->dev, "no interrupts property found on %s\n", - dev->node->full_name); + dev->dev.of_node->full_name); err = -ENODEV; goto error_out; } if (count % 8 != 0) { dev_err(&dev->dev, "Malformed interrupts property on %s\n", - dev->node->full_name); + dev->dev.of_node->full_name); err = -EINVAL; goto error_out; } + offset = 0; + p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); + if (p) + offset = *p / IRQS_PER_MSI_REG; count /= sizeof(u32); - for (i = 0; i < count / 2; i++) { - if (i > NR_MSI_REG) - break; - virt_msir = irq_of_parse_and_map(dev->node, i); + for (i = 0; i < min(count / 2, NR_MSI_REG); i++) { + virt_msir = irq_of_parse_and_map(dev->dev.of_node, i); if (virt_msir != NO_IRQ) { - set_irq_data(virt_msir, (void *)i); + cascade_data = kzalloc( + sizeof(struct fsl_msi_cascade_data), + GFP_KERNEL); + if (!cascade_data) { + dev_err(&dev->dev, + "No memory for MSI cascade data\n"); + err = -ENOMEM; + goto error_out; + } + msi->msi_virqs[i] = virt_msir; + cascade_data->index = i + offset; + cascade_data->msi_data = msi; + set_irq_data(virt_msir, (void *)cascade_data); set_irq_chained_handler(virt_msir, fsl_msi_cascade); } } - fsl_msi = msi; + list_add_tail(&msi->list, &msi_head); - WARN_ON(ppc_md.setup_msi_irqs); - ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; - ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; - ppc_md.msi_check_device = fsl_msi_check_device; + /* The multiple setting ppc_md.setup_msi_irqs will not harm things */ + if (!ppc_md.setup_msi_irqs) { + ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; + ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; + ppc_md.msi_check_device = fsl_msi_check_device; + } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) { + dev_err(&dev->dev, "Different MSI driver already installed!\n"); + err = -ENODEV; + goto error_out; + } return 0; error_out: - kfree(msi); + fsl_of_msi_remove(dev); return err; } @@ -345,9 +413,13 @@ static const struct of_device_id fsl_of_msi_ids[] = { }; static struct of_platform_driver fsl_of_msi_driver = { - .name = "fsl-msi", - .match_table = fsl_of_msi_ids, + .driver = { + .name = "fsl-msi", + .owner = THIS_MODULE, + .of_match_table = fsl_of_msi_ids, + }, .probe = fsl_of_msi_probe, + .remove = fsl_of_msi_remove, }; static __init int fsl_of_msi_init(void) diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h index 331c7e7025b7..624580c252d7 100644 --- a/arch/powerpc/sysdev/fsl_msi.h +++ b/arch/powerpc/sysdev/fsl_msi.h @@ -32,8 +32,11 @@ struct fsl_msi { u32 msi_addr_hi; void __iomem *msi_regs; u32 feature; + int msi_virqs[NR_MSI_REG]; struct msi_bitmap bitmap; + + struct list_head list; /* support multiple MSI banks */ }; #endif /* _POWERPC_SYSDEV_FSL_MSI_H */ diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c index a7635a993dca..9082eb921ad9 100644 --- a/arch/powerpc/sysdev/fsl_pmc.c +++ b/arch/powerpc/sysdev/fsl_pmc.c @@ -60,7 +60,7 @@ static struct platform_suspend_ops pmc_suspend_ops = { static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id) { - pmc_regs = of_iomap(ofdev->node, 0); + pmc_regs = of_iomap(ofdev->dev.of_node, 0); if (!pmc_regs) return -ENOMEM; @@ -76,8 +76,11 @@ static const struct of_device_id pmc_ids[] = { }; static struct of_platform_driver pmc_driver = { - .driver.name = "fsl-pmc", - .match_table = pmc_ids, + .driver = { + .name = "fsl-pmc", + .owner = THIS_MODULE, + .of_match_table = pmc_ids, + }, .probe = pmc_probe, }; diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 71fba88f50db..30e1626b2e85 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -1,6 +1,15 @@ /* * Freescale MPC85xx/MPC86xx RapidIO support * + * Copyright 2009 Sysgo AG + * Thomas Moll <thomas.moll@sysgo.com> + * - fixed maintenance access routines, check for aligned access + * + * Copyright 2009 Integrated Device Technology, Inc. + * Alex Bounine <alexandre.bounine@idt.com> + * - Added Port-Write message handling + * - Added Machine Check exception handling + * * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc. * Zhang Wei <wei.zhang@freescale.com> * @@ -24,19 +33,30 @@ #include <linux/of_platform.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/kfifo.h> #include <asm/io.h> +#include <asm/machdep.h> +#include <asm/uaccess.h> + +#undef DEBUG_PW /* Port-Write debugging */ /* RapidIO definition irq, which read from OF-tree */ #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) +#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) #define RIO_ATMU_REGS_OFFSET 0x10c00 #define RIO_P_MSG_REGS_OFFSET 0x11000 #define RIO_S_MSG_REGS_OFFSET 0x13000 #define RIO_ESCSR 0x158 #define RIO_CCSR 0x15c +#define RIO_LTLEDCSR 0x0608 +#define RIO_LTLEDCSR_IER 0x80000000 +#define RIO_LTLEDCSR_PRT 0x01000000 +#define RIO_LTLEECSR 0x060c +#define RIO_EPWISR 0x10010 #define RIO_ISR_AACR 0x10120 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ #define RIO_MAINT_WIN_SIZE 0x400000 @@ -55,6 +75,18 @@ #define RIO_MSG_ISR_QFI 0x00000010 #define RIO_MSG_ISR_DIQI 0x00000001 +#define RIO_IPWMR_SEN 0x00100000 +#define RIO_IPWMR_QFIE 0x00000100 +#define RIO_IPWMR_EIE 0x00000020 +#define RIO_IPWMR_CQ 0x00000002 +#define RIO_IPWMR_PWE 0x00000001 + +#define RIO_IPWSR_QF 0x00100000 +#define RIO_IPWSR_TE 0x00000080 +#define RIO_IPWSR_QFI 0x00000010 +#define RIO_IPWSR_PWD 0x00000008 +#define RIO_IPWSR_PWB 0x00000004 + #define RIO_MSG_DESC_SIZE 32 #define RIO_MSG_BUFFER_SIZE 4096 #define RIO_MIN_TX_RING_SIZE 2 @@ -121,7 +153,7 @@ struct rio_msg_regs { u32 pad10[26]; u32 pwmr; u32 pwsr; - u32 pad11; + u32 epwqbar; u32 pwqbar; }; @@ -160,6 +192,14 @@ struct rio_msg_rx_ring { void *dev_id; }; +struct rio_port_write_msg { + void *virt; + dma_addr_t phys; + u32 msg_count; + u32 err_count; + u32 discard_count; +}; + struct rio_priv { struct device *dev; void __iomem *regs_win; @@ -172,11 +212,64 @@ struct rio_priv { struct rio_dbell_ring dbell_ring; struct rio_msg_tx_ring msg_tx_ring; struct rio_msg_rx_ring msg_rx_ring; + struct rio_port_write_msg port_write_msg; int bellirq; int txirq; int rxirq; + int pwirq; + struct work_struct pw_work; + struct kfifo pw_fifo; + spinlock_t pw_fifo_lock; }; +#define __fsl_read_rio_config(x, addr, err, op) \ + __asm__ __volatile__( \ + "1: "op" %1,0(%2)\n" \ + " eieio\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %1,-1\n" \ + " li %0,%3\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (err), "=r" (x) \ + : "b" (addr), "i" (-EFAULT), "0" (err)) + +static void __iomem *rio_regs_win; + +static int (*saved_mcheck_exception)(struct pt_regs *regs); + +static int fsl_rio_mcheck_exception(struct pt_regs *regs) +{ + const struct exception_table_entry *entry = NULL; + unsigned long reason = (mfspr(SPRN_MCSR) & MCSR_MASK); + + if (reason & MCSR_BUS_RBERR) { + reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); + if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { + /* Check if we are prepared to handle this fault */ + entry = search_exception_tables(regs->nip); + if (entry) { + pr_debug("RIO: %s - MC Exception handled\n", + __func__); + out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), + 0); + regs->msr |= MSR_RI; + regs->nip = entry->fixup; + return 1; + } + } + } + + if (saved_mcheck_exception) + return saved_mcheck_exception(regs); + else + return cur_cpu_spec->machine_check(regs); +} + /** * fsl_rio_doorbell_send - Send a MPC85xx doorbell message * @mport: RapidIO master port info @@ -277,27 +370,44 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, { struct rio_priv *priv = mport->priv; u8 *data; + u32 rval, err = 0; pr_debug ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", index, destid, hopcount, offset, len); + + /* 16MB maintenance window possible */ + /* allow only aligned access to maintenance registers */ + if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) + return -EINVAL; + out_be32(&priv->maint_atmu_regs->rowtar, - (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); + (destid << 22) | (hopcount << 12) | (offset >> 12)); + out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); - data = (u8 *) priv->maint_win + offset; + data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); switch (len) { case 1: - *val = in_8((u8 *) data); + __fsl_read_rio_config(rval, data, err, "lbz"); break; case 2: - *val = in_be16((u16 *) data); + __fsl_read_rio_config(rval, data, err, "lhz"); break; - default: - *val = in_be32((u32 *) data); + case 4: + __fsl_read_rio_config(rval, data, err, "lwz"); break; + default: + return -EINVAL; } - return 0; + if (err) { + pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", + err, destid, hopcount, offset); + } + + *val = rval; + + return err; } /** @@ -322,10 +432,17 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, pr_debug ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", index, destid, hopcount, offset, len, val); + + /* 16MB maintenance windows possible */ + /* allow only aligned access to maintenance registers */ + if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) + return -EINVAL; + out_be32(&priv->maint_atmu_regs->rowtar, - (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); + (destid << 22) | (hopcount << 12) | (offset >> 12)); + out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); - data = (u8 *) priv->maint_win + offset; + data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); switch (len) { case 1: out_8((u8 *) data, val); @@ -333,9 +450,11 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, case 2: out_be16((u16 *) data, val); break; - default: + case 4: out_be32((u32 *) data, val); break; + default: + return -EINVAL; } return 0; @@ -930,6 +1049,223 @@ static int fsl_rio_doorbell_init(struct rio_mport *mport) return rc; } +/** + * fsl_rio_port_write_handler - MPC85xx port write interrupt handler + * @irq: Linux interrupt number + * @dev_instance: Pointer to interrupt-specific data + * + * Handles port write interrupts. Parses a list of registered + * port write event handlers and executes a matching event handler. + */ +static irqreturn_t +fsl_rio_port_write_handler(int irq, void *dev_instance) +{ + u32 ipwmr, ipwsr; + struct rio_mport *port = (struct rio_mport *)dev_instance; + struct rio_priv *priv = port->priv; + u32 epwisr, tmp; + + ipwmr = in_be32(&priv->msg_regs->pwmr); + ipwsr = in_be32(&priv->msg_regs->pwsr); + + epwisr = in_be32(priv->regs_win + RIO_EPWISR); + if (epwisr & 0x80000000) { + tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); + pr_info("RIO_LTLEDCSR = 0x%x\n", tmp); + out_be32(priv->regs_win + RIO_LTLEDCSR, 0); + } + + if (!(epwisr & 0x00000001)) + return IRQ_HANDLED; + +#ifdef DEBUG_PW + pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); + if (ipwsr & RIO_IPWSR_QF) + pr_debug(" QF"); + if (ipwsr & RIO_IPWSR_TE) + pr_debug(" TE"); + if (ipwsr & RIO_IPWSR_QFI) + pr_debug(" QFI"); + if (ipwsr & RIO_IPWSR_PWD) + pr_debug(" PWD"); + if (ipwsr & RIO_IPWSR_PWB) + pr_debug(" PWB"); + pr_debug(" )\n"); +#endif + out_be32(&priv->msg_regs->pwsr, + ipwsr & (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); + + if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { + priv->port_write_msg.err_count++; + pr_info("RIO: Port-Write Transaction Err (%d)\n", + priv->port_write_msg.err_count); + } + if (ipwsr & RIO_IPWSR_PWD) { + priv->port_write_msg.discard_count++; + pr_info("RIO: Port Discarded Port-Write Msg(s) (%d)\n", + priv->port_write_msg.discard_count); + } + + /* Schedule deferred processing if PW was received */ + if (ipwsr & RIO_IPWSR_QFI) { + /* Save PW message (if there is room in FIFO), + * otherwise discard it. + */ + if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { + priv->port_write_msg.msg_count++; + kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, + RIO_PW_MSG_SIZE); + } else { + priv->port_write_msg.discard_count++; + pr_info("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", + priv->port_write_msg.discard_count); + } + schedule_work(&priv->pw_work); + } + + /* Issue Clear Queue command. This allows another + * port-write to be received. + */ + out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); + + return IRQ_HANDLED; +} + +static void fsl_pw_dpc(struct work_struct *work) +{ + struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); + unsigned long flags; + u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; + + /* + * Process port-write messages + */ + spin_lock_irqsave(&priv->pw_fifo_lock, flags); + while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, + RIO_PW_MSG_SIZE)) { + /* Process one message */ + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); +#ifdef DEBUG_PW + { + u32 i; + pr_debug("%s : Port-Write Message:", __func__); + for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { + if ((i%4) == 0) + pr_debug("\n0x%02x: 0x%08x", i*4, + msg_buffer[i]); + else + pr_debug(" 0x%08x", msg_buffer[i]); + } + pr_debug("\n"); + } +#endif + /* Pass the port-write message to RIO core for processing */ + rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); + spin_lock_irqsave(&priv->pw_fifo_lock, flags); + } + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); +} + +/** + * fsl_rio_pw_enable - enable/disable port-write interface init + * @mport: Master port implementing the port write unit + * @enable: 1=enable; 0=disable port-write message handling + */ +static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) +{ + struct rio_priv *priv = mport->priv; + u32 rval; + + rval = in_be32(&priv->msg_regs->pwmr); + + if (enable) + rval |= RIO_IPWMR_PWE; + else + rval &= ~RIO_IPWMR_PWE; + + out_be32(&priv->msg_regs->pwmr, rval); + + return 0; +} + +/** + * fsl_rio_port_write_init - MPC85xx port write interface init + * @mport: Master port implementing the port write unit + * + * Initializes port write unit hardware and DMA buffer + * ring. Called from fsl_rio_setup(). Returns %0 on success + * or %-ENOMEM on failure. + */ +static int fsl_rio_port_write_init(struct rio_mport *mport) +{ + struct rio_priv *priv = mport->priv; + int rc = 0; + + /* Following configurations require a disabled port write controller */ + out_be32(&priv->msg_regs->pwmr, + in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); + + /* Initialize port write */ + priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, + RIO_PW_MSG_SIZE, + &priv->port_write_msg.phys, GFP_KERNEL); + if (!priv->port_write_msg.virt) { + pr_err("RIO: unable allocate port write queue\n"); + return -ENOMEM; + } + + priv->port_write_msg.err_count = 0; + priv->port_write_msg.discard_count = 0; + + /* Point dequeue/enqueue pointers at first entry */ + out_be32(&priv->msg_regs->epwqbar, 0); + out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); + + pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", + in_be32(&priv->msg_regs->epwqbar), + in_be32(&priv->msg_regs->pwqbar)); + + /* Clear interrupt status IPWSR */ + out_be32(&priv->msg_regs->pwsr, + (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); + + /* Configure port write contoller for snooping enable all reporting, + clear queue full */ + out_be32(&priv->msg_regs->pwmr, + RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); + + + /* Hook up port-write handler */ + rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0, + "port-write", (void *)mport); + if (rc < 0) { + pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); + goto err_out; + } + + INIT_WORK(&priv->pw_work, fsl_pw_dpc); + spin_lock_init(&priv->pw_fifo_lock); + if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { + pr_err("FIFO allocation failed\n"); + rc = -ENOMEM; + goto err_out_irq; + } + + pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", + in_be32(&priv->msg_regs->pwmr), + in_be32(&priv->msg_regs->pwsr)); + + return rc; + +err_out_irq: + free_irq(IRQ_RIO_PW(mport), (void *)mport); +err_out: + dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, + priv->port_write_msg.virt, + priv->port_write_msg.phys); + return rc; +} + static char *cmdline = NULL; static int fsl_rio_get_hdid(int index) @@ -1015,41 +1351,41 @@ int fsl_rio_setup(struct of_device *dev) u64 law_start, law_size; int paw, aw, sw; - if (!dev->node) { + if (!dev->dev.of_node) { dev_err(&dev->dev, "Device OF-Node is NULL"); return -EFAULT; } - rc = of_address_to_resource(dev->node, 0, ®s); + rc = of_address_to_resource(dev->dev.of_node, 0, ®s); if (rc) { dev_err(&dev->dev, "Can't get %s property 'reg'\n", - dev->node->full_name); + dev->dev.of_node->full_name); return -EFAULT; } - dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name); + dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); dev_info(&dev->dev, "Regs: %pR\n", ®s); - dt_range = of_get_property(dev->node, "ranges", &rlen); + dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); if (!dt_range) { dev_err(&dev->dev, "Can't get %s property 'ranges'\n", - dev->node->full_name); + dev->dev.of_node->full_name); return -EFAULT; } /* Get node address wide */ - cell = of_get_property(dev->node, "#address-cells", NULL); + cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); if (cell) aw = *cell; else - aw = of_n_addr_cells(dev->node); + aw = of_n_addr_cells(dev->dev.of_node); /* Get node size wide */ - cell = of_get_property(dev->node, "#size-cells", NULL); + cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); if (cell) sw = *cell; else - sw = of_n_size_cells(dev->node); + sw = of_n_size_cells(dev->dev.of_node); /* Get parent address wide wide */ - paw = of_n_addr_cells(dev->node); + paw = of_n_addr_cells(dev->dev.of_node); law_start = of_read_number(dt_range + aw, paw); law_size = of_read_number(dt_range + aw + paw, sw); @@ -1057,7 +1393,7 @@ int fsl_rio_setup(struct of_device *dev) dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", law_start, law_size); - ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); + ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); if (!ops) { rc = -ENOMEM; goto err_ops; @@ -1067,6 +1403,7 @@ int fsl_rio_setup(struct of_device *dev) ops->cread = fsl_rio_config_read; ops->cwrite = fsl_rio_config_write; ops->dsend = fsl_rio_doorbell_send; + ops->pwenable = fsl_rio_pw_enable; port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); if (!port) { @@ -1089,11 +1426,12 @@ int fsl_rio_setup(struct of_device *dev) port->iores.flags = IORESOURCE_MEM; port->iores.name = "rio_io_win"; - priv->bellirq = irq_of_parse_and_map(dev->node, 2); - priv->txirq = irq_of_parse_and_map(dev->node, 3); - priv->rxirq = irq_of_parse_and_map(dev->node, 4); - dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq, - priv->txirq, priv->rxirq); + priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); + priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); + priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); + priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); + dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", + priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); @@ -1109,6 +1447,7 @@ int fsl_rio_setup(struct of_device *dev) rio_register_mport(port); priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); + rio_regs_win = priv->regs_win; /* Probe the master port phy type */ ccsr = in_be32(priv->regs_win + RIO_CCSR); @@ -1166,7 +1505,8 @@ int fsl_rio_setup(struct of_device *dev) /* Configure maintenance transaction window */ out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); - out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); /* 4M */ + out_be32(&priv->maint_atmu_regs->rowar, + 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); @@ -1175,6 +1515,12 @@ int fsl_rio_setup(struct of_device *dev) (law_start + RIO_MAINT_WIN_SIZE) >> 12); out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ fsl_rio_doorbell_init(port); + fsl_rio_port_write_init(port); + + saved_mcheck_exception = ppc_md.machine_check_exception; + ppc_md.machine_check_exception = fsl_rio_mcheck_exception; + /* Ensure that RFXE is set */ + mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000)); return 0; err: @@ -1195,7 +1541,7 @@ static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev, { int rc; printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", - dev->node->full_name); + dev->dev.of_node->full_name); rc = fsl_rio_setup(dev); if (rc) @@ -1215,8 +1561,11 @@ static const struct of_device_id fsl_of_rio_rpn_ids[] = { }; static struct of_platform_driver fsl_of_rio_rpn_driver = { - .name = "fsl-of-rio", - .match_table = fsl_of_rio_rpn_ids, + .driver = { + .name = "fsl-of-rio", + .owner = THIS_MODULE, + .of_match_table = fsl_of_rio_rpn_ids, + }, .probe = fsl_of_rio_rpn_probe, }; diff --git a/arch/powerpc/sysdev/pmi.c b/arch/powerpc/sysdev/pmi.c index 652652db4ce2..d07137a07d75 100644 --- a/arch/powerpc/sysdev/pmi.c +++ b/arch/powerpc/sysdev/pmi.c @@ -124,7 +124,7 @@ static void pmi_notify_handlers(struct work_struct *work) static int pmi_of_probe(struct of_device *dev, const struct of_device_id *match) { - struct device_node *np = dev->node; + struct device_node *np = dev->dev.of_node; int rc; if (data) { @@ -206,11 +206,12 @@ static int pmi_of_remove(struct of_device *dev) } static struct of_platform_driver pmi_of_platform_driver = { - .match_table = pmi_match, .probe = pmi_of_probe, .remove = pmi_of_remove, - .driver = { - .name = "pmi", + .driver = { + .name = "pmi", + .owner = THIS_MODULE, + .of_match_table = pmi_match, }, }; diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 106d767bf65b..156aa7d36258 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = .setup_utl = ppc460ex_pciex_init_utl, }; +static int __init ppc460sx_pciex_core_init(struct device_node *np) +{ + /* HSS drive amplitude */ + mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); + mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); + + mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); + mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); + mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); + mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); + + mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); + mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); + mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); + mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); + + /* HSS TX pre-emphasis */ + mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); + + mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); + + mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); + mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); + + /* HSS TX calibration control */ + mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); + mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); + mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); + + /* HSS TX slew control */ + mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); + mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); + mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); + + udelay(100); + + /* De-assert PLLRESET */ + dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); + + /* Reset DL, UTL, GPL before configuration */ + mtdcri(SDR0, PESDR0_460SX_RCSSET, + PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); + mtdcri(SDR0, PESDR1_460SX_RCSSET, + PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); + mtdcri(SDR0, PESDR2_460SX_RCSSET, + PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); + + udelay(100); + + /* + * If bifurcation is not enabled, u-boot would have disabled the + * third PCIe port + */ + if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == + 0x00000001)) { + printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n"); + printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n"); + return 3; + } + + printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n"); + return 2; +} + +static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) +{ + + if (port->endpoint) + dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, + 0x01000000, 0); + else + dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, + 0, 0x01000000); + + /*Gen-1*/ + mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000); + + dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, + (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL), + PESDRx_RCSSET_RSTPYN); + + port->has_ibpre = 1; + + return 0; +} + +static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) +{ + /* Max 128 Bytes */ + out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); + return 0; +} + +static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { + .core_init = ppc460sx_pciex_core_init, + .port_init_hw = ppc460sx_pciex_init_port_hw, + .setup_utl = ppc460sx_pciex_init_utl, +}; + #endif /* CONFIG_44x */ #ifdef CONFIG_40x @@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np) } if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; + if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) + ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops; #endif /* CONFIG_44x */ #ifdef CONFIG_40x if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h index d04e40b306fb..56d9e5deccbf 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.h +++ b/arch/powerpc/sysdev/ppc4xx_pci.h @@ -324,6 +324,64 @@ #define PESDR0_460EX_IHS2 0x036D /* + * 460SX addtional DCRs + */ +#define PESDRn_460SX_RCEI 0x02 + +#define PESDR0_460SX_HSSL0DAMP 0x320 +#define PESDR0_460SX_HSSL1DAMP 0x321 +#define PESDR0_460SX_HSSL2DAMP 0x322 +#define PESDR0_460SX_HSSL3DAMP 0x323 +#define PESDR0_460SX_HSSL4DAMP 0x324 +#define PESDR0_460SX_HSSL5DAMP 0x325 +#define PESDR0_460SX_HSSL6DAMP 0x326 +#define PESDR0_460SX_HSSL7DAMP 0x327 + +#define PESDR1_460SX_HSSL0DAMP 0x354 +#define PESDR1_460SX_HSSL1DAMP 0x355 +#define PESDR1_460SX_HSSL2DAMP 0x356 +#define PESDR1_460SX_HSSL3DAMP 0x357 + +#define PESDR2_460SX_HSSL0DAMP 0x384 +#define PESDR2_460SX_HSSL1DAMP 0x385 +#define PESDR2_460SX_HSSL2DAMP 0x386 +#define PESDR2_460SX_HSSL3DAMP 0x387 + +#define PESDR0_460SX_HSSL0COEFA 0x328 +#define PESDR0_460SX_HSSL1COEFA 0x329 +#define PESDR0_460SX_HSSL2COEFA 0x32A +#define PESDR0_460SX_HSSL3COEFA 0x32B +#define PESDR0_460SX_HSSL4COEFA 0x32C +#define PESDR0_460SX_HSSL5COEFA 0x32D +#define PESDR0_460SX_HSSL6COEFA 0x32E +#define PESDR0_460SX_HSSL7COEFA 0x32F + +#define PESDR1_460SX_HSSL0COEFA 0x358 +#define PESDR1_460SX_HSSL1COEFA 0x359 +#define PESDR1_460SX_HSSL2COEFA 0x35A +#define PESDR1_460SX_HSSL3COEFA 0x35B + +#define PESDR2_460SX_HSSL0COEFA 0x388 +#define PESDR2_460SX_HSSL1COEFA 0x389 +#define PESDR2_460SX_HSSL2COEFA 0x38A +#define PESDR2_460SX_HSSL3COEFA 0x38B + +#define PESDR0_460SX_HSSL1CALDRV 0x339 +#define PESDR1_460SX_HSSL1CALDRV 0x361 +#define PESDR2_460SX_HSSL1CALDRV 0x391 + +#define PESDR0_460SX_HSSSLEW 0x338 +#define PESDR1_460SX_HSSSLEW 0x360 +#define PESDR2_460SX_HSSSLEW 0x390 + +#define PESDR0_460SX_HSSCTLSET 0x31E +#define PESDR1_460SX_HSSCTLSET 0x352 +#define PESDR2_460SX_HSSCTLSET 0x382 + +#define PESDR0_460SX_RCSSET 0x304 +#define PESDR1_460SX_RCSSET 0x344 +#define PESDR2_460SX_RCSSET 0x374 +/* * Of the above, some are common offsets from the base */ #define PESDRn_UTLSET1 0x00 diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 149393c02c3f..093e0ae1a941 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -669,8 +669,11 @@ static const struct of_device_id qe_ids[] = { }; static struct of_platform_driver qe_driver = { - .driver.name = "fsl-qe", - .match_table = qe_ids, + .driver = { + .name = "fsl-qe", + .owner = THIS_MODULE, + .of_match_table = qe_ids, + }, .probe = qe_probe, .resume = qe_resume, }; diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 79d0ca086820..bee1c0f794cf 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -102,6 +102,7 @@ config S390 select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA + select HAVE_KERNEL_LZO select ARCH_INLINE_SPIN_TRYLOCK select ARCH_INLINE_SPIN_TRYLOCK_BH select ARCH_INLINE_SPIN_LOCK @@ -479,13 +480,6 @@ config CMM Everybody who wants to run Linux under VM should select this option. -config CMM_PROC - bool "/proc interface to cooperative memory management" - depends on CMM - help - Select this option to enable the /proc interface to the - cooperative memory management. - config CMM_IUCV bool "IUCV special message interface to cooperative memory management" depends on CMM && (SMSGIUCV=y || CMM=SMSGIUCV) diff --git a/arch/s390/appldata/appldata_os.c b/arch/s390/appldata/appldata_os.c index 55c80ffd42b9..92f1cb745d69 100644 --- a/arch/s390/appldata/appldata_os.c +++ b/arch/s390/appldata/appldata_os.c @@ -181,7 +181,7 @@ static int __init appldata_os_init(void) goto out; } - appldata_os_data = kzalloc(max_size, GFP_DMA); + appldata_os_data = kzalloc(max_size, GFP_KERNEL | GFP_DMA); if (appldata_os_data == NULL) { rc = -ENOMEM; goto out; diff --git a/arch/s390/boot/compressed/Makefile b/arch/s390/boot/compressed/Makefile index 6e4a67ad07e1..1c999f726a58 100644 --- a/arch/s390/boot/compressed/Makefile +++ b/arch/s390/boot/compressed/Makefile @@ -7,7 +7,7 @@ BITS := $(if $(CONFIG_64BIT),64,31) targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \ - vmlinux.bin.lzma misc.o piggy.o sizes.h head$(BITS).o + vmlinux.bin.lzma vmlinux.bin.lzo misc.o piggy.o sizes.h head$(BITS).o KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 KBUILD_CFLAGS += $(cflags-y) @@ -47,6 +47,7 @@ vmlinux.bin.all-y := $(obj)/vmlinux.bin suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma +suffix-$(CONFIG_KERNEL_LZO) := lzo $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) $(call if_changed,gzip) @@ -54,6 +55,8 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) $(call if_changed,bzip2) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) $(call if_changed,lzma) +$(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) + $(call if_changed,lzo) LDFLAGS_piggy.o := -r --format binary --oformat $(LD_BFD) -T $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c index 14e0479d3888..0851eb1e919e 100644 --- a/arch/s390/boot/compressed/misc.c +++ b/arch/s390/boot/compressed/misc.c @@ -50,6 +50,10 @@ static unsigned long free_mem_end_ptr; #include "../../../../lib/decompress_unlzma.c" #endif +#ifdef CONFIG_KERNEL_LZO +#include "../../../../lib/decompress_unlzo.c" +#endif + extern _sclp_print_early(const char *); int puts(const char *s) diff --git a/arch/s390/defconfig b/arch/s390/defconfig index bcd6884985ad..253f158db668 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.34-rc3 -# Fri Apr 9 09:57:10 2010 +# Linux kernel version: 2.6.35-rc1 +# Fri Jun 4 11:32:40 2010 # CONFIG_SCHED_MC=y CONFIG_MMU=y @@ -35,11 +35,13 @@ CONFIG_CONSTRUCTORS=y CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set @@ -77,6 +79,7 @@ CONFIG_CGROUP_NS=y # CONFIG_CGROUP_CPUACCT is not set # CONFIG_RESOURCE_COUNTERS is not set # CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set @@ -157,7 +160,6 @@ CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_CGROUP is not set CONFIG_BLOCK_COMPAT=y # @@ -166,7 +168,6 @@ CONFIG_BLOCK_COMPAT=y CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_CFQ_GROUP_IOSCHED is not set CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set @@ -247,7 +248,6 @@ CONFIG_64BIT=y CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_HOTPLUG_CPU=y -# CONFIG_SCHED_BOOK is not set CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_AUDIT_ARCH=y @@ -320,7 +320,6 @@ CONFIG_COMPAT_BINFMT_ELF=y # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m CONFIG_FORCE_MAX_ZONEORDER=9 -# CONFIG_PROCESS_DEBUG is not set CONFIG_PFAULT=y # CONFIG_SHARED_KERNEL is not set # CONFIG_CMM is not set @@ -457,6 +456,7 @@ CONFIG_NF_CONNTRACK=m # CONFIG_IP6_NF_IPTABLES is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=m +# CONFIG_NET_SCTPPROBE is not set # CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set # CONFIG_SCTP_HMAC_NONE is not set @@ -465,6 +465,7 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set # CONFIG_BRIDGE is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set @@ -525,6 +526,7 @@ CONFIG_NET_ACT_NAT=m # CONFIG_NET_CLS_IND is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set +CONFIG_RPS=y # # Network testing @@ -546,6 +548,7 @@ CONFIG_CAN_VCAN=m # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set +# CONFIG_CAIF is not set # CONFIG_PCMCIA is not set CONFIG_CCW=y @@ -728,6 +731,7 @@ CONFIG_VIRTIO_NET=m # Character devices # CONFIG_DEVKMEM=y +# CONFIG_N_GSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -775,6 +779,7 @@ CONFIG_S390_TAPE_34XX=m # CONFIG_MONREADER is not set CONFIG_MONWRITER=m CONFIG_S390_VMUR=m +# CONFIG_RAMOOPS is not set # # PPS support @@ -788,10 +793,6 @@ CONFIG_S390_VMUR=m # CONFIG_NEW_LEDS is not set CONFIG_ACCESSIBILITY=y # CONFIG_AUXDISPLAY is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -976,6 +977,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y # CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y @@ -1010,6 +1012,7 @@ CONFIG_BRANCH_PROFILE_NONE=y CONFIG_KPROBE_EVENT=y # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set CONFIG_SAMPLES=y # CONFIG_SAMPLE_TRACEPOINTS is not set # CONFIG_SAMPLE_TRACE_EVENTS is not set diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h index 451bfbb9db3d..76daea117181 100644 --- a/arch/s390/include/asm/atomic.h +++ b/arch/s390/include/asm/atomic.h @@ -15,6 +15,7 @@ #include <linux/compiler.h> #include <linux/types.h> +#include <asm/system.h> #define ATOMIC_INIT(i) { (i) } @@ -274,6 +275,7 @@ static inline void atomic64_clear_mask(unsigned long long mask, atomic64_t *v) static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) { long long c, old; + c = atomic64_read(v); for (;;) { if (unlikely(c == u)) @@ -286,6 +288,23 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) return c != u; } +static inline long long atomic64_dec_if_positive(atomic64_t *v) +{ + long long c, old, dec; + + c = atomic64_read(v); + for (;;) { + dec = c - 1; + if (unlikely(dec < 0)) + break; + old = atomic64_cmpxchg((v), c, dec); + if (likely(old == c)) + break; + c = old; + } + return dec; +} + #define atomic64_add(_i, _v) atomic64_add_return(_i, _v) #define atomic64_add_negative(_i, _v) (atomic64_add_return(_i, _v) < 0) #define atomic64_inc(_v) atomic64_add_return(1, _v) diff --git a/arch/s390/include/asm/bug.h b/arch/s390/include/asm/bug.h index 9beeb9db9b23..bf90d1fd97a5 100644 --- a/arch/s390/include/asm/bug.h +++ b/arch/s390/include/asm/bug.h @@ -46,18 +46,18 @@ unreachable(); \ } while (0) -#define __WARN() do { \ - __EMIT_BUG(BUGFLAG_WARNING); \ +#define __WARN_TAINT(taint) do { \ + __EMIT_BUG(BUGFLAG_TAINT(taint)); \ } while (0) #define WARN_ON(x) ({ \ int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ - __EMIT_BUG(BUGFLAG_WARNING); \ + __WARN(); \ } else { \ if (unlikely(__ret_warn_on)) \ - __EMIT_BUG(BUGFLAG_WARNING); \ + __WARN(); \ } \ unlikely(__ret_warn_on); \ }) diff --git a/arch/s390/include/asm/cache.h b/arch/s390/include/asm/cache.h index 9b866816863c..24aafa68b643 100644 --- a/arch/s390/include/asm/cache.h +++ b/arch/s390/include/asm/cache.h @@ -14,6 +14,6 @@ #define L1_CACHE_BYTES 256 #define L1_CACHE_SHIFT 8 -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #endif diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h index f4bd346a52d3..1c0030f9b890 100644 --- a/arch/s390/include/asm/ccwdev.h +++ b/arch/s390/include/asm/ccwdev.h @@ -91,6 +91,14 @@ struct ccw_device { void (*handler) (struct ccw_device *, unsigned long, struct irb *); }; +/* + * Possible CIO actions triggered by the unit check handler. + */ +enum uc_todo { + UC_TODO_RETRY, + UC_TODO_RETRY_ON_NEW_PATH, + UC_TODO_STOP +}; /** * struct ccw driver - device driver for channel attached devices @@ -107,6 +115,7 @@ struct ccw_device { * @freeze: callback for freezing during hibernation snapshotting * @thaw: undo work done in @freeze * @restore: callback for restoring after hibernation + * @uc_handler: callback for unit check handler * @driver: embedded device driver structure * @name: device driver name */ @@ -124,6 +133,7 @@ struct ccw_driver { int (*freeze)(struct ccw_device *); int (*thaw) (struct ccw_device *); int (*restore)(struct ccw_device *); + enum uc_todo (*uc_handler) (struct ccw_device *, struct irb *); struct device_driver driver; char *name; }; diff --git a/arch/s390/include/asm/scatterlist.h b/arch/s390/include/asm/scatterlist.h index 35d786fe93ae..be44d94cba54 100644 --- a/arch/s390/include/asm/scatterlist.h +++ b/arch/s390/include/asm/scatterlist.h @@ -1 +1,3 @@ +#define ISA_DMA_THRESHOLD (~0UL) + #include <asm-generic/scatterlist.h> diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index d9b490a2716e..5232278d79ad 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -132,8 +132,6 @@ int main(void) DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock)); DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags)); DEFINE(__LC_FTRACE_FUNC, offsetof(struct _lowcore, ftrace_func)); - DEFINE(__LC_SIE_HOOK, offsetof(struct _lowcore, sie_hook)); - DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp)); DEFINE(__LC_IRB, offsetof(struct _lowcore, irb)); DEFINE(__LC_CPU_TIMER_SAVE_AREA, offsetof(struct _lowcore, cpu_timer_save_area)); DEFINE(__LC_CLOCK_COMP_SAVE_AREA, offsetof(struct _lowcore, clock_comp_save_area)); @@ -154,6 +152,8 @@ int main(void) DEFINE(__LC_FP_CREG_SAVE_AREA, offsetof(struct _lowcore, fpt_creg_save_area)); DEFINE(__LC_LAST_BREAK, offsetof(struct _lowcore, breaking_event_addr)); DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data)); + DEFINE(__LC_SIE_HOOK, offsetof(struct _lowcore, sie_hook)); + DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp)); #endif /* CONFIG_32BIT */ return 0; } diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 178d92536d90..e7192e1cb678 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -65,7 +65,7 @@ _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \ ltgr %r3,%r3 jz 0f basr %r14,%r3 - 0: +0: #endif .endm diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 3d34eef5a2c3..2a3d2bf6f083 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -63,6 +63,8 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction) case 0x0b: /* bsm */ case 0x83: /* diag */ case 0x44: /* ex */ + case 0xac: /* stnsm */ + case 0xad: /* stosm */ return -EINVAL; } switch (*(__u16 *) instruction) { @@ -72,6 +74,7 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction) case 0xb258: /* bsg */ case 0xb218: /* pc */ case 0xb228: /* pt */ + case 0xb98d: /* epsw */ return -EINVAL; } return 0; diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c index 639380a0c45c..22cfd634c355 100644 --- a/arch/s390/kernel/module.c +++ b/arch/s390/kernel/module.c @@ -55,8 +55,10 @@ void *module_alloc(unsigned long size) /* Free memory returned from module_alloc */ void module_free(struct module *mod, void *module_region) { - vfree(mod->arch.syminfo); - mod->arch.syminfo = NULL; + if (mod) { + vfree(mod->arch.syminfo); + mod->arch.syminfo = NULL; + } vfree(module_region); } diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 7d893248d265..c8e8e1354e1d 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -401,7 +401,6 @@ setup_lowcore(void) lc->io_new_psw.mask = psw_kernel_bits; lc->io_new_psw.addr = PSW_ADDR_AMODE | (unsigned long) io_int_handler; lc->clock_comparator = -1ULL; - lc->cmf_hpp = -1ULL; lc->kernel_stack = ((unsigned long) &init_thread_union) + THREAD_SIZE; lc->async_stack = (unsigned long) __alloc_bootmem(ASYNC_SIZE, ASYNC_SIZE, 0) + ASYNC_SIZE; @@ -418,6 +417,7 @@ setup_lowcore(void) __ctl_set_bit(14, 29); } #else + lc->cmf_hpp = -1ULL; lc->vdso_per_cpu_data = (unsigned long) &lc->paste[0]; #endif lc->sync_enter_timer = S390_lowcore.sync_enter_timer; diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index e4d98de83dd8..541053ed234e 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -944,21 +944,21 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self, struct cpu *c = &per_cpu(cpu_devices, cpu); struct sys_device *s = &c->sysdev; struct s390_idle_data *idle; + int err = 0; switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: idle = &per_cpu(s390_idle, cpu); memset(idle, 0, sizeof(struct s390_idle_data)); - if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) - return NOTIFY_BAD; + err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); break; case CPU_DEAD: case CPU_DEAD_FROZEN: sysfs_remove_group(&s->kobj, &cpu_online_attr_group); break; } - return NOTIFY_OK; + return notifier_from_errno(err); } static struct notifier_block __cpuinitdata smp_cpu_nb = { diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S index c56d3f56d020..1f066e46e83e 100644 --- a/arch/s390/kernel/swsusp_asm64.S +++ b/arch/s390/kernel/swsusp_asm64.S @@ -264,7 +264,7 @@ restore_registers: lghi %r2,0 br %r14 - .section .data.nosave,"aw",@progbits + .section .data..nosave,"aw",@progbits .align 8 .Ldisabled_wait_31: .long 0x000a0000,0x00000000 diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig index 2f4b687cc7fa..a7251580891c 100644 --- a/arch/s390/kvm/Kconfig +++ b/arch/s390/kvm/Kconfig @@ -33,17 +33,6 @@ config KVM If unsure, say N. -config KVM_AWARE_CMF - depends on KVM - bool "KVM aware sampling" - ---help--- - This option enhances the sampling data from the CPU Measurement - Facility with additional information, that allows to distinguish - guest(s) and host when using the kernel based virtual machine - functionality. - - If unsure, say N. - # OK, it's a little counter-intuitive to do this, but it puts it neatly under # the virtualization menu. source drivers/vhost/Kconfig diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 49292869a5cd..ae3705816878 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -341,11 +341,13 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, rc = kvm_vcpu_init(vcpu, kvm, id); if (rc) - goto out_free_cpu; + goto out_free_sie_block; VM_EVENT(kvm, 3, "create cpu %d at %p, sie block at %p", id, vcpu, vcpu->arch.sie_block); return vcpu; +out_free_sie_block: + free_page((unsigned long)(vcpu->arch.sie_block)); out_free_cpu: kfree(vcpu); out_nomem: @@ -750,7 +752,7 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) static int __init kvm_s390_init(void) { int ret; - ret = kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); + ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); if (ret) return ret; @@ -759,7 +761,7 @@ static int __init kvm_s390_init(void) * to hold the maximum amount of facilites. On the other hand, we * only set facilities that are known to work in KVM. */ - facilities = (unsigned long long *) get_zeroed_page(GFP_DMA); + facilities = (unsigned long long *) get_zeroed_page(GFP_KERNEL|GFP_DMA); if (!facilities) { kvm_exit(); return -ENOMEM; diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 60f09ab3672c..cfa9d1777457 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -72,7 +72,7 @@ static inline void kvm_s390_vcpu_set_mem(struct kvm_vcpu *vcpu) struct kvm_memslots *memslots; idx = srcu_read_lock(&vcpu->kvm->srcu); - memslots = rcu_dereference(vcpu->kvm->memslots); + memslots = kvm_memslots(vcpu->kvm); mem = &memslots->memslots[0]; diff --git a/arch/s390/kvm/sie64a.S b/arch/s390/kvm/sie64a.S index 31646bd0e469..7e9d30d567b0 100644 --- a/arch/s390/kvm/sie64a.S +++ b/arch/s390/kvm/sie64a.S @@ -32,12 +32,10 @@ SPI_PSW = STACK_FRAME_OVERHEAD + __PT_PSW .macro SPP newpp -#ifdef CONFIG_KVM_AWARE_CMF tm __LC_MACHINE_FLAGS+6,0x20 # MACHINE_FLAG_SPP jz 0f .insn s,0xb2800000,\newpp - 0: -#endif +0: .endm sie_irq_handler: diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c index eff3c5989b46..702276f5e2fa 100644 --- a/arch/s390/kvm/sigp.c +++ b/arch/s390/kvm/sigp.c @@ -113,7 +113,7 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action) { struct kvm_s390_interrupt_info *inti; - inti = kzalloc(sizeof(*inti), GFP_KERNEL); + inti = kzalloc(sizeof(*inti), GFP_ATOMIC); if (!inti) return -ENOMEM; inti->type = KVM_S390_SIGP_STOP; diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c index f87b34731e1d..eb6a2ef5f82e 100644 --- a/arch/s390/mm/cmm.c +++ b/arch/s390/mm/cmm.c @@ -1,11 +1,9 @@ /* - * arch/s390/mm/cmm.c + * Collaborative memory management interface. * - * S390 version - * Copyright (C) 2003 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) + * Copyright IBM Corp 2003,2010 + * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, * - * Collaborative memory management interface. */ #include <linux/errno.h> @@ -20,9 +18,9 @@ #include <linux/kthread.h> #include <linux/oom.h> #include <linux/suspend.h> +#include <linux/uaccess.h> #include <asm/pgalloc.h> -#include <asm/uaccess.h> #include <asm/diag.h> static char *sender = "VMRMSVM"; @@ -53,14 +51,14 @@ static struct cmm_page_array *cmm_timed_page_list; static DEFINE_SPINLOCK(cmm_lock); static struct task_struct *cmm_thread_ptr; -static wait_queue_head_t cmm_thread_wait; -static struct timer_list cmm_timer; +static DECLARE_WAIT_QUEUE_HEAD(cmm_thread_wait); +static DEFINE_TIMER(cmm_timer, NULL, 0, 0); static void cmm_timer_fn(unsigned long); static void cmm_set_timer(void); -static long -cmm_alloc_pages(long nr, long *counter, struct cmm_page_array **list) +static long cmm_alloc_pages(long nr, long *counter, + struct cmm_page_array **list) { struct cmm_page_array *pa, *npa; unsigned long addr; @@ -99,8 +97,7 @@ cmm_alloc_pages(long nr, long *counter, struct cmm_page_array **list) return nr; } -static long -cmm_free_pages(long nr, long *counter, struct cmm_page_array **list) +static long cmm_free_pages(long nr, long *counter, struct cmm_page_array **list) { struct cmm_page_array *pa; unsigned long addr; @@ -140,11 +137,10 @@ static int cmm_oom_notify(struct notifier_block *self, } static struct notifier_block cmm_oom_nb = { - .notifier_call = cmm_oom_notify + .notifier_call = cmm_oom_notify, }; -static int -cmm_thread(void *dummy) +static int cmm_thread(void *dummy) { int rc; @@ -170,7 +166,7 @@ cmm_thread(void *dummy) cmm_timed_pages_target = cmm_timed_pages; } else if (cmm_timed_pages_target < cmm_timed_pages) { cmm_free_pages(1, &cmm_timed_pages, - &cmm_timed_page_list); + &cmm_timed_page_list); } if (cmm_timed_pages > 0 && !timer_pending(&cmm_timer)) cmm_set_timer(); @@ -178,14 +174,12 @@ cmm_thread(void *dummy) return 0; } -static void -cmm_kick_thread(void) +static void cmm_kick_thread(void) { wake_up(&cmm_thread_wait); } -static void -cmm_set_timer(void) +static void cmm_set_timer(void) { if (cmm_timed_pages_target <= 0 || cmm_timeout_seconds <= 0) { if (timer_pending(&cmm_timer)) @@ -202,8 +196,7 @@ cmm_set_timer(void) add_timer(&cmm_timer); } -static void -cmm_timer_fn(unsigned long ignored) +static void cmm_timer_fn(unsigned long ignored) { long nr; @@ -216,57 +209,49 @@ cmm_timer_fn(unsigned long ignored) cmm_set_timer(); } -void -cmm_set_pages(long nr) +static void cmm_set_pages(long nr) { cmm_pages_target = nr; cmm_kick_thread(); } -long -cmm_get_pages(void) +static long cmm_get_pages(void) { return cmm_pages; } -void -cmm_add_timed_pages(long nr) +static void cmm_add_timed_pages(long nr) { cmm_timed_pages_target += nr; cmm_kick_thread(); } -long -cmm_get_timed_pages(void) +static long cmm_get_timed_pages(void) { return cmm_timed_pages; } -void -cmm_set_timeout(long nr, long seconds) +static void cmm_set_timeout(long nr, long seconds) { cmm_timeout_pages = nr; cmm_timeout_seconds = seconds; cmm_set_timer(); } -static int -cmm_skip_blanks(char *cp, char **endp) +static int cmm_skip_blanks(char *cp, char **endp) { char *str; - for (str = cp; *str == ' ' || *str == '\t'; str++); + for (str = cp; *str == ' ' || *str == '\t'; str++) + ; *endp = str; return str != cp; } -#ifdef CONFIG_CMM_PROC - static struct ctl_table cmm_table[]; -static int -cmm_pages_handler(ctl_table *ctl, int write, - void __user *buffer, size_t *lenp, loff_t *ppos) +static int cmm_pages_handler(ctl_table *ctl, int write, void __user *buffer, + size_t *lenp, loff_t *ppos) { char buf[16], *p; long nr; @@ -305,9 +290,8 @@ cmm_pages_handler(ctl_table *ctl, int write, return 0; } -static int -cmm_timeout_handler(ctl_table *ctl, int write, - void __user *buffer, size_t *lenp, loff_t *ppos) +static int cmm_timeout_handler(ctl_table *ctl, int write, void __user *buffer, + size_t *lenp, loff_t *ppos) { char buf[64], *p; long nr, seconds; @@ -370,12 +354,10 @@ static struct ctl_table cmm_dir_table[] = { }, { } }; -#endif #ifdef CONFIG_CMM_IUCV #define SMSG_PREFIX "CMM" -static void -cmm_smsg_target(const char *from, char *msg) +static void cmm_smsg_target(const char *from, char *msg) { long nr, seconds; @@ -445,16 +427,13 @@ static struct notifier_block cmm_power_notifier = { .notifier_call = cmm_power_event, }; -static int -cmm_init (void) +static int cmm_init(void) { int rc = -ENOMEM; -#ifdef CONFIG_CMM_PROC cmm_sysctl_header = register_sysctl_table(cmm_dir_table); if (!cmm_sysctl_header) goto out_sysctl; -#endif #ifdef CONFIG_CMM_IUCV rc = smsg_register_callback(SMSG_PREFIX, cmm_smsg_target); if (rc < 0) @@ -466,8 +445,6 @@ cmm_init (void) rc = register_pm_notifier(&cmm_power_notifier); if (rc) goto out_pm; - init_waitqueue_head(&cmm_thread_wait); - init_timer(&cmm_timer); cmm_thread_ptr = kthread_run(cmm_thread, NULL, "cmmthread"); rc = IS_ERR(cmm_thread_ptr) ? PTR_ERR(cmm_thread_ptr) : 0; if (rc) @@ -483,36 +460,26 @@ out_oom_notify: smsg_unregister_callback(SMSG_PREFIX, cmm_smsg_target); out_smsg: #endif -#ifdef CONFIG_CMM_PROC unregister_sysctl_table(cmm_sysctl_header); out_sysctl: -#endif + del_timer_sync(&cmm_timer); return rc; } +module_init(cmm_init); -static void -cmm_exit(void) +static void cmm_exit(void) { - kthread_stop(cmm_thread_ptr); - unregister_pm_notifier(&cmm_power_notifier); - unregister_oom_notifier(&cmm_oom_nb); - cmm_free_pages(cmm_pages, &cmm_pages, &cmm_page_list); - cmm_free_pages(cmm_timed_pages, &cmm_timed_pages, &cmm_timed_page_list); -#ifdef CONFIG_CMM_PROC unregister_sysctl_table(cmm_sysctl_header); -#endif #ifdef CONFIG_CMM_IUCV smsg_unregister_callback(SMSG_PREFIX, cmm_smsg_target); #endif + unregister_pm_notifier(&cmm_power_notifier); + unregister_oom_notifier(&cmm_oom_nb); + kthread_stop(cmm_thread_ptr); + del_timer_sync(&cmm_timer); + cmm_free_pages(cmm_pages, &cmm_pages, &cmm_page_list); + cmm_free_pages(cmm_timed_pages, &cmm_timed_pages, &cmm_timed_page_list); } - -module_init(cmm_init); module_exit(cmm_exit); -EXPORT_SYMBOL(cmm_set_pages); -EXPORT_SYMBOL(cmm_get_pages); -EXPORT_SYMBOL(cmm_add_timed_pages); -EXPORT_SYMBOL(cmm_get_timed_pages); -EXPORT_SYMBOL(cmm_set_timeout); - MODULE_LICENSE("GPL"); diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c index 6409fd57eb04..3cc95dd0a3a6 100644 --- a/arch/s390/mm/extmem.c +++ b/arch/s390/mm/extmem.c @@ -105,7 +105,7 @@ static int dcss_set_subcodes(void) { #ifdef CONFIG_64BIT - char *name = kmalloc(8 * sizeof(char), GFP_DMA); + char *name = kmalloc(8 * sizeof(char), GFP_KERNEL | GFP_DMA); unsigned long rx, ry; int rc; @@ -252,12 +252,13 @@ dcss_diag_translate_rc (int vm_rc) { static int query_segment_type (struct dcss_segment *seg) { - struct qin64 *qin = kmalloc (sizeof(struct qin64), GFP_DMA); - struct qout64 *qout = kmalloc (sizeof(struct qout64), GFP_DMA); - - int diag_cc, rc, i; unsigned long dummy, vmrc; + int diag_cc, rc, i; + struct qout64 *qout; + struct qin64 *qin; + qin = kmalloc(sizeof(*qin), GFP_KERNEL | GFP_DMA); + qout = kmalloc(sizeof(*qout), GFP_KERNEL | GFP_DMA); if ((qin == NULL) || (qout == NULL)) { rc = -ENOMEM; goto out_free; @@ -286,7 +287,7 @@ query_segment_type (struct dcss_segment *seg) copy data for the new format. */ if (segext_scode == DCSS_SEGEXT) { struct qout64_old *qout_old; - qout_old = kzalloc(sizeof(struct qout64_old), GFP_DMA); + qout_old = kzalloc(sizeof(*qout_old), GFP_KERNEL | GFP_DMA); if (qout_old == NULL) { rc = -ENOMEM; goto out_free; @@ -407,11 +408,11 @@ segment_overlaps_others (struct dcss_segment *seg) static int __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long *end) { - struct dcss_segment *seg = kmalloc(sizeof(struct dcss_segment), - GFP_DMA); - int rc, diag_cc; unsigned long start_addr, end_addr, dummy; + struct dcss_segment *seg; + int rc, diag_cc; + seg = kmalloc(sizeof(*seg), GFP_KERNEL | GFP_DMA); if (seg == NULL) { rc = -ENOMEM; goto out; diff --git a/arch/score/include/asm/scatterlist.h b/arch/score/include/asm/scatterlist.h index 9f533b8362c7..4fa1a6658215 100644 --- a/arch/score/include/asm/scatterlist.h +++ b/arch/score/include/asm/scatterlist.h @@ -1,6 +1,8 @@ #ifndef _ASM_SCORE_SCATTERLIST_H #define _ASM_SCORE_SCATTERLIST_H +#define ISA_DMA_THRESHOLD (~0UL) + #include <asm-generic/scatterlist.h> #endif /* _ASM_SCORE_SCATTERLIST_H */ diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 0e318c905eea..573fca1fbd9b 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -9,7 +9,7 @@ config SUPERH def_bool y select EMBEDDED select HAVE_CLK - select HAVE_IDE + select HAVE_IDE if HAS_IOPORT select HAVE_LMB select HAVE_OPROFILE select HAVE_GENERIC_DMA_COHERENT @@ -174,6 +174,9 @@ config ARCH_HAS_DEFAULT_IDLE config ARCH_HAS_CPU_IDLE_WAIT def_bool y +config NO_IOPORT + bool + config IO_TRAPPED bool @@ -186,6 +189,9 @@ config DMA_NONCOHERENT config NEED_DMA_MAP_STATE def_bool DMA_NONCOHERENT +config NEED_SG_DMA_LENGTH + def_bool y + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -773,6 +779,17 @@ config ENTRY_OFFSET default "0x00010000" if PAGE_SIZE_64KB default "0x00000000" +config ROMIMAGE_MMCIF + bool "Include MMCIF loader in romImage (EXPERIMENTAL)" + depends on CPU_SUBTYPE_SH7724 && EXPERIMENTAL + help + Say Y here to include experimental MMCIF loading code in + romImage. With this enabled it is possible to write the romImage + kernel image to an MMC card and boot the kernel straight from + the reset vector. At reset the processor Mask ROM will load the + first part of the romImage which in turn loads the rest the kernel + image to RAM using the MMCIF hardware block. + choice prompt "Kernel command line" optional diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 938e87d51482..07b35ca2f644 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -154,6 +154,7 @@ config SH_SDK7786 bool "SDK7786" depends on CPU_SUBTYPE_SH7786 select SYS_SUPPORTS_PCI + select NO_IOPORT if !PCI help Select SDK7786 if configuring for a Renesas Technology Europe SH7786-65nm board. @@ -190,6 +191,7 @@ config SH_URQUELL depends on CPU_SUBTYPE_SH7786 select ARCH_REQUIRE_GPIOLIB select SYS_SUPPORTS_PCI + select NO_IOPORT if !PCI config SH_MIGOR bool "Migo-R" @@ -286,6 +288,7 @@ config SH_LBOX_RE2 config SH_X3PROTO bool "SH-X3 Prototype board" depends on CPU_SUBTYPE_SHX3 + select NO_IOPORT if !PCI config SH_MAGIC_PANEL_R2 bool "Magic Panel R2" diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c index 57e37e284208..3a170bd3f3d0 100644 --- a/arch/sh/boards/mach-ap325rxa/setup.c +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -328,7 +328,7 @@ static struct soc_camera_platform_info camera_info = { .set_capture = camera_set_capture, }; -struct soc_camera_link camera_link = { +static struct soc_camera_link camera_link = { .bus_id = 0, .add_device = ap325rxa_camera_add, .del_device = ap325rxa_camera_del, diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 62123885a6fa..be1d114d3a43 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -11,6 +11,9 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> +#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> #include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/interrupt.h> @@ -25,7 +28,6 @@ #include <linux/mmc/host.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <video/sh_mobile_lcdc.h> #include <sound/sh_fsi.h> #include <media/sh_mobile_ceu.h> @@ -138,7 +140,7 @@ static struct resource sh_eth_resources[] = { }, }; -struct sh_eth_plat_data sh_eth_plat = { +static struct sh_eth_plat_data sh_eth_plat = { .phy = 0x1f, /* SMSC LAN8700 */ .edmac_endian = EDMAC_LITTLE_ENDIAN, .ether_link_active_low = 1 @@ -158,7 +160,7 @@ static struct platform_device sh_eth_device = { }; /* USB0 host */ -void usb0_port_power(int port, int power) +static void usb0_port_power(int port, int power) { gpio_set_value(GPIO_PTB4, power); } @@ -194,7 +196,7 @@ static struct platform_device usb0_host_device = { }; /* USB1 host/function */ -void usb1_port_power(int port, int power) +static void usb1_port_power(int port, int power) { gpio_set_value(GPIO_PTB5, power); } @@ -420,7 +422,7 @@ static int ts_init(void) return 0; } -struct tsc2007_platform_data tsc2007_info = { +static struct tsc2007_platform_data tsc2007_info = { .model = 2007, .x_plate_ohms = 180, .get_pendown_state = ts_get_pendown_state, @@ -435,14 +437,16 @@ static struct i2c_board_info ts_i2c_clients = { }; #ifdef CONFIG_MFD_SH_MOBILE_SDHI -/* SHDI0 */ +/* SDHI0 */ static void sdhi0_set_pwr(struct platform_device *pdev, int state) { gpio_set_value(GPIO_PTB6, state); } static struct sh_mobile_sdhi_info sdhi0_info = { - .set_pwr = sdhi0_set_pwr, + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .set_pwr = sdhi0_set_pwr, }; static struct resource sdhi0_resources[] = { @@ -471,14 +475,17 @@ static struct platform_device sdhi0_device = { }, }; -/* SHDI1 */ +#if !defined(CONFIG_MMC_SH_MMCIF) +/* SDHI1 */ static void sdhi1_set_pwr(struct platform_device *pdev, int state) { gpio_set_value(GPIO_PTB7, state); } static struct sh_mobile_sdhi_info sdhi1_info = { - .set_pwr = sdhi1_set_pwr, + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, + .set_pwr = sdhi1_set_pwr, }; static struct resource sdhi1_resources[] = { @@ -506,6 +513,7 @@ static struct platform_device sdhi1_device = { .hwblk_id = HWBLK_SDHI1, }, }; +#endif /* CONFIG_MMC_SH_MMCIF */ #else @@ -715,7 +723,7 @@ static struct clk fsimckb_clk = { .rate = 0, /* unknown */ }; -struct sh_fsi_platform_info fsi_info = { +static struct sh_fsi_platform_info fsi_info = { .portb_flags = SH_FSI_BRS_INV | SH_FSI_OUT_SLAVE_MODE | SH_FSI_IN_SLAVE_MODE | @@ -769,6 +777,103 @@ static struct platform_device irda_device = { .resource = irda_resources, }; +#include <media/ak881x.h> +#include <media/sh_vou.h> + +static struct ak881x_pdata ak881x_pdata = { + .flags = AK881X_IF_MODE_SLAVE, +}; + +static struct i2c_board_info ak8813 = { + I2C_BOARD_INFO("ak8813", 0x20), + .platform_data = &ak881x_pdata, +}; + +static struct sh_vou_pdata sh_vou_pdata = { + .bus_fmt = SH_VOU_BUS_8BIT, + .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, + .board_info = &ak8813, + .i2c_adap = 0, + .module_name = "ak881x", +}; + +static struct resource sh_vou_resources[] = { + [0] = { + .start = 0xfe960000, + .end = 0xfe962043, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 55, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vou_device = { + .name = "sh-vou", + .id = -1, + .num_resources = ARRAY_SIZE(sh_vou_resources), + .resource = sh_vou_resources, + .dev = { + .platform_data = &sh_vou_pdata, + }, + .archdata = { + .hwblk_id = HWBLK_VOU, + }, +}; + +#if defined(CONFIG_MMC_SH_MMCIF) +/* SH_MMCIF */ +static void mmcif_set_pwr(struct platform_device *pdev, int state) +{ + gpio_set_value(GPIO_PTB7, state); +} + +static void mmcif_down_pwr(struct platform_device *pdev) +{ + gpio_set_value(GPIO_PTB7, 0); +} + +static struct resource sh_mmcif_resources[] = { + [0] = { + .name = "SH_MMCIF", + .start = 0xA4CA0000, + .end = 0xA4CA00FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* MMC2I */ + .start = 29, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* MMC3I */ + .start = 30, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .set_pwr = mmcif_set_pwr, + .down_pwr = mmcif_down_pwr, + .sup_pclk = 0, /* SH7724: Max Pclk/2 */ + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NEEDS_POLL, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; +#endif + static struct platform_device *ecovec_devices[] __initdata = { &heartbeat_device, &nor_flash_device, @@ -781,7 +886,9 @@ static struct platform_device *ecovec_devices[] __initdata = { &keysc_device, #ifdef CONFIG_MFD_SH_MOBILE_SDHI &sdhi0_device, +#if !defined(CONFIG_MMC_SH_MMCIF) &sdhi1_device, +#endif #else &msiof0_device, #endif @@ -790,6 +897,10 @@ static struct platform_device *ecovec_devices[] __initdata = { &camera_devices[2], &fsi_device, &irda_device, + &vou_device, +#if defined(CONFIG_MMC_SH_MMCIF) + &sh_mmcif_device, +#endif }; #ifdef CONFIG_I2C @@ -1083,6 +1194,7 @@ static int __init arch_setup(void) gpio_request(GPIO_PTB6, NULL); gpio_direction_output(GPIO_PTB6, 0); +#if !defined(CONFIG_MMC_SH_MMCIF) /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ gpio_request(GPIO_FN_SDHI1CD, NULL); gpio_request(GPIO_FN_SDHI1WP, NULL); @@ -1097,6 +1209,7 @@ static int __init arch_setup(void) /* I/O buffer drive ability is high for SDHI1 */ __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); +#endif /* CONFIG_MMC_SH_MMCIF */ #else /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ gpio_request(GPIO_FN_MSIOF0_TXD, NULL); @@ -1172,6 +1285,25 @@ static int __init arch_setup(void) gpio_request(GPIO_PTU5, NULL); gpio_direction_output(GPIO_PTU5, 0); +#if defined(CONFIG_MMC_SH_MMCIF) + /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */ + gpio_request(GPIO_FN_MMC_D7, NULL); + gpio_request(GPIO_FN_MMC_D6, NULL); + gpio_request(GPIO_FN_MMC_D5, NULL); + gpio_request(GPIO_FN_MMC_D4, NULL); + gpio_request(GPIO_FN_MMC_D3, NULL); + gpio_request(GPIO_FN_MMC_D2, NULL); + gpio_request(GPIO_FN_MMC_D1, NULL); + gpio_request(GPIO_FN_MMC_D0, NULL); + gpio_request(GPIO_FN_MMC_CLK, NULL); + gpio_request(GPIO_FN_MMC_CMD, NULL); + gpio_request(GPIO_PTB7, NULL); + gpio_direction_output(GPIO_PTB7, 0); + + /* I/O buffer drive ability is high for MMCIF */ + __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); +#endif + /* enable I2C device */ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); @@ -1179,6 +1311,38 @@ static int __init arch_setup(void) i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices)); + /* VOU */ + gpio_request(GPIO_FN_DV_D15, NULL); + gpio_request(GPIO_FN_DV_D14, NULL); + gpio_request(GPIO_FN_DV_D13, NULL); + gpio_request(GPIO_FN_DV_D12, NULL); + gpio_request(GPIO_FN_DV_D11, NULL); + gpio_request(GPIO_FN_DV_D10, NULL); + gpio_request(GPIO_FN_DV_D9, NULL); + gpio_request(GPIO_FN_DV_D8, NULL); + gpio_request(GPIO_FN_DV_CLKI, NULL); + gpio_request(GPIO_FN_DV_CLK, NULL); + gpio_request(GPIO_FN_DV_VSYNC, NULL); + gpio_request(GPIO_FN_DV_HSYNC, NULL); + + /* AK8813 power / reset sequence */ + gpio_request(GPIO_PTG4, NULL); + gpio_request(GPIO_PTU3, NULL); + /* Reset */ + gpio_direction_output(GPIO_PTG4, 0); + /* Power down */ + gpio_direction_output(GPIO_PTU3, 1); + + udelay(10); + + /* Power up, reset */ + gpio_set_value(GPIO_PTU3, 0); + + udelay(10); + + /* Remove reset */ + gpio_set_value(GPIO_PTG4, 1); + return platform_add_devices(ecovec_devices, ARRAY_SIZE(ecovec_devices)); } diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c index b2cd0ed8664e..68994a163f6c 100644 --- a/arch/sh/boards/mach-kfr2r09/setup.c +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -10,6 +10,8 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/interrupt.h> +#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mfd/tmio.h> #include <linux/mtd/physmap.h> #include <linux/mtd/onenand.h> #include <linux/delay.h> @@ -356,10 +358,19 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = { }, }; +static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, +}; + static struct platform_device kfr2r09_sh_sdhi0_device = { .name = "sh_mobile_sdhi", .num_resources = ARRAY_SIZE(kfr2r09_sh_sdhi0_resources), .resource = kfr2r09_sh_sdhi0_resources, + .dev = { + .platform_data = &sh7724_sdhi0_data, + }, .archdata = { .hwblk_id = HWBLK_SDHI0, }, diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c index 7da0fc94a01e..662debe4ead2 100644 --- a/arch/sh/boards/mach-migor/setup.c +++ b/arch/sh/boards/mach-migor/setup.c @@ -12,6 +12,7 @@ #include <linux/interrupt.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> +#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/mtd/nand.h> #include <linux/i2c.h> @@ -180,7 +181,7 @@ static int migor_nand_flash_ready(struct mtd_info *mtd) return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ } -struct platform_nand_data migor_nand_flash_data = { +static struct platform_nand_data migor_nand_flash_data = { .chip = { .nr_chips = 1, .partitions = migor_nand_flash_partitions, @@ -402,10 +403,18 @@ static struct resource sdhi_cn9_resources[] = { }, }; +static struct sh_mobile_sdhi_info sh7724_sdhi_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +}; + static struct platform_device sdhi_cn9_device = { .name = "sh_mobile_sdhi", .num_resources = ARRAY_SIZE(sdhi_cn9_resources), .resource = sdhi_cn9_resources, + .dev = { + .platform_data = &sh7724_sdhi_data, + }, .archdata = { .hwblk_id = HWBLK_SDHI, }, diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index e74ae7b0d8bf..552ebd9ba82b 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -14,6 +14,7 @@ #include <linux/device.h> #include <linux/interrupt.h> #include <linux/platform_device.h> +#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mtd/physmap.h> #include <linux/delay.h> #include <linux/smc91x.h> @@ -282,7 +283,7 @@ static struct clk fsimcka_clk = { }; /* change J20, J21, J22 pin to 1-2 connection to use slave mode */ -struct sh_fsi_platform_info fsi_info = { +static struct sh_fsi_platform_info fsi_info = { .porta_flags = SH_FSI_BRS_INV | SH_FSI_OUT_SLAVE_MODE | SH_FSI_IN_SLAVE_MODE | @@ -370,7 +371,7 @@ static struct resource sh_eth_resources[] = { }, }; -struct sh_eth_plat_data sh_eth_plat = { +static struct sh_eth_plat_data sh_eth_plat = { .phy = 0x1f, /* SMSC LAN8187 */ .edmac_endian = EDMAC_LITTLE_ENDIAN, }; @@ -462,11 +463,19 @@ static struct resource sdhi0_cn7_resources[] = { }, }; +static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +}; + static struct platform_device sdhi0_cn7_device = { .name = "sh_mobile_sdhi", .id = 0, .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), .resource = sdhi0_cn7_resources, + .dev = { + .platform_data = &sh7724_sdhi0_data, + }, .archdata = { .hwblk_id = HWBLK_SDHI0, }, @@ -485,11 +494,19 @@ static struct resource sdhi1_cn8_resources[] = { }, }; +static struct sh_mobile_sdhi_info sh7724_sdhi1_data = { + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, +}; + static struct platform_device sdhi1_cn8_device = { .name = "sh_mobile_sdhi", .id = 1, .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), .resource = sdhi1_cn8_resources, + .dev = { + .platform_data = &sh7724_sdhi1_data, + }, .archdata = { .hwblk_id = HWBLK_SDHI1, }, @@ -515,6 +532,52 @@ static struct platform_device irda_device = { .resource = irda_resources, }; +#include <media/ak881x.h> +#include <media/sh_vou.h> + +static struct ak881x_pdata ak881x_pdata = { + .flags = AK881X_IF_MODE_SLAVE, +}; + +static struct i2c_board_info ak8813 = { + /* With open J18 jumper address is 0x21 */ + I2C_BOARD_INFO("ak8813", 0x20), + .platform_data = &ak881x_pdata, +}; + +static struct sh_vou_pdata sh_vou_pdata = { + .bus_fmt = SH_VOU_BUS_8BIT, + .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, + .board_info = &ak8813, + .i2c_adap = 0, + .module_name = "ak881x", +}; + +static struct resource sh_vou_resources[] = { + [0] = { + .start = 0xfe960000, + .end = 0xfe962043, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 55, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vou_device = { + .name = "sh-vou", + .id = -1, + .num_resources = ARRAY_SIZE(sh_vou_resources), + .resource = sh_vou_resources, + .dev = { + .platform_data = &sh_vou_pdata, + }, + .archdata = { + .hwblk_id = HWBLK_VOU, + }, +}; + static struct platform_device *ms7724se_devices[] __initdata = { &heartbeat_device, &smc91x_eth_device, @@ -530,6 +593,7 @@ static struct platform_device *ms7724se_devices[] __initdata = { &sdhi0_cn7_device, &sdhi1_cn8_device, &irda_device, + &vou_device, }; /* I2C device */ @@ -614,6 +678,7 @@ static int __init devices_setup(void) { u16 sw = __raw_readw(SW4140); /* select camera, monitor */ struct clk *clk; + u16 fpga_out; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | @@ -623,14 +688,26 @@ static int __init devices_setup(void) &ms7724se_sdram_leave_start, &ms7724se_sdram_leave_end); /* Reset Release */ - __raw_writew(__raw_readw(FPGA_OUT) & - ~((1 << 1) | /* LAN */ - (1 << 6) | /* VIDEO DAC */ - (1 << 7) | /* AK4643 */ - (1 << 8) | /* IrDA */ - (1 << 12) | /* USB0 */ - (1 << 14)), /* RMII */ - FPGA_OUT); + fpga_out = __raw_readw(FPGA_OUT); + /* bit4: NTSC_PDN, bit5: NTSC_RESET */ + fpga_out &= ~((1 << 1) | /* LAN */ + (1 << 4) | /* AK8813 PDN */ + (1 << 5) | /* AK8813 RESET */ + (1 << 6) | /* VIDEO DAC */ + (1 << 7) | /* AK4643 */ + (1 << 8) | /* IrDA */ + (1 << 12) | /* USB0 */ + (1 << 14)); /* RMII */ + __raw_writew(fpga_out | (1 << 4), FPGA_OUT); + + udelay(10); + + /* AK8813 RESET */ + __raw_writew(fpga_out | (1 << 5), FPGA_OUT); + + udelay(10); + + __raw_writew(fpga_out, FPGA_OUT); /* turn on USB clocks, use external clock */ __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); @@ -862,6 +939,20 @@ static int __init devices_setup(void) lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; } + /* VOU */ + gpio_request(GPIO_FN_DV_D15, NULL); + gpio_request(GPIO_FN_DV_D14, NULL); + gpio_request(GPIO_FN_DV_D13, NULL); + gpio_request(GPIO_FN_DV_D12, NULL); + gpio_request(GPIO_FN_DV_D11, NULL); + gpio_request(GPIO_FN_DV_D10, NULL); + gpio_request(GPIO_FN_DV_D9, NULL); + gpio_request(GPIO_FN_DV_D8, NULL); + gpio_request(GPIO_FN_DV_CLKI, NULL); + gpio_request(GPIO_FN_DV_CLK, NULL); + gpio_request(GPIO_FN_DV_VSYNC, NULL); + gpio_request(GPIO_FN_DV_HSYNC, NULL); + return platform_add_devices(ms7724se_devices, ARRAY_SIZE(ms7724se_devices)); } diff --git a/arch/sh/boot/compressed/vmlinux.scr b/arch/sh/boot/compressed/vmlinux.scr index f02382ae5c48..862d74808236 100644 --- a/arch/sh/boot/compressed/vmlinux.scr +++ b/arch/sh/boot/compressed/vmlinux.scr @@ -1,6 +1,6 @@ SECTIONS { - .rodata.compressed : { + .rodata..compressed : { input_len = .; LONG(input_data_end - input_data) input_data = .; *(.data) diff --git a/arch/sh/boot/romimage/Makefile b/arch/sh/boot/romimage/Makefile index f473a24a2d92..2216ee57f251 100644 --- a/arch/sh/boot/romimage/Makefile +++ b/arch/sh/boot/romimage/Makefile @@ -1,16 +1,21 @@ # # linux/arch/sh/boot/romimage/Makefile # -# create an image suitable for burning to flash from zImage +# create an romImage file suitable for burning to flash/mmc from zImage # targets := vmlinux head.o zeropage.bin piggy.o +load-y := 0 -OBJECTS = $(obj)/head.o -LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext 0 -e romstart \ +mmcif-load-$(CONFIG_CPU_SUBTYPE_SH7724) := 0xe5200000 # ILRAM +mmcif-obj-$(CONFIG_CPU_SUBTYPE_SH7724) := $(obj)/mmcif-sh7724.o +load-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-load-y) +obj-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-obj-y) + +LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(load-y) -e romstart \ -T $(obj)/../../kernel/vmlinux.lds -$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE +$(obj)/vmlinux: $(obj)/head.o $(obj-y) $(obj)/piggy.o FORCE $(call if_changed,ld) @: diff --git a/arch/sh/boot/romimage/head.S b/arch/sh/boot/romimage/head.S index 93e779a405ec..4671d1b82150 100644 --- a/arch/sh/boot/romimage/head.S +++ b/arch/sh/boot/romimage/head.S @@ -12,8 +12,40 @@ romstart: /* include board specific setup code */ #include <mach/romimage.h> +#ifdef CONFIG_ROMIMAGE_MMCIF + /* load the romImage to above the empty zero page */ + mov.l empty_zero_page_dst, r4 + mov.l empty_zero_page_dst_adj, r5 + add r5, r4 + mov.l bytes_to_load, r5 + mov.l loader_function, r7 + jsr @r7 + mov r4, r15 + + mov.l empty_zero_page_dst, r4 + mov.l empty_zero_page_dst_adj, r5 + add r5, r4 + mov.l loaded_code_offs, r5 + add r5, r4 + jmp @r4 + nop + + .balign 4 +empty_zero_page_dst_adj: + .long PAGE_SIZE +bytes_to_load: + .long end_data - romstart +loader_function: + .long mmcif_loader +loaded_code_offs: + .long loaded_code - romstart +loaded_code: +#endif /* CONFIG_ROMIMAGE_MMCIF */ + /* copy the empty_zero_page contents to where vmlinux expects it */ - mova empty_zero_page_src, r0 + mova extra_data_pos, r0 + mov.l extra_data_size, r1 + add r1, r0 mov.l empty_zero_page_dst, r1 mov #(PAGE_SHIFT - 4), r4 mov #1, r3 @@ -37,7 +69,9 @@ romstart: mov #PAGE_SHIFT, r4 mov #1, r1 shld r4, r1 - mova empty_zero_page_src, r0 + mova extra_data_pos, r0 + add r1, r0 + mov.l extra_data_size, r1 add r1, r0 jmp @r0 nop @@ -45,4 +79,6 @@ romstart: .align 2 empty_zero_page_dst: .long _text -empty_zero_page_src: +extra_data_pos: +extra_data_size: + .long zero_page_pos - extra_data_pos diff --git a/arch/sh/boot/romimage/mmcif-sh7724.c b/arch/sh/boot/romimage/mmcif-sh7724.c new file mode 100644 index 000000000000..14863d7292cb --- /dev/null +++ b/arch/sh/boot/romimage/mmcif-sh7724.c @@ -0,0 +1,72 @@ +/* + * sh7724 MMCIF loader + * + * Copyright (C) 2010 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/mmc/sh_mmcif.h> +#include <mach/romimage.h> + +#define MMCIF_BASE (void __iomem *)0xa4ca0000 + +#define MSTPCR2 0xa4150038 +#define PTWCR 0xa4050146 +#define PTXCR 0xa4050148 +#define PSELA 0xa405014e +#define PSELE 0xa4050156 +#define HIZCRC 0xa405015c +#define DRVCRA 0xa405018a + +enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT, + MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE }; + +/* SH7724 specific MMCIF loader + * + * loads the romImage from an MMC card starting from block 512 + * use the following line to write the romImage to an MMC card + * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512 + */ +asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) +{ + mmcif_update_progress(MMCIF_PROGRESS_ENTER); + + /* enable clock to the MMCIF hardware block */ + __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); + + /* setup pins D7-D0 */ + __raw_writew(0x0000, PTWCR); + + /* setup pins MMC_CLK, MMC_CMD */ + __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR); + + /* select D3-D0 pin function */ + __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA); + + /* select D7-D4 pin function */ + __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE); + + /* disable Hi-Z for the MMC pins */ + __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC); + + /* high drive capability for MMC pins */ + __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); + + mmcif_update_progress(MMCIF_PROGRESS_INIT); + + /* setup MMCIF hardware */ + sh_mmcif_boot_init(MMCIF_BASE); + + mmcif_update_progress(MMCIF_PROGRESS_LOAD); + + /* load kernel via MMCIF interface */ + sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes); + + /* disable clock to the MMCIF hardware block */ + __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); + + mmcif_update_progress(MMCIF_PROGRESS_DONE); +} diff --git a/arch/sh/boot/romimage/vmlinux.scr b/arch/sh/boot/romimage/vmlinux.scr index 287c08f8b4bb..590394e2f5f2 100644 --- a/arch/sh/boot/romimage/vmlinux.scr +++ b/arch/sh/boot/romimage/vmlinux.scr @@ -1,6 +1,8 @@ SECTIONS { .text : { + zero_page_pos = .; *(.data) + end_data = .; } } diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig index e9af616b2160..71f39c71b04b 100644 --- a/arch/sh/configs/sh7785lcr_32bit_defconfig +++ b/arch/sh/configs/sh7785lcr_32bit_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.34-rc5 -# Tue May 18 17:22:09 2010 +# Linux kernel version: 2.6.34 +# Mon May 24 08:33:02 2010 # CONFIG_SUPERH=y CONFIG_SUPERH32=y @@ -76,7 +76,7 @@ CONFIG_RCU_FANOUT=32 # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_BUF_SHIFT=16 # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set @@ -111,18 +111,17 @@ CONFIG_PERF_USE_VMALLOC=y # CONFIG_PERF_EVENTS=y CONFIG_PERF_COUNTERS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y -CONFIG_COMPAT_BRK=y +# CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y +# CONFIG_OPROFILE is not set CONFIG_HAVE_OPROFILE=y -CONFIG_KPROBES=y -CONFIG_KRETPROBES=y +# CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y @@ -130,6 +129,7 @@ CONFIG_HAVE_DMA_ATTRS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y # # GCOV-based kernel profiling @@ -243,8 +243,9 @@ CONFIG_PAGE_OFFSET=0x80000000 CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_MEMORY_START=0x40000000 CONFIG_MEMORY_SIZE=0x20000000 -CONFIG_29BIT=y -# CONFIG_PMB is not set +# CONFIG_29BIT is not set +CONFIG_32BIT=y +CONFIG_PMB=y CONFIG_X2TLB=y CONFIG_VSYSCALL=y # CONFIG_NUMA is not set @@ -262,9 +263,9 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_HUGETLB_PAGE_SIZE_64K=y +# CONFIG_HUGETLB_PAGE_SIZE_64K is not set # CONFIG_HUGETLB_PAGE_SIZE_256K is not set -# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set +CONFIG_HUGETLB_PAGE_SIZE_1MB=y # CONFIG_HUGETLB_PAGE_SIZE_4MB is not set # CONFIG_HUGETLB_PAGE_SIZE_64MB is not set # CONFIG_HUGETLB_PAGE_SIZE_512MB is not set @@ -276,7 +277,7 @@ CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_STATIC=y # CONFIG_MEMORY_HOTPLUG is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTLOCK_CPUS=999999 CONFIG_MIGRATION=y # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 @@ -298,7 +299,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_SH_FPU=y CONFIG_SH_STORE_QUEUES=y -# CONFIG_SPECULATIVE_EXECUTION is not set +CONFIG_SPECULATIVE_EXECUTION=y CONFIG_CPU_HAS_INTEVT=y CONFIG_CPU_HAS_SR_RB=y CONFIG_CPU_HAS_FPU=y @@ -308,7 +309,7 @@ CONFIG_CPU_HAS_FPU=y # # CONFIG_SH_HIGHLANDER is not set CONFIG_SH_SH7785LCR=y -CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS=y +# CONFIG_SH_SH7785LCR_PT is not set # # Timer and clock configuration @@ -371,7 +372,7 @@ CONFIG_SECCOMP=y # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_GUSA=y -# CONFIG_INTC_USERIMASK is not set +CONFIG_INTC_USERIMASK=y # # Boot options @@ -389,6 +390,7 @@ CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCIEPORTBUS is not set # CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_DEBUG=y # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set # CONFIG_PCCARD is not set @@ -465,6 +467,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +# CONFIG_L2TP is not set # CONFIG_BRIDGE is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set @@ -485,8 +488,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NET_TCPPROBE is not set -# CONFIG_NET_DROP_MONITOR is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set @@ -499,11 +500,20 @@ CONFIG_WIRELESS=y # # CFG80211 needs to be enabled for MAC80211 # + +# +# Some wireless drivers require a rate control algorithm +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # +# CAIF Support +# +# CONFIG_CAIF is not set + +# # Device Drivers # @@ -514,7 +524,11 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y @@ -537,6 +551,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set # CONFIG_MTD_OOPS is not set # @@ -668,7 +683,9 @@ CONFIG_ATA=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set # CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_INIC162X is not set CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set @@ -683,7 +700,6 @@ CONFIG_SATA_SIL=y # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set # CONFIG_SATA_VITESSE is not set -# CONFIG_SATA_INIC162X is not set # CONFIG_PATA_ALI is not set # CONFIG_PATA_AMD is not set # CONFIG_PATA_ARTOP is not set @@ -753,8 +769,36 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_ARCNET is not set -# CONFIG_NET_ETHERNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +CONFIG_NET_VENDOR_3COM=y +CONFIG_VORTEX=y +# CONFIG_TYPHOON is not set +# CONFIG_SMC91X is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set @@ -836,6 +880,7 @@ CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -884,6 +929,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # @@ -901,6 +947,8 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set CONFIG_UNIX98_PTYS=y CONFIG_DEVPTS_MULTIPLE_INSTANCES=y # CONFIG_LEGACY_PTYS is not set @@ -1071,7 +1119,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_SIS is not set # CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set +CONFIG_FB_KYRO=y # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VT8623 is not set @@ -1097,15 +1145,15 @@ CONFIG_FB_SM501=y # CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y CONFIG_LOGO_SUPERH_MONO=y CONFIG_LOGO_SUPERH_VGA16=y CONFIG_LOGO_SUPERH_CLUT224=y @@ -1129,15 +1177,18 @@ CONFIG_SND_SEQ_HRTIMER_DEFAULT=y CONFIG_SND_DYNAMIC_MINORS=y # CONFIG_SND_SUPPORT_OLD_API is not set # CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_VERBOSE=y +CONFIG_SND_VMASTER=y CONFIG_SND_RAWMIDI_SEQ=y CONFIG_SND_OPL3_LIB_SEQ=y # CONFIG_SND_OPL4_LIB_SEQ is not set # CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_EMU10K1_SEQ=y CONFIG_SND_MPU401_UART=y CONFIG_SND_OPL3_LIB=y +CONFIG_SND_AC97_CODEC=y # CONFIG_SND_DRIVERS is not set CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set @@ -1172,7 +1223,7 @@ CONFIG_SND_CMIPCI=y # CONFIG_SND_INDIGODJ is not set # CONFIG_SND_INDIGOIOX is not set # CONFIG_SND_INDIGODJX is not set -# CONFIG_SND_EMU10K1 is not set +CONFIG_SND_EMU10K1=y # CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set # CONFIG_SND_ENS1371 is not set @@ -1211,6 +1262,7 @@ CONFIG_SND_USB=y # CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HIDRAW is not set @@ -1226,44 +1278,42 @@ CONFIG_USB_HID=y # Special HID drivers # # CONFIG_HID_3M_PCT is not set -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -# CONFIG_DRAGONRISE_FF is not set -CONFIG_HID_EZKEY=m -CONFIG_HID_KYE=m -CONFIG_HID_GYRATION=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LOGITECH=m -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGIG940_FF is not set -CONFIG_HID_MICROSOFT=m +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MOSART is not set -CONFIG_HID_MONTEREY=m -CONFIG_HID_NTRIG=m +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set # CONFIG_HID_ORTEK is not set -CONFIG_HID_PANTHERLORD=m -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=m +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set # CONFIG_HID_QUANTA is not set -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set # CONFIG_HID_STANTUM is not set -CONFIG_HID_SUNPLUS=m -CONFIG_HID_GREENASIA=m -# CONFIG_GREENASIA_FF is not set -CONFIG_HID_SMARTJOYPLUS=m -# CONFIG_SMARTJOYPLUS_FF is not set -CONFIG_HID_TOPSEED=m +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set -CONFIG_HID_ZEROPLUS=m -# CONFIG_ZEROPLUS_FF is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1276,9 +1326,8 @@ CONFIG_USB=y # Miscellaneous USB options # # CONFIG_USB_DEVICEFS is not set -CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_MON is not set @@ -1290,9 +1339,7 @@ CONFIG_USB_DEVICE_CLASS=y # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set -CONFIG_USB_EHCI_HCD=m -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set @@ -1361,7 +1408,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set @@ -1464,6 +1510,7 @@ CONFIG_DMADEVICES=y # # DMA Devices # +# CONFIG_TIMB_DMA is not set # CONFIG_AUXDISPLAY is not set CONFIG_UIO=m # CONFIG_UIO_CIF is not set @@ -1473,10 +1520,6 @@ CONFIG_UIO=m # CONFIG_UIO_SERCOS3 is not set # CONFIG_UIO_PCI_GENERIC is not set # CONFIG_UIO_NETX is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -1653,63 +1696,75 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y CONFIG_SCHEDSTATS=y -CONFIG_TRACE_IRQFLAGS=y +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set CONFIG_FRAME_POINTER=y +# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FTRACE_NMI_ENTER=y +# CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_RING_BUFFER=y -CONFIG_FTRACE_NMI_ENTER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -CONFIG_FUNCTION_TRACER=y -CONFIG_FUNCTION_GRAPH_TRACER=y -CONFIG_IRQSOFF_TRACER=y -# CONFIG_PREEMPT_TRACER is not set -CONFIG_SCHED_TRACER=y -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_KSYM_TRACER is not set -CONFIG_STACK_TRACER=y -CONFIG_KMEMTRACE=y -CONFIG_WORKQUEUE_TRACER=y -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_DYNAMIC_FTRACE=y -# CONFIG_FUNCTION_PROFILER is not set -CONFIG_FTRACE_MCOUNT_RECORD=y -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set # CONFIG_SH_STANDARD_BIOS is not set -CONFIG_DWARF_UNWINDER=y -CONFIG_MCOUNT=y +# CONFIG_STACK_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_4KSTACKS is not set +CONFIG_DUMP_CODE=y +# CONFIG_DWARF_UNWINDER is not set +# CONFIG_SH_NO_BSS_INIT is not set # # Security options @@ -1820,7 +1875,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # CONFIG_VIRTUALIZATION is not set -CONFIG_BINARY_PRINTF=y +# CONFIG_BINARY_PRINTF is not set # # Library routines diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h index d02c01b3e6b9..6323f864d111 100644 --- a/arch/sh/include/asm/bug.h +++ b/arch/sh/include/asm/bug.h @@ -48,7 +48,7 @@ do { \ "i" (sizeof(struct bug_entry))); \ } while (0) -#define __WARN() \ +#define __WARN_TAINT(taint) \ do { \ __asm__ __volatile__ ( \ "1:\t.short %O0\n" \ @@ -57,7 +57,7 @@ do { \ : "n" (TRAPA_BUG_OPCODE), \ "i" (__FILE__), \ "i" (__LINE__), \ - "i" (BUGFLAG_WARNING), \ + "i" (BUGFLAG_TAINT(taint)), \ "i" (sizeof(struct bug_entry))); \ } while (0) diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index e461d67f03c3..ef9e555aafba 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -14,7 +14,7 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #ifndef __ASSEMBLY__ struct cache_info { diff --git a/arch/sh/include/asm/dmaengine.h b/arch/sh/include/asm/dmaengine.h deleted file mode 100644 index 2a02b611a9ad..000000000000 --- a/arch/sh/include/asm/dmaengine.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Header for the new SH dmaengine driver - * - * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASM_DMAENGINE_H -#define ASM_DMAENGINE_H - -#include <linux/sh_dma.h> - -enum { - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SIUA_TX, - SHDMA_SLAVE_SIUA_RX, - SHDMA_SLAVE_SIUB_TX, - SHDMA_SLAVE_SIUB_RX, -}; - -#endif diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index f689554e17c1..b237d525d592 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -39,6 +39,8 @@ #include <asm/io_generic.h> #include <asm/io_trapped.h> +#ifdef CONFIG_HAS_IOPORT + #define inb(p) sh_mv.mv_inb((p)) #define inw(p) sh_mv.mv_inw((p)) #define inl(p) sh_mv.mv_inl((p)) @@ -60,6 +62,8 @@ #define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) #define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) +#endif + #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) @@ -240,6 +244,8 @@ __BUILD_MEMORY_STRING(q, u64) #define IO_SPACE_LIMIT 0xffffffff +#ifdef CONFIG_HAS_IOPORT + /* * This function provides a method for the generic case where a * board-specific ioport_map simply needs to return the port + some @@ -255,6 +261,8 @@ static inline void __set_io_port_base(unsigned long pbase) #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) +#endif + /* We really want to try and get these to memcpy etc */ void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); void memcpy_toio(volatile void __iomem *, const void *, unsigned long); diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h index bc0218cb72e1..a0b0cf79cf8a 100644 --- a/arch/sh/include/asm/machvec.h +++ b/arch/sh/include/asm/machvec.h @@ -19,6 +19,10 @@ struct sh_machine_vector { const char *mv_name; int mv_nr_irqs; + int (*mv_irq_demux)(int irq); + void (*mv_init_irq)(void); + +#ifdef CONFIG_HAS_IOPORT u8 (*mv_inb)(unsigned long); u16 (*mv_inw)(unsigned long); u32 (*mv_inl)(unsigned long); @@ -40,12 +44,9 @@ struct sh_machine_vector { void (*mv_outsw)(unsigned long, const void *src, unsigned long count); void (*mv_outsl)(unsigned long, const void *src, unsigned long count); - int (*mv_irq_demux)(int irq); - - void (*mv_init_irq)(void); - void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); void (*mv_ioport_unmap)(void __iomem *); +#endif int (*mv_clk_init)(void); int (*mv_mode_pins)(void); diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h index e8d4142baf59..1d95c78808d1 100644 --- a/arch/sh/include/asm/siu.h +++ b/arch/sh/include/asm/siu.h @@ -11,8 +11,6 @@ #ifndef ASM_SIU_H #define ASM_SIU_H -#include <asm/dmaengine.h> - struct device; struct siu_platform { diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h index 48560407cbe1..7a5b8a331b4a 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7722.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h @@ -235,4 +235,19 @@ enum { HWBLK_NR, }; +enum { + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SIUA_TX, + SHDMA_SLAVE_SIUA_RX, + SHDMA_SLAVE_SIUB_TX, + SHDMA_SLAVE_SIUB_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, +}; + #endif /* __ASM_SH7722_H__ */ diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h index 0cd1f71a1116..4c27b68789b3 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7724.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h @@ -9,6 +9,7 @@ * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] * MD8: Test Mode + * BOOT: FBR - Boot Mode (L: MMCIF, H: Area0) */ /* Pin Function Controller: @@ -283,4 +284,23 @@ enum { HWBLK_NR, }; +enum { + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, +}; + #endif /* __ASM_SH7724_H__ */ diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h index 267e24112d82..08fb42269ecd 100644 --- a/arch/sh/include/mach-common/mach/romimage.h +++ b/arch/sh/include/mach-common/mach/romimage.h @@ -1 +1,11 @@ +#ifdef __ASSEMBLY__ + /* do nothing here by default */ + +#else /* __ASSEMBLY__ */ + +extern inline void mmcif_update_progress(int nr) +{ +} + +#endif /* __ASSEMBLY__ */ diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h index 1c8787ecb1c1..1dcf5e6c8d83 100644 --- a/arch/sh/include/mach-ecovec24/mach/romimage.h +++ b/arch/sh/include/mach-ecovec24/mach/romimage.h @@ -1,3 +1,5 @@ +#ifdef __ASSEMBLY__ + /* EcoVec board specific boot code: * converts the "partner-jet-script.txt" script into assembly * the assembly code is the first code to be executed in the romImage @@ -18,3 +20,28 @@ .align 2 1 : .long 0xa8000000 2 : + +#else /* __ASSEMBLY__ */ + +/* Ecovec board specific information: + * + * Set the following to enable MMCIF boot from the MMC card in CN12: + * + * DS1.5 = OFF (SH BOOT pin set to L) + * DS2.6 = OFF (Select MMCIF on CN12 instead of SDHI1) + * DS2.7 = ON (Select MMCIF on CN12 instead of SDHI1) + * + */ +#define HIZCRA 0xa4050158 +#define PGDR 0xa405012c + +extern inline void mmcif_update_progress(int nr) +{ + /* disable Hi-Z for LED pins */ + __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA); + + /* update progress on LED4, LED5, LED6 and LED7 */ + __raw_writeb(1 << (nr - 1), PGDR); +} + +#endif /* __ASSEMBLY__ */ diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h index a110823f2bde..976256a323f2 100644 --- a/arch/sh/include/mach-kfr2r09/mach/romimage.h +++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h @@ -1,3 +1,5 @@ +#ifdef __ASSEMBLY__ + /* kfr2r09 board specific boot code: * converts the "partner-jet-script.txt" script into assembly * the assembly code is the first code to be executed in the romImage @@ -18,3 +20,11 @@ .align 2 1: .long 0xa8000000 2: + +#else /* __ASSEMBLY__ */ + +extern inline void mmcif_update_progress(int nr) +{ +} + +#endif /* __ASSEMBLY__ */ diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index 650b92f00ee5..e25f3c69525d 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -12,7 +12,7 @@ endif CFLAGS_REMOVE_return_address.o = -pg obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ - idle.o io.o io_generic.o irq.o \ + idle.o io.o irq.o \ irq_$(BITS).o machvec.o nmi_debug.o process.o \ process_$(BITS).o ptrace_$(BITS).o \ reboot.o return_address.o \ @@ -39,6 +39,7 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o obj-$(CONFIG_HIBERNATION) += swsusp.o obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o +obj-$(CONFIG_HAS_IOPORT) += io_generic.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index 105a6d41b569..597c9fbe49c6 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c @@ -13,7 +13,6 @@ #include <linux/kernel.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/clk.h> #include <asm/clkdev.h> #include <asm/clock.h> #include <asm/freq.h> diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 24c6167a7181..156ccc960015 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -17,7 +17,6 @@ #include <linux/usb/m66592.h> #include <asm/clock.h> -#include <asm/dmaengine.h> #include <asm/mmzone.h> #include <asm/siu.h> @@ -75,6 +74,16 @@ static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { .addr = 0xa454c094, .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), .mid_rid = 0xb6, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0x04ce0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0x04ce0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, }, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 89fe16d20fdb..79c556e56262 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -18,19 +18,103 @@ #include <linux/mm.h> #include <linux/serial_sci.h> #include <linux/uio_driver.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> #include <linux/io.h> #include <linux/notifier.h> #include <asm/suspend.h> #include <asm/clock.h> -#include <asm/dmaengine.h> #include <asm/mmzone.h> #include <cpu/dma-register.h> #include <cpu/sh7724.h> /* DMA */ +static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SCIF0_TX, + .addr = 0xffe0000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, { + .slave_id = SHDMA_SLAVE_SCIF0_RX, + .addr = 0xffe00014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_TX, + .addr = 0xffe1000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x25, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_RX, + .addr = 0xffe10014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x26, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0xffe2000c, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0xffe20014, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_TX, + .addr = 0xa4e30020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2d, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_RX, + .addr = 0xa4e30024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2e, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_TX, + .addr = 0xa4e40020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x31, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_RX, + .addr = 0xa4e40024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x32, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_TX, + .addr = 0xa4e50020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x35, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_RX, + .addr = 0xa4e50024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x36, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0x04ce0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0x04ce0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_TX, + .addr = 0x04cf0030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc9, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_RX, + .addr = 0x04cf0030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xca, + }, +}; + static const struct sh_dmae_channel sh7724_dmae_channels[] = { { .offset = 0, @@ -62,6 +146,8 @@ static const struct sh_dmae_channel sh7724_dmae_channels[] = { static const unsigned int ts_shift[] = TS_SHIFT; static struct sh_dmae_pdata dma_platform_data = { + .slave = sh7724_dmae_slaves, + .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), .channel = sh7724_dmae_channels, .channel_num = ARRAY_SIZE(sh7724_dmae_channels), .ts_low_shift = CHCR_TS_LOW_SHIFT, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index b12f537e4dde..0f414864f76b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -12,10 +12,9 @@ #include <linux/serial.h> #include <linux/io.h> #include <linux/serial_sci.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> -#include <asm/dmaengine.h> - #include <cpu/dma-register.h> static struct plat_sci_port scif0_platform_data = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index f3e3ea0ce050..c9a572bc6dc8 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -13,9 +13,9 @@ #include <linux/serial_sci.h> #include <linux/io.h> #include <linux/mm.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> -#include <asm/dmaengine.h> #include <asm/mmzone.h> #include <cpu/dma-register.h> diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 81657091da46..8797723231ea 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -21,10 +21,10 @@ #include <linux/mm.h> #include <linux/dma-mapping.h> #include <linux/sh_timer.h> +#include <linux/sh_dma.h> #include <linux/sh_intc.h> #include <cpu/dma-register.h> #include <asm/mmzone.h> -#include <asm/dmaengine.h> static struct plat_sci_port scif0_platform_data = { .mapbase = 0xffea0000, diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c index 5ec1d1818691..49c09c7d5b77 100644 --- a/arch/sh/kernel/dwarf.c +++ b/arch/sh/kernel/dwarf.c @@ -49,6 +49,8 @@ static DEFINE_SPINLOCK(dwarf_fde_lock); static struct dwarf_cie *cached_cie; +static unsigned int dwarf_unwinder_ready; + /** * dwarf_frame_alloc_reg - allocate memory for a DWARF register * @frame: the DWARF frame whose list of registers we insert on @@ -582,6 +584,13 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc, unsigned long addr; /* + * If we've been called in to before initialization has + * completed, bail out immediately. + */ + if (!dwarf_unwinder_ready) + return NULL; + + /* * If we're starting at the top of the stack we need get the * contents of a physical register to get the CFA in order to * begin the virtual unwinding of the stack. @@ -845,8 +854,10 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len, rb_link_node(&cie->node, parent, rb_node); rb_insert_color(&cie->node, &cie_root); +#ifdef CONFIG_MODULES if (mod != NULL) list_add_tail(&cie->link, &mod->arch.cie_list); +#endif spin_unlock_irqrestore(&dwarf_cie_lock, flags); @@ -935,8 +946,10 @@ static int dwarf_parse_fde(void *entry, u32 entry_type, rb_link_node(&fde->node, parent, rb_node); rb_insert_color(&fde->node, &fde_root); +#ifdef CONFIG_MODULES if (mod != NULL) list_add_tail(&fde->link, &mod->arch.fde_list); +#endif spin_unlock_irqrestore(&dwarf_fde_lock, flags); @@ -1163,7 +1176,7 @@ void module_dwarf_cleanup(struct module *mod) */ static int __init dwarf_unwinder_init(void) { - int err; + int err = -ENOMEM; dwarf_frame_cachep = kmem_cache_create("dwarf_frames", sizeof(struct dwarf_frame), 0, @@ -1177,11 +1190,15 @@ static int __init dwarf_unwinder_init(void) mempool_alloc_slab, mempool_free_slab, dwarf_frame_cachep); + if (!dwarf_frame_pool) + goto out; dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ, mempool_alloc_slab, mempool_free_slab, dwarf_reg_cachep); + if (!dwarf_reg_pool) + goto out; err = dwarf_parse_section(__start_eh_frame, __stop_eh_frame, NULL); if (err) @@ -1191,11 +1208,13 @@ static int __init dwarf_unwinder_init(void) if (err) goto out; + dwarf_unwinder_ready = 1; + return 0; out: printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err); dwarf_unwinder_cleanup(); - return -EINVAL; + return err; } early_initcall(dwarf_unwinder_init); diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c index 4770c241c679..5c51b794ba2a 100644 --- a/arch/sh/kernel/io.c +++ b/arch/sh/kernel/io.c @@ -112,25 +112,3 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count) } } EXPORT_SYMBOL(memset_io); - -#ifndef CONFIG_GENERIC_IOMAP - -void __iomem *ioport_map(unsigned long port, unsigned int nr) -{ - void __iomem *ret; - - ret = __ioport_map_trapped(port, nr); - if (ret) - return ret; - - return __ioport_map(port, nr); -} -EXPORT_SYMBOL(ioport_map); - -void ioport_unmap(void __iomem *addr) -{ - sh_mv.mv_ioport_unmap(addr); -} -EXPORT_SYMBOL(ioport_unmap); - -#endif /* CONFIG_GENERIC_IOMAP */ diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c index e1e1dbd19557..447d78f666f9 100644 --- a/arch/sh/kernel/io_generic.c +++ b/arch/sh/kernel/io_generic.c @@ -158,3 +158,23 @@ void __iomem *generic_ioport_map(unsigned long addr, unsigned int size) void generic_ioport_unmap(void __iomem *addr) { } + +#ifndef CONFIG_GENERIC_IOMAP +void __iomem *ioport_map(unsigned long port, unsigned int nr) +{ + void __iomem *ret; + + ret = __ioport_map_trapped(port, nr); + if (ret) + return ret; + + return __ioport_map(port, nr); +} +EXPORT_SYMBOL(ioport_map); + +void ioport_unmap(void __iomem *addr) +{ + sh_mv.mv_ioport_unmap(addr); +} +EXPORT_SYMBOL(ioport_unmap); +#endif /* CONFIG_GENERIC_IOMAP */ diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c index 4a8bb4eeb8ad..2947d2bd1291 100644 --- a/arch/sh/kernel/io_trapped.c +++ b/arch/sh/kernel/io_trapped.c @@ -91,10 +91,14 @@ int register_trapped_io(struct trapped_io *tiop) tiop->magic = IO_TRAPPED_MAGIC; INIT_LIST_HEAD(&tiop->list); spin_lock_irq(&trapped_lock); +#ifdef CONFIG_HAS_IOPORT if (flags & IORESOURCE_IO) list_add(&tiop->list, &trapped_io); +#endif +#ifdef CONFIG_HAS_IOMEM if (flags & IORESOURCE_MEM) list_add(&tiop->list, &trapped_mem); +#endif spin_unlock_irq(&trapped_lock); return 0; diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c index 85cfaf916fdc..9f9bb63616ad 100644 --- a/arch/sh/kernel/machvec.c +++ b/arch/sh/kernel/machvec.c @@ -118,6 +118,14 @@ void __init sh_mv_setup(void) sh_mv.mv_##elem = generic_##elem; \ } while (0) +#ifdef CONFIG_HAS_IOPORT + +#ifdef P2SEG + __set_io_port_base(P2SEG); +#else + __set_io_port_base(0); +#endif + mv_set(inb); mv_set(inw); mv_set(inl); mv_set(outb); mv_set(outw); mv_set(outl); @@ -129,16 +137,13 @@ void __init sh_mv_setup(void) mv_set(ioport_map); mv_set(ioport_unmap); + +#endif + mv_set(irq_demux); mv_set(mode_pins); mv_set(mem_init); if (!sh_mv.mv_nr_irqs) sh_mv.mv_nr_irqs = NR_IRQS; - -#ifdef P2SEG - __set_io_port_base(P2SEG); -#else - __set_io_port_base(0); -#endif } diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index d4104ce9fe53..6c4bbba2a675 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -436,29 +436,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) 0, sizeof(struct pt_dspregs), (const void __user *)data); #endif -#ifdef CONFIG_BINFMT_ELF_FDPIC - case PTRACE_GETFDPIC: { - unsigned long tmp = 0; - - switch (addr) { - case PTRACE_GETFDPIC_EXEC: - tmp = child->mm->context.exec_fdpic_loadmap; - break; - case PTRACE_GETFDPIC_INTERP: - tmp = child->mm->context.interp_fdpic_loadmap; - break; - default: - break; - } - - ret = 0; - if (put_user(tmp, datap)) { - ret = -EFAULT; - break; - } - break; - } -#endif default: ret = ptrace_request(child, request, addr, data); break; diff --git a/arch/sh/kernel/return_address.c b/arch/sh/kernel/return_address.c index cbf1dd5372b2..5124aeb28c3f 100644 --- a/arch/sh/kernel/return_address.c +++ b/arch/sh/kernel/return_address.c @@ -24,6 +24,8 @@ void *return_address(unsigned int depth) struct dwarf_frame *tmp; tmp = dwarf_unwind_stack(ra, frame); + if (!tmp) + return NULL; if (frame) dwarf_free_frame(frame); diff --git a/arch/sh/lib/strlen.S b/arch/sh/lib/strlen.S index f8ab296047b3..1bcc13f05962 100644 --- a/arch/sh/lib/strlen.S +++ b/arch/sh/lib/strlen.S @@ -35,7 +35,7 @@ ENTRY(strlen) mov.b @r4+,r1 tst r1,r1 bt 8f - add #1,r2 + add #1,r2 1: mov #0,r3 diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index d6781ce687e2..6f1470baa314 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -133,6 +133,9 @@ config ZONE_DMA config NEED_DMA_MAP_STATE def_bool y +config NEED_SG_DMA_LENGTH + def_bool y + config GENERIC_ISA_DMA bool default y if SPARC32 diff --git a/arch/sparc/boot/btfixupprep.c b/arch/sparc/boot/btfixupprep.c index b60491102237..da031159e2b7 100644 --- a/arch/sparc/boot/btfixupprep.c +++ b/arch/sparc/boot/btfixupprep.c @@ -325,7 +325,7 @@ main1: (*rr)->next = NULL; } printf("! Generated by btfixupprep. Do not edit.\n\n"); - printf("\t.section\t\".data.init\",#alloc,#write\n\t.align\t4\n\n"); + printf("\t.section\t\".data..init\",#alloc,#write\n\t.align\t4\n\n"); printf("\t.global\t___btfixup_start\n___btfixup_start:\n\n"); for (i = 0; i < last; i++) { f = array + i; diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 78b07009f60a..0588b8c7faa2 100644 --- a/arch/sparc/include/asm/cache.h +++ b/arch/sparc/include/asm/cache.h @@ -21,7 +21,7 @@ #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #ifdef CONFIG_SPARC32 #include <asm/asi.h> diff --git a/arch/sparc/include/asm/device.h b/arch/sparc/include/asm/device.h index f3b85b6b0b76..d4c452147412 100644 --- a/arch/sparc/include/asm/device.h +++ b/arch/sparc/include/asm/device.h @@ -13,25 +13,10 @@ struct dev_archdata { void *iommu; void *stc; void *host_controller; - - struct device_node *prom_node; struct of_device *op; - int numa_node; }; -static inline void dev_archdata_set_node(struct dev_archdata *ad, - struct device_node *np) -{ - ad->prom_node = np; -} - -static inline struct device_node * -dev_archdata_get_node(const struct dev_archdata *ad) -{ - return ad->prom_node; -} - struct pdev_archdata { }; diff --git a/arch/sparc/include/asm/fb.h b/arch/sparc/include/asm/fb.h index b83e44729655..e834880be204 100644 --- a/arch/sparc/include/asm/fb.h +++ b/arch/sparc/include/asm/fb.h @@ -18,7 +18,7 @@ static inline int fb_is_primary_device(struct fb_info *info) struct device *dev = info->device; struct device_node *node; - node = dev->archdata.prom_node; + node = dev->of_node; if (node && node == of_console_device) return 1; diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h index 36439d67ad71..8fac3ab22f36 100644 --- a/arch/sparc/include/asm/floppy_64.h +++ b/arch/sparc/include/asm/floppy_64.h @@ -589,7 +589,7 @@ static unsigned long __init sun_floppy_init(void) if (!op) return 0; - state_prop = of_get_property(op->node, "status", NULL); + state_prop = of_get_property(op->dev.of_node, "status", NULL); if (state_prop && !strncmp(state_prop, "disabled", 8)) return 0; @@ -716,7 +716,7 @@ static unsigned long __init sun_floppy_init(void) return sun_floppy_types[0]; } - prop = of_get_property(op->node, "status", NULL); + prop = of_get_property(op->dev.of_node, "status", NULL); if (prop && !strncmp(state, "disabled", 8)) return 0; diff --git a/arch/sparc/include/asm/of_device.h b/arch/sparc/include/asm/of_device.h index a5d9811f9697..f320246a0586 100644 --- a/arch/sparc/include/asm/of_device.h +++ b/arch/sparc/include/asm/of_device.h @@ -14,7 +14,6 @@ */ struct of_device { - struct device_node *node; struct device dev; struct resource resource[PROMREG_MAX]; unsigned int irqs[PROMINTR_MAX]; diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h index ff9ead640c4a..c333b8d0949b 100644 --- a/arch/sparc/include/asm/parport.h +++ b/arch/sparc/include/asm/parport.h @@ -113,7 +113,7 @@ static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id struct parport *p; int slot, err; - parent = op->node->parent; + parent = op->dev.of_node->parent; if (!strcmp(parent->name, "dma")) { p = parport_pc_probe_port(base, base + 0x400, op->irqs[0], PARPORT_DMA_NOFIFO, @@ -232,8 +232,11 @@ static const struct of_device_id ecpp_match[] = { }; static struct of_platform_driver ecpp_driver = { - .name = "ecpp", - .match_table = ecpp_match, + .driver = { + .name = "ecpp", + .owner = THIS_MODULE, + .of_match_table = ecpp_match, + }, .probe = ecpp_probe, .remove = __devexit_p(ecpp_remove), }; diff --git a/arch/sparc/include/asm/scatterlist.h b/arch/sparc/include/asm/scatterlist.h index d1120257b033..433e45f05fd4 100644 --- a/arch/sparc/include/asm/scatterlist.h +++ b/arch/sparc/include/asm/scatterlist.h @@ -1,8 +1,9 @@ #ifndef _SPARC_SCATTERLIST_H #define _SPARC_SCATTERLIST_H -#define sg_dma_len(sg) ((sg)->dma_length) - #include <asm-generic/scatterlist.h> +#define ISA_DMA_THRESHOLD (~0UL) +#define ARCH_HAS_SG_CHAIN + #endif /* !(_SPARC_SCATTERLIST_H) */ diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c index 71ec90b9e316..b27476caa133 100644 --- a/arch/sparc/kernel/apc.c +++ b/arch/sparc/kernel/apc.c @@ -174,8 +174,11 @@ static struct of_device_id __initdata apc_match[] = { MODULE_DEVICE_TABLE(of, apc_match); static struct of_platform_driver apc_driver = { - .name = "apc", - .match_table = apc_match, + .driver = { + .name = "apc", + .owner = THIS_MODULE, + .of_match_table = apc_match, + }, .probe = apc_probe, }; diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c index 9f52db2d441c..ddc84128b3c2 100644 --- a/arch/sparc/kernel/auxio_64.c +++ b/arch/sparc/kernel/auxio_64.c @@ -104,7 +104,7 @@ MODULE_DEVICE_TABLE(of, auxio_match); static int __devinit auxio_probe(struct of_device *dev, const struct of_device_id *match) { - struct device_node *dp = dev->node; + struct device_node *dp = dev->dev.of_node; unsigned long size; if (!strcmp(dp->parent->name, "ebus")) { @@ -132,10 +132,11 @@ static int __devinit auxio_probe(struct of_device *dev, const struct of_device_i } static struct of_platform_driver auxio_driver = { - .match_table = auxio_match, .probe = auxio_probe, - .driver = { - .name = "auxio", + .driver = { + .name = "auxio", + .owner = THIS_MODULE, + .of_match_table = auxio_match, }, }; diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c index 415c86d5a8da..434335f65823 100644 --- a/arch/sparc/kernel/central.c +++ b/arch/sparc/kernel/central.c @@ -149,10 +149,11 @@ static struct of_device_id __initdata clock_board_match[] = { }; static struct of_platform_driver clock_board_driver = { - .match_table = clock_board_match, .probe = clock_board_probe, - .driver = { - .name = "clock_board", + .driver = { + .name = "clock_board", + .owner = THIS_MODULE, + .of_match_table = clock_board_match, }, }; @@ -168,7 +169,7 @@ static int __devinit fhc_probe(struct of_device *op, goto out; } - if (!strcmp(op->node->parent->name, "central")) + if (!strcmp(op->dev.of_node->parent->name, "central")) p->central = true; p->pregs = of_ioremap(&op->resource[0], 0, @@ -183,7 +184,7 @@ static int __devinit fhc_probe(struct of_device *op, reg = upa_readl(p->pregs + FHC_PREGS_BSR); p->board_num = ((reg >> 16) & 1) | ((reg >> 12) & 0x0e); } else { - p->board_num = of_getintprop_default(op->node, "board#", -1); + p->board_num = of_getintprop_default(op->dev.of_node, "board#", -1); if (p->board_num == -1) { printk(KERN_ERR "fhc: No board# property\n"); goto out_unmap_pregs; @@ -254,10 +255,11 @@ static struct of_device_id __initdata fhc_match[] = { }; static struct of_platform_driver fhc_driver = { - .match_table = fhc_match, .probe = fhc_probe, - .driver = { - .name = "fhc", + .driver = { + .name = "fhc", + .owner = THIS_MODULE, + .of_match_table = fhc_match, }, }; diff --git a/arch/sparc/kernel/chmc.c b/arch/sparc/kernel/chmc.c index e1a9598e2a4d..870cb65b3f21 100644 --- a/arch/sparc/kernel/chmc.c +++ b/arch/sparc/kernel/chmc.c @@ -425,7 +425,7 @@ static int __devinit jbusmc_probe(struct of_device *op, INIT_LIST_HEAD(&p->list); err = -ENODEV; - prop = of_get_property(op->node, "portid", &len); + prop = of_get_property(op->dev.of_node, "portid", &len); if (!prop || len != 4) { printk(KERN_ERR PFX "Cannot find portid.\n"); goto out_free; @@ -433,7 +433,7 @@ static int __devinit jbusmc_probe(struct of_device *op, p->portid = *prop; - prop = of_get_property(op->node, "memory-control-register-1", &len); + prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len); if (!prop || len != 8) { printk(KERN_ERR PFX "Cannot get memory control register 1.\n"); goto out_free; @@ -449,7 +449,7 @@ static int __devinit jbusmc_probe(struct of_device *op, } err = -ENODEV; - ml = of_get_property(op->node, "memory-layout", &p->layout_len); + ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len); if (!ml) { printk(KERN_ERR PFX "Cannot get memory layout property.\n"); goto out_iounmap; @@ -466,7 +466,7 @@ static int __devinit jbusmc_probe(struct of_device *op, mc_list_add(&p->list); printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %s\n", - op->node->full_name); + op->dev.of_node->full_name); dev_set_drvdata(&op->dev, p); @@ -693,7 +693,7 @@ static void chmc_fetch_decode_regs(struct chmc *p) static int __devinit chmc_probe(struct of_device *op, const struct of_device_id *match) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; unsigned long ver; const void *pval; int len, portid; @@ -811,8 +811,11 @@ static const struct of_device_id us3mc_match[] = { MODULE_DEVICE_TABLE(of, us3mc_match); static struct of_platform_driver us3mc_driver = { - .name = "us3mc", - .match_table = us3mc_match, + .driver = { + .name = "us3mc", + .owner = THIS_MODULE, + .of_match_table = us3mc_match, + }, .probe = us3mc_probe, .remove = __devexit_p(us3mc_remove), }; diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 84e5386714cd..703e4aa9bc38 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c @@ -290,7 +290,7 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len, if (mmu_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0) goto err_noiommu; - res->name = op->node->name; + res->name = op->dev.of_node->name; return (void *)(unsigned long)res->start; diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c index da527b33ebc7..47e63f1e719c 100644 --- a/arch/sparc/kernel/of_device_32.c +++ b/arch/sparc/kernel/of_device_32.c @@ -254,10 +254,10 @@ static void __init build_device_resources(struct of_device *op, return; p_op = to_of_device(parent); - bus = of_match_bus(p_op->node); - bus->count_cells(op->node, &na, &ns); + bus = of_match_bus(p_op->dev.of_node); + bus->count_cells(op->dev.of_node, &na, &ns); - preg = of_get_property(op->node, bus->addr_prop_name, &num_reg); + preg = of_get_property(op->dev.of_node, bus->addr_prop_name, &num_reg); if (!preg || num_reg == 0) return; @@ -271,8 +271,8 @@ static void __init build_device_resources(struct of_device *op, struct resource *r = &op->resource[index]; u32 addr[OF_MAX_ADDR_CELLS]; const u32 *reg = (preg + (index * ((na + ns) * 4))); - struct device_node *dp = op->node; - struct device_node *pp = p_op->node; + struct device_node *dp = op->dev.of_node; + struct device_node *pp = p_op->dev.of_node; struct of_bus *pbus, *dbus; u64 size, result = OF_BAD_ADDR; unsigned long flags; @@ -321,7 +321,7 @@ static void __init build_device_resources(struct of_device *op, if (of_resource_verbose) printk("%s reg[%d] -> %llx\n", - op->node->full_name, index, + op->dev.of_node->full_name, index, result); if (result != OF_BAD_ADDR) { @@ -329,7 +329,7 @@ static void __init build_device_resources(struct of_device *op, r->end = result + size - 1; r->flags = flags | ((result >> 32ULL) & 0xffUL); } - r->name = op->node->name; + r->name = op->dev.of_node->name; } } @@ -345,10 +345,9 @@ static struct of_device * __init scan_one_device(struct device_node *dp, return NULL; sd = &op->dev.archdata; - sd->prom_node = dp; sd->op = op; - op->node = dp; + op->dev.of_node = dp; op->clock_freq = of_getintprop_default(dp, "clock-frequency", (25*1000*1000)); diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c index b3d4cb5d21b3..1dae8079f728 100644 --- a/arch/sparc/kernel/of_device_64.c +++ b/arch/sparc/kernel/of_device_64.c @@ -323,10 +323,10 @@ static void __init build_device_resources(struct of_device *op, return; p_op = to_of_device(parent); - bus = of_match_bus(p_op->node); - bus->count_cells(op->node, &na, &ns); + bus = of_match_bus(p_op->dev.of_node); + bus->count_cells(op->dev.of_node, &na, &ns); - preg = of_get_property(op->node, bus->addr_prop_name, &num_reg); + preg = of_get_property(op->dev.of_node, bus->addr_prop_name, &num_reg); if (!preg || num_reg == 0) return; @@ -340,7 +340,7 @@ static void __init build_device_resources(struct of_device *op, if (num_reg > PROMREG_MAX) { printk(KERN_WARNING "%s: Too many regs (%d), " "limiting to %d.\n", - op->node->full_name, num_reg, PROMREG_MAX); + op->dev.of_node->full_name, num_reg, PROMREG_MAX); num_reg = PROMREG_MAX; } @@ -348,8 +348,8 @@ static void __init build_device_resources(struct of_device *op, struct resource *r = &op->resource[index]; u32 addr[OF_MAX_ADDR_CELLS]; const u32 *reg = (preg + (index * ((na + ns) * 4))); - struct device_node *dp = op->node; - struct device_node *pp = p_op->node; + struct device_node *dp = op->dev.of_node; + struct device_node *pp = p_op->dev.of_node; struct of_bus *pbus, *dbus; u64 size, result = OF_BAD_ADDR; unsigned long flags; @@ -397,7 +397,7 @@ static void __init build_device_resources(struct of_device *op, if (of_resource_verbose) printk("%s reg[%d] -> %llx\n", - op->node->full_name, index, + op->dev.of_node->full_name, index, result); if (result != OF_BAD_ADDR) { @@ -408,7 +408,7 @@ static void __init build_device_resources(struct of_device *op, r->end = result + size - 1; r->flags = flags; } - r->name = op->node->name; + r->name = op->dev.of_node->name; } } @@ -530,7 +530,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op, struct device *parent, unsigned int irq) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct device_node *pp, *ip; unsigned int orig_irq = irq; int nid; @@ -575,7 +575,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op, if (of_irq_verbose) printk("%s: Apply [%s:%x] imap --> [%s:%x]\n", - op->node->full_name, + op->dev.of_node->full_name, pp->full_name, this_orig_irq, (iret ? iret->full_name : "NULL"), irq); @@ -594,7 +594,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op, if (of_irq_verbose) printk("%s: PCI swizzle [%s] " "%x --> %x\n", - op->node->full_name, + op->dev.of_node->full_name, pp->full_name, this_orig_irq, irq); @@ -611,11 +611,11 @@ static unsigned int __init build_one_device_irq(struct of_device *op, if (!ip) return orig_irq; - irq = ip->irq_trans->irq_build(op->node, irq, + irq = ip->irq_trans->irq_build(op->dev.of_node, irq, ip->irq_trans->data); if (of_irq_verbose) printk("%s: Apply IRQ trans [%s] %x --> %x\n", - op->node->full_name, ip->full_name, orig_irq, irq); + op->dev.of_node->full_name, ip->full_name, orig_irq, irq); out: nid = of_node_to_nid(dp); @@ -640,10 +640,9 @@ static struct of_device * __init scan_one_device(struct device_node *dp, return NULL; sd = &op->dev.archdata; - sd->prom_node = dp; sd->op = op; - op->node = dp; + op->dev.of_node = dp; op->clock_freq = of_getintprop_default(dp, "clock-frequency", (25*1000*1000)); diff --git a/arch/sparc/kernel/of_device_common.c b/arch/sparc/kernel/of_device_common.c index 0247e68210b3..10c6c36a6e75 100644 --- a/arch/sparc/kernel/of_device_common.c +++ b/arch/sparc/kernel/of_device_common.c @@ -16,7 +16,7 @@ static int node_match(struct device *dev, void *data) struct of_device *op = to_of_device(dev); struct device_node *dp = data; - return (op->node == dp); + return (op->dev.of_node == dp); } struct of_device *of_find_device_by_node(struct device_node *dp) @@ -48,7 +48,7 @@ EXPORT_SYMBOL(irq_of_parse_and_map); void of_propagate_archdata(struct of_device *bus) { struct dev_archdata *bus_sd = &bus->dev.archdata; - struct device_node *bus_dp = bus->node; + struct device_node *bus_dp = bus->dev.of_node; struct device_node *dp; for (dp = bus_dp->child; dp; dp = dp->sibling) { diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 5ac539a5930f..8a8363adb8bd 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -261,7 +261,6 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, sd->iommu = pbm->iommu; sd->stc = &pbm->stc; sd->host_controller = pbm; - sd->prom_node = node; sd->op = op = of_find_device_by_node(node); sd->numa_node = pbm->numa_node; @@ -285,6 +284,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, dev->sysdata = node; dev->dev.parent = bus->bridge; dev->dev.bus = &pci_bus_type; + dev->dev.of_node = node; dev->devfn = devfn; dev->multifunction = 0; /* maybe a lie? */ set_pcie_port_type(dev); @@ -653,7 +653,7 @@ show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * struct device_node *dp; pdev = to_pci_dev(dev); - dp = pdev->dev.archdata.prom_node; + dp = pdev->dev.of_node; return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); } @@ -683,7 +683,7 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, struct device *parent) { - struct device_node *node = pbm->op->node; + struct device_node *node = pbm->op->dev.of_node; struct pci_bus *bus; printk("PCI: Scanning PBM %s\n", node->full_name); @@ -1022,7 +1022,7 @@ void arch_teardown_msi_irq(unsigned int virt_irq) struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) { - return pdev->dev.archdata.prom_node; + return pdev->dev.of_node; } EXPORT_SYMBOL(pci_device_to_OF_node); @@ -1151,15 +1151,13 @@ static int __init of_pci_slot_init(void) struct device_node *node; if (pbus->self) { - struct dev_archdata *sd = pbus->self->sysdata; - /* PCI->PCI bridge */ - node = sd->prom_node; + node = pbus->self->dev.of_node; } else { struct pci_pbm_info *pbm = pbus->sysdata; /* Host PCI controller */ - node = pbm->op->node; + node = pbm->op->dev.of_node; } pci_bus_slot_names(node, pbus); diff --git a/arch/sparc/kernel/pci_common.c b/arch/sparc/kernel/pci_common.c index 8a000583b5cf..6c7a33af3ba6 100644 --- a/arch/sparc/kernel/pci_common.c +++ b/arch/sparc/kernel/pci_common.c @@ -314,12 +314,12 @@ struct pci_ops sun4v_pci_ops = { void pci_get_pbm_props(struct pci_pbm_info *pbm) { - const u32 *val = of_get_property(pbm->op->node, "bus-range", NULL); + const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL); pbm->pci_first_busno = val[0]; pbm->pci_last_busno = val[1]; - val = of_get_property(pbm->op->node, "ino-bitmap", NULL); + val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL); if (val) { pbm->ino_bitmap = (((u64)val[1] << 32UL) | ((u64)val[0] << 0UL)); @@ -365,7 +365,8 @@ static void pci_register_legacy_regions(struct resource *io_res, static void pci_register_iommu_region(struct pci_pbm_info *pbm) { - const u32 *vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); + const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", + NULL); if (vdma) { struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL); @@ -394,7 +395,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm) int num_pbm_ranges; saw_mem = saw_io = 0; - pbm_ranges = of_get_property(pbm->op->node, "ranges", &i); + pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i); if (!pbm_ranges) { prom_printf("PCI: Fatal error, missing PBM ranges property " " for %s\n", diff --git a/arch/sparc/kernel/pci_fire.c b/arch/sparc/kernel/pci_fire.c index d53f45bc7dda..51cfa09e392a 100644 --- a/arch/sparc/kernel/pci_fire.c +++ b/arch/sparc/kernel/pci_fire.c @@ -413,7 +413,7 @@ static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm, struct of_device *op, u32 portid) { const struct linux_prom64_registers *regs; - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; int err; pbm->numa_node = -1; @@ -458,7 +458,7 @@ static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm, static int __devinit fire_probe(struct of_device *op, const struct of_device_id *match) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct pci_pbm_info *pbm; struct iommu *iommu; u32 portid; @@ -508,8 +508,11 @@ static struct of_device_id __initdata fire_match[] = { }; static struct of_platform_driver fire_driver = { - .name = DRIVER_NAME, - .match_table = fire_match, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = fire_match, + }, .probe = fire_probe, }; diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c index e0ef847219c3..548b8ca9c210 100644 --- a/arch/sparc/kernel/pci_msi.c +++ b/arch/sparc/kernel/pci_msi.c @@ -324,7 +324,7 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, const u32 *val; int len; - val = of_get_property(pbm->op->node, "#msi-eqs", &len); + val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len); if (!val || len != 4) goto no_msi; pbm->msiq_num = *val; @@ -347,16 +347,16 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, u32 msi64_len; } *arng; - val = of_get_property(pbm->op->node, "msi-eq-size", &len); + val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len); if (!val || len != 4) goto no_msi; pbm->msiq_ent_count = *val; - mqp = of_get_property(pbm->op->node, + mqp = of_get_property(pbm->op->dev.of_node, "msi-eq-to-devino", &len); if (!mqp) - mqp = of_get_property(pbm->op->node, + mqp = of_get_property(pbm->op->dev.of_node, "msi-eq-devino", &len); if (!mqp || len != sizeof(struct msiq_prop)) goto no_msi; @@ -364,27 +364,27 @@ void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, pbm->msiq_first = mqp->first_msiq; pbm->msiq_first_devino = mqp->first_devino; - val = of_get_property(pbm->op->node, "#msi", &len); + val = of_get_property(pbm->op->dev.of_node, "#msi", &len); if (!val || len != 4) goto no_msi; pbm->msi_num = *val; - mrng = of_get_property(pbm->op->node, "msi-ranges", &len); + mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len); if (!mrng || len != sizeof(struct msi_range_prop)) goto no_msi; pbm->msi_first = mrng->first_msi; - val = of_get_property(pbm->op->node, "msi-data-mask", &len); + val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len); if (!val || len != 4) goto no_msi; pbm->msi_data_mask = *val; - val = of_get_property(pbm->op->node, "msix-data-width", &len); + val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len); if (!val || len != 4) goto no_msi; pbm->msix_data_width = *val; - arng = of_get_property(pbm->op->node, "msi-address-ranges", + arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges", &len); if (!arng || len != sizeof(struct addr_range_prop)) goto no_msi; diff --git a/arch/sparc/kernel/pci_psycho.c b/arch/sparc/kernel/pci_psycho.c index 142b9d6984a8..558a70512824 100644 --- a/arch/sparc/kernel/pci_psycho.c +++ b/arch/sparc/kernel/pci_psycho.c @@ -285,7 +285,7 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id) #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ static void psycho_register_error_handlers(struct pci_pbm_info *pbm) { - struct of_device *op = of_find_device_by_node(pbm->op->node); + struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node); unsigned long base = pbm->controller_regs; u64 tmp; int err; @@ -507,7 +507,7 @@ static int __devinit psycho_probe(struct of_device *op, const struct of_device_id *match) { const struct linux_prom64_registers *pr_regs; - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct pci_pbm_info *pbm; struct iommu *iommu; int is_pbm_a, err; @@ -602,8 +602,11 @@ static struct of_device_id __initdata psycho_match[] = { }; static struct of_platform_driver psycho_driver = { - .name = DRIVER_NAME, - .match_table = psycho_match, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = psycho_match, + }, .probe = psycho_probe, }; diff --git a/arch/sparc/kernel/pci_sabre.c b/arch/sparc/kernel/pci_sabre.c index ba6fbeba3e2c..6dad8e3b7506 100644 --- a/arch/sparc/kernel/pci_sabre.c +++ b/arch/sparc/kernel/pci_sabre.c @@ -310,7 +310,7 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id) static void sabre_register_error_handlers(struct pci_pbm_info *pbm) { - struct device_node *dp = pbm->op->node; + struct device_node *dp = pbm->op->dev.of_node; struct of_device *op; unsigned long base = pbm->controller_regs; u64 tmp; @@ -456,7 +456,7 @@ static int __devinit sabre_probe(struct of_device *op, const struct of_device_id *match) { const struct linux_prom64_registers *pr_regs; - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct pci_pbm_info *pbm; u32 upa_portid, dma_mask; struct iommu *iommu; @@ -596,8 +596,11 @@ static struct of_device_id __initdata sabre_match[] = { }; static struct of_platform_driver sabre_driver = { - .name = DRIVER_NAME, - .match_table = sabre_match, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = sabre_match, + }, .probe = sabre_probe, }; diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c index 2b5cdde77af7..97a1ae2e1c02 100644 --- a/arch/sparc/kernel/pci_schizo.c +++ b/arch/sparc/kernel/pci_schizo.c @@ -844,7 +844,7 @@ static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) */ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) { - struct of_device *op = of_find_device_by_node(pbm->op->node); + struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node); u64 tmp, err_mask, err_no_mask; int err; @@ -939,7 +939,7 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) static void schizo_register_error_handlers(struct pci_pbm_info *pbm) { - struct of_device *op = of_find_device_by_node(pbm->op->node); + struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node); u64 tmp, err_mask, err_no_mask; int err; @@ -1068,7 +1068,7 @@ static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm, { pbm_config_busmastering(pbm); pbm->is_66mhz_capable = - (of_find_property(pbm->op->node, "66mhz-capable", NULL) + (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) != NULL); pbm->pci_bus = pci_scan_one_pbm(pbm, parent); @@ -1138,7 +1138,7 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) u32 dma_mask; u64 control; - vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); + vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); if (!vdma) vdma = vdma_default; @@ -1268,7 +1268,7 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) pbm->chip_version >= 0x2) tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; - if (!of_find_property(pbm->op->node, "no-bus-parking", NULL)) + if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL)) tmp |= SCHIZO_PCICTRL_PARK; else tmp &= ~SCHIZO_PCICTRL_PARK; @@ -1311,7 +1311,7 @@ static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, int chip_type) { const struct linux_prom64_registers *regs; - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; const char *chipset_name; int is_pbm_a, err; @@ -1415,7 +1415,7 @@ static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid, static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct pci_pbm_info *pbm; struct iommu *iommu; u32 portid; @@ -1491,8 +1491,11 @@ static struct of_device_id __initdata schizo_match[] = { }; static struct of_platform_driver schizo_driver = { - .name = DRIVER_NAME, - .match_table = schizo_match, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = schizo_match, + }, .probe = schizo_probe, }; diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c index 23c33ff9c31e..a24af6f7e17f 100644 --- a/arch/sparc/kernel/pci_sun4v.c +++ b/arch/sparc/kernel/pci_sun4v.c @@ -540,7 +540,7 @@ static void __devinit pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct property *prop; struct device_node *dp; - dp = pbm->op->node; + dp = pbm->op->dev.of_node; prop = of_find_property(dp, "66mhz-capable", NULL); pbm->is_66mhz_capable = (prop != NULL); pbm->pci_bus = pci_scan_one_pbm(pbm, parent); @@ -584,7 +584,7 @@ static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm) u32 dma_mask, dma_offset; const u32 *vdma; - vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); + vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); if (!vdma) vdma = vdma_default; @@ -881,7 +881,7 @@ static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm, struct of_device *op, u32 devhandle) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; int err; pbm->numa_node = of_node_to_nid(dp); @@ -929,7 +929,7 @@ static int __devinit pci_sun4v_probe(struct of_device *op, u32 devhandle; int i, err; - dp = op->node; + dp = op->dev.of_node; if (!hvapi_negotiated++) { err = sun4v_hvapi_register(HV_GRP_PCI, @@ -1009,8 +1009,11 @@ static struct of_device_id __initdata pci_sun4v_match[] = { }; static struct of_platform_driver pci_sun4v_driver = { - .name = DRIVER_NAME, - .match_table = pci_sun4v_match, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = pci_sun4v_match, + }, .probe = pci_sun4v_probe, }; diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 34ce49f80eac..0ec92c8861dd 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -92,6 +92,8 @@ struct cpu_hw_events { /* Enabled/disable state. */ int enabled; + + unsigned int group_flag; }; DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; @@ -981,53 +983,6 @@ static int collect_events(struct perf_event *group, int max_count, return n; } -static void event_sched_in(struct perf_event *event) -{ - event->state = PERF_EVENT_STATE_ACTIVE; - event->oncpu = smp_processor_id(); - event->tstamp_running += event->ctx->time - event->tstamp_stopped; - if (is_software_event(event)) - event->pmu->enable(event); -} - -int hw_perf_group_sched_in(struct perf_event *group_leader, - struct perf_cpu_context *cpuctx, - struct perf_event_context *ctx) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - struct perf_event *sub; - int n0, n; - - if (!sparc_pmu) - return 0; - - n0 = cpuc->n_events; - n = collect_events(group_leader, perf_max_events - n0, - &cpuc->event[n0], &cpuc->events[n0], - &cpuc->current_idx[n0]); - if (n < 0) - return -EAGAIN; - if (check_excludes(cpuc->event, n0, n)) - return -EINVAL; - if (sparc_check_constraints(cpuc->event, cpuc->events, n + n0)) - return -EAGAIN; - cpuc->n_events = n0 + n; - cpuc->n_added += n; - - cpuctx->active_oncpu += n; - n = 1; - event_sched_in(group_leader); - list_for_each_entry(sub, &group_leader->sibling_list, group_entry) { - if (sub->state != PERF_EVENT_STATE_OFF) { - event_sched_in(sub); - n++; - } - } - ctx->nr_active += n; - - return 1; -} - static int sparc_pmu_enable(struct perf_event *event) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -1045,11 +1000,20 @@ static int sparc_pmu_enable(struct perf_event *event) cpuc->events[n0] = event->hw.event_base; cpuc->current_idx[n0] = PIC_NO_INDEX; + /* + * If group events scheduling transaction was started, + * skip the schedulability test here, it will be peformed + * at commit time(->commit_txn) as a whole + */ + if (cpuc->group_flag & PERF_EVENT_TXN_STARTED) + goto nocheck; + if (check_excludes(cpuc->event, n0, 1)) goto out; if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) goto out; +nocheck: cpuc->n_events++; cpuc->n_added++; @@ -1129,11 +1093,61 @@ static int __hw_perf_event_init(struct perf_event *event) return 0; } +/* + * Start group events scheduling transaction + * Set the flag to make pmu::enable() not perform the + * schedulability test, it will be performed at commit time + */ +static void sparc_pmu_start_txn(const struct pmu *pmu) +{ + struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); + + cpuhw->group_flag |= PERF_EVENT_TXN_STARTED; +} + +/* + * Stop group events scheduling transaction + * Clear the flag and pmu::enable() will perform the + * schedulability test. + */ +static void sparc_pmu_cancel_txn(const struct pmu *pmu) +{ + struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); + + cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED; +} + +/* + * Commit group events scheduling transaction + * Perform the group schedulability test as a whole + * Return 0 if success + */ +static int sparc_pmu_commit_txn(const struct pmu *pmu) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int n; + + if (!sparc_pmu) + return -EINVAL; + + cpuc = &__get_cpu_var(cpu_hw_events); + n = cpuc->n_events; + if (check_excludes(cpuc->event, 0, n)) + return -EINVAL; + if (sparc_check_constraints(cpuc->event, cpuc->events, n)) + return -EAGAIN; + + return 0; +} + static const struct pmu pmu = { .enable = sparc_pmu_enable, .disable = sparc_pmu_disable, .read = sparc_pmu_read, .unthrottle = sparc_pmu_unthrottle, + .start_txn = sparc_pmu_start_txn, + .cancel_txn = sparc_pmu_cancel_txn, + .commit_txn = sparc_pmu_commit_txn, }; const struct pmu *hw_perf_event_init(struct perf_event *event) diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c index 5e4563d86f19..9589d8b9b0c1 100644 --- a/arch/sparc/kernel/pmc.c +++ b/arch/sparc/kernel/pmc.c @@ -79,8 +79,11 @@ static struct of_device_id __initdata pmc_match[] = { MODULE_DEVICE_TABLE(of, pmc_match); static struct of_platform_driver pmc_driver = { - .name = "pmc", - .match_table = pmc_match, + .driver = { + .name = "pmc", + .owner = THIS_MODULE, + .of_match_table = pmc_match, + }, .probe = pmc_probe, }; diff --git a/arch/sparc/kernel/power.c b/arch/sparc/kernel/power.c index e2a045c235a1..168d4cb63f5b 100644 --- a/arch/sparc/kernel/power.c +++ b/arch/sparc/kernel/power.c @@ -41,9 +41,9 @@ static int __devinit power_probe(struct of_device *op, const struct of_device_id power_reg = of_ioremap(res, 0, 0x4, "power"); printk(KERN_INFO "%s: Control reg at %llx\n", - op->node->name, res->start); + op->dev.of_node->name, res->start); - if (has_button_interrupt(irq, op->node)) { + if (has_button_interrupt(irq, op->dev.of_node)) { if (request_irq(irq, power_handler, 0, "power", NULL) < 0) printk(KERN_ERR "power: Cannot setup IRQ handler.\n"); @@ -60,10 +60,11 @@ static struct of_device_id __initdata power_match[] = { }; static struct of_platform_driver power_driver = { - .match_table = power_match, .probe = power_probe, - .driver = { - .name = "power", + .driver = { + .name = "power", + .owner = THIS_MODULE, + .of_match_table = power_match, }, }; diff --git a/arch/sparc/kernel/psycho_common.c b/arch/sparc/kernel/psycho_common.c index 8f1478475421..3f34ac853931 100644 --- a/arch/sparc/kernel/psycho_common.c +++ b/arch/sparc/kernel/psycho_common.c @@ -450,7 +450,7 @@ int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize, void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct of_device *op, const char *chip_name, int chip_type) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; pbm->name = dp->full_name; pbm->numa_node = -1; diff --git a/arch/sparc/kernel/sbus.c b/arch/sparc/kernel/sbus.c index 406e0872504e..cfeaf04b9cdf 100644 --- a/arch/sparc/kernel/sbus.c +++ b/arch/sparc/kernel/sbus.c @@ -63,10 +63,10 @@ void sbus_set_sbus64(struct device *dev, int bursts) int slot; u64 val; - regs = of_get_property(op->node, "reg", NULL); + regs = of_get_property(op->dev.of_node, "reg", NULL); if (!regs) { printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n", - op->node->full_name); + op->dev.of_node->full_name); return; } slot = regs->which_io; @@ -287,7 +287,7 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id) SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); upa_writeq(error_bits, afsr_reg); - portid = of_getintprop_default(op->node, "portid", -1); + portid = of_getintprop_default(op->dev.of_node, "portid", -1); /* Log the error. */ printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", @@ -361,7 +361,7 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id) SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); upa_writeq(error_bits, afsr_reg); - portid = of_getintprop_default(op->node, "portid", -1); + portid = of_getintprop_default(op->dev.of_node, "portid", -1); printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", portid, @@ -439,7 +439,7 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); upa_writeq(error_bits, afsr_reg); - portid = of_getintprop_default(op->node, "portid", -1); + portid = of_getintprop_default(op->dev.of_node, "portid", -1); /* Log the error. */ printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", @@ -496,7 +496,7 @@ static void __init sysio_register_error_handlers(struct of_device *op) u64 control; int portid; - portid = of_getintprop_default(op->node, "portid", -1); + portid = of_getintprop_default(op->dev.of_node, "portid", -1); irq = sbus_build_irq(op, SYSIO_UE_INO); if (request_irq(irq, sysio_ue_handler, 0, @@ -537,7 +537,7 @@ static void __init sysio_register_error_handlers(struct of_device *op) static void __init sbus_iommu_init(struct of_device *op) { const struct linux_prom64_registers *pr; - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; struct iommu *iommu; struct strbuf *strbuf; unsigned long regs, reg_base; @@ -589,7 +589,7 @@ static void __init sbus_iommu_init(struct of_device *op) */ iommu->write_complete_reg = regs + 0x2000UL; - portid = of_getintprop_default(op->node, "portid", -1); + portid = of_getintprop_default(op->dev.of_node, "portid", -1); printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n", portid, regs); diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c index 4453003032b5..e404b063be2c 100644 --- a/arch/sparc/kernel/time_32.c +++ b/arch/sparc/kernel/time_32.c @@ -144,7 +144,7 @@ static struct platform_device m48t59_rtc = { static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; const char *model = of_get_property(dp, "model", NULL); if (!model) @@ -177,10 +177,11 @@ static struct of_device_id __initdata clock_match[] = { }; static struct of_platform_driver clock_driver = { - .match_table = clock_match, .probe = clock_probe, - .driver = { - .name = "rtc", + .driver = { + .name = "rtc", + .owner = THIS_MODULE, + .of_match_table = clock_match, }, }; diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c index c7bbe6cf7b85..21e9fcae0668 100644 --- a/arch/sparc/kernel/time_64.c +++ b/arch/sparc/kernel/time_64.c @@ -424,7 +424,7 @@ static int __devinit rtc_probe(struct of_device *op, const struct of_device_id * struct resource *r; printk(KERN_INFO "%s: RTC regs at 0x%llx\n", - op->node->full_name, op->resource[0].start); + op->dev.of_node->full_name, op->resource[0].start); /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons * up a fake resource so that the probe works for all cases. @@ -463,10 +463,11 @@ static struct of_device_id __initdata rtc_match[] = { }; static struct of_platform_driver rtc_driver = { - .match_table = rtc_match, .probe = rtc_probe, - .driver = { - .name = "rtc", + .driver = { + .name = "rtc", + .owner = THIS_MODULE, + .of_match_table = rtc_match, }, }; @@ -480,7 +481,7 @@ static int __devinit bq4802_probe(struct of_device *op, const struct of_device_i { printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n", - op->node->full_name, op->resource[0].start); + op->dev.of_node->full_name, op->resource[0].start); rtc_bq4802_device.resource = &op->resource[0]; return platform_device_register(&rtc_bq4802_device); @@ -495,10 +496,11 @@ static struct of_device_id __initdata bq4802_match[] = { }; static struct of_platform_driver bq4802_driver = { - .match_table = bq4802_match, .probe = bq4802_probe, - .driver = { - .name = "bq4802", + .driver = { + .name = "bq4802", + .owner = THIS_MODULE, + .of_match_table = bq4802_match, }, }; @@ -534,7 +536,7 @@ static struct platform_device m48t59_rtc = { static int __devinit mostek_probe(struct of_device *op, const struct of_device_id *match) { - struct device_node *dp = op->node; + struct device_node *dp = op->dev.of_node; /* On an Enterprise system there can be multiple mostek clocks. * We should only match the one that is on the central FHC bus. @@ -558,10 +560,11 @@ static struct of_device_id __initdata mostek_match[] = { }; static struct of_platform_driver mostek_driver = { - .match_table = mostek_match, .probe = mostek_probe, - .driver = { - .name = "mostek", + .driver = { + .name = "mostek", + .owner = THIS_MODULE, + .of_match_table = mostek_match, }, }; diff --git a/arch/um/drivers/harddog_kern.c b/arch/um/drivers/harddog_kern.c index d332503fa1be..cfcac1ff4cf2 100644 --- a/arch/um/drivers/harddog_kern.c +++ b/arch/um/drivers/harddog_kern.c @@ -124,8 +124,8 @@ static ssize_t harddog_write(struct file *file, const char __user *data, size_t return 0; } -static int harddog_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static int harddog_ioctl_unlocked(struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp= (void __user *)arg; static struct watchdog_info ident = { @@ -148,10 +148,22 @@ static int harddog_ioctl(struct inode *inode, struct file *file, } } +static long harddog_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + long ret; + + lock_kernel(); + ret = harddog_ioctl_unlocked(file, cmd, arg); + unlock_kernel(); + + return ret; +} + static const struct file_operations harddog_fops = { .owner = THIS_MODULE, .write = harddog_write, - .ioctl = harddog_ioctl, + .unlocked_ioctl = harddog_ioctl, .open = harddog_open, .release = harddog_release, }; diff --git a/arch/um/drivers/hostaudio_kern.c b/arch/um/drivers/hostaudio_kern.c index 368219cc2366..ae42695c3597 100644 --- a/arch/um/drivers/hostaudio_kern.c +++ b/arch/um/drivers/hostaudio_kern.c @@ -136,7 +136,7 @@ static unsigned int hostaudio_poll(struct file *file, return mask; } -static int hostaudio_ioctl(struct inode *inode, struct file *file, +static long hostaudio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct hostaudio_state *state = file->private_data; @@ -223,7 +223,7 @@ static int hostaudio_release(struct inode *inode, struct file *file) /* /dev/mixer file operations */ -static int hostmixer_ioctl_mixdev(struct inode *inode, struct file *file, +static long hostmixer_ioctl_mixdev(struct file *file, unsigned int cmd, unsigned long arg) { struct hostmixer_state *state = file->private_data; @@ -289,7 +289,7 @@ static const struct file_operations hostaudio_fops = { .read = hostaudio_read, .write = hostaudio_write, .poll = hostaudio_poll, - .ioctl = hostaudio_ioctl, + .unlocked_ioctl = hostaudio_ioctl, .mmap = NULL, .open = hostaudio_open, .release = hostaudio_release, @@ -298,7 +298,7 @@ static const struct file_operations hostaudio_fops = { static const struct file_operations hostmixer_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = hostmixer_ioctl_mixdev, + .unlocked_ioctl = hostmixer_ioctl_mixdev, .open = hostmixer_open_mixdev, .release = hostmixer_release, }; diff --git a/arch/um/drivers/mmapper_kern.c b/arch/um/drivers/mmapper_kern.c index d22f9e5c0eac..7158393b6793 100644 --- a/arch/um/drivers/mmapper_kern.c +++ b/arch/um/drivers/mmapper_kern.c @@ -46,8 +46,7 @@ static ssize_t mmapper_write(struct file *file, const char __user *buf, return count; } -static int mmapper_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mmapper_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { return -ENOIOCTLCMD; } @@ -90,7 +89,7 @@ static const struct file_operations mmapper_fops = { .owner = THIS_MODULE, .read = mmapper_read, .write = mmapper_write, - .ioctl = mmapper_ioctl, + .unlocked_ioctl = mmapper_ioctl, .mmap = mmapper_mmap, .open = mmapper_open, .release = mmapper_release, diff --git a/arch/um/kernel/dyn.lds.S b/arch/um/kernel/dyn.lds.S index 7fcad58e216d..69268014dd8e 100644 --- a/arch/um/kernel/dyn.lds.S +++ b/arch/um/kernel/dyn.lds.S @@ -94,7 +94,7 @@ SECTIONS .data : { INIT_TASK_DATA(KERNEL_STACK_SIZE) . = ALIGN(KERNEL_STACK_SIZE); - *(.data.init_irqstack) + *(.data..init_irqstack) DATA_DATA *(.data.* .gnu.linkonce.d.*) SORT(CONSTRUCTORS) diff --git a/arch/um/kernel/init_task.c b/arch/um/kernel/init_task.c index 8aa77b61a5ff..ddc9698b66ed 100644 --- a/arch/um/kernel/init_task.c +++ b/arch/um/kernel/init_task.c @@ -34,5 +34,5 @@ union thread_union init_thread_union __init_task_data = { INIT_THREAD_INFO(init_task) }; union thread_union cpu0_irqstack - __attribute__((__section__(".data.init_irqstack"))) = + __attribute__((__section__(".data..init_irqstack"))) = { INIT_THREAD_INFO(init_task) }; diff --git a/arch/um/kernel/skas/uaccess.c b/arch/um/kernel/skas/uaccess.c index e22c96993db3..696634214dc6 100644 --- a/arch/um/kernel/skas/uaccess.c +++ b/arch/um/kernel/skas/uaccess.c @@ -81,7 +81,7 @@ static int do_op_one_page(unsigned long addr, int len, int is_write, current->thread.fault_catcher = NULL; - kunmap_atomic(page, KM_UML_USERCOPY); + kunmap_atomic((void *)addr, KM_UML_USERCOPY); return n; } diff --git a/arch/um/kernel/uml.lds.S b/arch/um/kernel/uml.lds.S index e7a6cca667aa..ec6378550671 100644 --- a/arch/um/kernel/uml.lds.S +++ b/arch/um/kernel/uml.lds.S @@ -50,7 +50,7 @@ SECTIONS { INIT_TASK_DATA(KERNEL_STACK_SIZE) . = ALIGN(KERNEL_STACK_SIZE); - *(.data.init_irqstack) + *(.data..init_irqstack) DATA_DATA *(.gnu.linkonce.d*) CONSTRUCTORS diff --git a/arch/x86/.gitignore b/arch/x86/.gitignore new file mode 100644 index 000000000000..028079065af6 --- /dev/null +++ b/arch/x86/.gitignore @@ -0,0 +1,3 @@ +boot/compressed/vmlinux +tools/test_get_len + diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a2d3a5fbeeda..dcb0593b4a66 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -109,6 +109,9 @@ config SBUS config NEED_DMA_MAP_STATE def_bool (X86_64 || DMAR || DMA_API_DEBUG) +config NEED_SG_DMA_LENGTH + def_bool y + config GENERIC_ISA_DMA def_bool y @@ -1703,6 +1706,10 @@ config HAVE_ARCH_EARLY_PFN_TO_NID def_bool X86_64 depends on NUMA +config USE_PERCPU_NUMA_NODE_ID + def_bool X86_64 + depends on NUMA + menu "Power management and ACPI options" config ARCH_HIBERNATION_HEADER @@ -1923,6 +1930,14 @@ config PCI_MMCONFIG bool "Support mmconfig PCI config space access" depends on X86_64 && PCI && ACPI +config PCI_CNB20LE_QUIRK + bool "Read CNB20LE Host Bridge Windows" + depends on PCI + help + Read the PCI windows out of the CNB20LE host bridge. This allows + PCI hotplug to work on systems with the CNB20LE chipset which do + not have ACPI. + config DMAR bool "Support for DMA Remapping Devices (EXPERIMENTAL)" depends on PCI_MSI && ACPI && EXPERIMENTAL diff --git a/arch/x86/boot/compressed/mkpiggy.c b/arch/x86/boot/compressed/mkpiggy.c index bcbd36c41432..5c228129d175 100644 --- a/arch/x86/boot/compressed/mkpiggy.c +++ b/arch/x86/boot/compressed/mkpiggy.c @@ -77,7 +77,7 @@ int main(int argc, char *argv[]) offs += 32*1024 + 18; /* Add 32K + 18 bytes slack */ offs = (offs+4095) & ~4095; /* Round to a 4K boundary */ - printf(".section \".rodata.compressed\",\"a\",@progbits\n"); + printf(".section \".rodata..compressed\",\"a\",@progbits\n"); printf(".globl z_input_len\n"); printf("z_input_len = %lu\n", ilen); printf(".globl z_output_len\n"); diff --git a/arch/x86/boot/compressed/vmlinux.lds.S b/arch/x86/boot/compressed/vmlinux.lds.S index a6f1a59a5b0c..5ddabceee124 100644 --- a/arch/x86/boot/compressed/vmlinux.lds.S +++ b/arch/x86/boot/compressed/vmlinux.lds.S @@ -26,8 +26,8 @@ SECTIONS HEAD_TEXT _ehead = . ; } - .rodata.compressed : { - *(.rodata.compressed) + .rodata..compressed : { + *(.rodata..compressed) } .text : { _text = .; /* Text */ diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S index 20bb0e1ac681..ff16756a51c1 100644 --- a/arch/x86/crypto/aesni-intel_asm.S +++ b/arch/x86/crypto/aesni-intel_asm.S @@ -32,6 +32,9 @@ #define IN IN1 #define KEY %xmm2 #define IV %xmm3 +#define BSWAP_MASK %xmm10 +#define CTR %xmm11 +#define INC %xmm12 #define KEYP %rdi #define OUTP %rsi @@ -42,6 +45,7 @@ #define T1 %r10 #define TKEYP T1 #define T2 %r11 +#define TCTR_LOW T2 _key_expansion_128: _key_expansion_256a: @@ -724,3 +728,114 @@ ENTRY(aesni_cbc_dec) movups IV, (IVP) .Lcbc_dec_just_ret: ret + +.align 16 +.Lbswap_mask: + .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +/* + * _aesni_inc_init: internal ABI + * setup registers used by _aesni_inc + * input: + * IV + * output: + * CTR: == IV, in little endian + * TCTR_LOW: == lower qword of CTR + * INC: == 1, in little endian + * BSWAP_MASK == endian swapping mask + */ +_aesni_inc_init: + movaps .Lbswap_mask, BSWAP_MASK + movaps IV, CTR + PSHUFB_XMM BSWAP_MASK CTR + mov $1, TCTR_LOW + MOVQ_R64_XMM TCTR_LOW INC + MOVQ_R64_XMM CTR TCTR_LOW + ret + +/* + * _aesni_inc: internal ABI + * Increase IV by 1, IV is in big endian + * input: + * IV + * CTR: == IV, in little endian + * TCTR_LOW: == lower qword of CTR + * INC: == 1, in little endian + * BSWAP_MASK == endian swapping mask + * output: + * IV: Increase by 1 + * changed: + * CTR: == output IV, in little endian + * TCTR_LOW: == lower qword of CTR + */ +_aesni_inc: + paddq INC, CTR + add $1, TCTR_LOW + jnc .Linc_low + pslldq $8, INC + paddq INC, CTR + psrldq $8, INC +.Linc_low: + movaps CTR, IV + PSHUFB_XMM BSWAP_MASK IV + ret + +/* + * void aesni_ctr_enc(struct crypto_aes_ctx *ctx, const u8 *dst, u8 *src, + * size_t len, u8 *iv) + */ +ENTRY(aesni_ctr_enc) + cmp $16, LEN + jb .Lctr_enc_just_ret + mov 480(KEYP), KLEN + movups (IVP), IV + call _aesni_inc_init + cmp $64, LEN + jb .Lctr_enc_loop1 +.align 4 +.Lctr_enc_loop4: + movaps IV, STATE1 + call _aesni_inc + movups (INP), IN1 + movaps IV, STATE2 + call _aesni_inc + movups 0x10(INP), IN2 + movaps IV, STATE3 + call _aesni_inc + movups 0x20(INP), IN3 + movaps IV, STATE4 + call _aesni_inc + movups 0x30(INP), IN4 + call _aesni_enc4 + pxor IN1, STATE1 + movups STATE1, (OUTP) + pxor IN2, STATE2 + movups STATE2, 0x10(OUTP) + pxor IN3, STATE3 + movups STATE3, 0x20(OUTP) + pxor IN4, STATE4 + movups STATE4, 0x30(OUTP) + sub $64, LEN + add $64, INP + add $64, OUTP + cmp $64, LEN + jge .Lctr_enc_loop4 + cmp $16, LEN + jb .Lctr_enc_ret +.align 4 +.Lctr_enc_loop1: + movaps IV, STATE + call _aesni_inc + movups (INP), IN + call _aesni_enc1 + pxor IN, STATE + movups STATE, (OUTP) + sub $16, LEN + add $16, INP + add $16, OUTP + cmp $16, LEN + jge .Lctr_enc_loop1 +.Lctr_enc_ret: + movups IV, (IVP) +.Lctr_enc_just_ret: + ret diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index 49c552c060e9..2cb3dcc4490a 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c @@ -18,6 +18,7 @@ #include <crypto/algapi.h> #include <crypto/aes.h> #include <crypto/cryptd.h> +#include <crypto/ctr.h> #include <asm/i387.h> #include <asm/aes.h> @@ -58,6 +59,8 @@ asmlinkage void aesni_cbc_enc(struct crypto_aes_ctx *ctx, u8 *out, const u8 *in, unsigned int len, u8 *iv); asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out, const u8 *in, unsigned int len, u8 *iv); +asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out, + const u8 *in, unsigned int len, u8 *iv); static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx) { @@ -321,6 +324,72 @@ static struct crypto_alg blk_cbc_alg = { }, }; +static void ctr_crypt_final(struct crypto_aes_ctx *ctx, + struct blkcipher_walk *walk) +{ + u8 *ctrblk = walk->iv; + u8 keystream[AES_BLOCK_SIZE]; + u8 *src = walk->src.virt.addr; + u8 *dst = walk->dst.virt.addr; + unsigned int nbytes = walk->nbytes; + + aesni_enc(ctx, keystream, ctrblk); + crypto_xor(keystream, src, nbytes); + memcpy(dst, keystream, nbytes); + crypto_inc(ctrblk, AES_BLOCK_SIZE); +} + +static int ctr_crypt(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm)); + struct blkcipher_walk walk; + int err; + + blkcipher_walk_init(&walk, dst, src, nbytes); + err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE); + desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; + + kernel_fpu_begin(); + while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) { + aesni_ctr_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr, + nbytes & AES_BLOCK_MASK, walk.iv); + nbytes &= AES_BLOCK_SIZE - 1; + err = blkcipher_walk_done(desc, &walk, nbytes); + } + if (walk.nbytes) { + ctr_crypt_final(ctx, &walk); + err = blkcipher_walk_done(desc, &walk, 0); + } + kernel_fpu_end(); + + return err; +} + +static struct crypto_alg blk_ctr_alg = { + .cra_name = "__ctr-aes-aesni", + .cra_driver_name = "__driver-ctr-aes-aesni", + .cra_priority = 0, + .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1, + .cra_alignmask = 0, + .cra_type = &crypto_blkcipher_type, + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(blk_ctr_alg.cra_list), + .cra_u = { + .blkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = aes_set_key, + .encrypt = ctr_crypt, + .decrypt = ctr_crypt, + }, + }, +}; + static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key, unsigned int key_len) { @@ -467,13 +536,11 @@ static struct crypto_alg ablk_cbc_alg = { }, }; -#ifdef HAS_CTR static int ablk_ctr_init(struct crypto_tfm *tfm) { struct cryptd_ablkcipher *cryptd_tfm; - cryptd_tfm = cryptd_alloc_ablkcipher("fpu(ctr(__driver-aes-aesni))", - 0, 0); + cryptd_tfm = cryptd_alloc_ablkcipher("__driver-ctr-aes-aesni", 0, 0); if (IS_ERR(cryptd_tfm)) return PTR_ERR(cryptd_tfm); ablk_init_common(tfm, cryptd_tfm); @@ -500,11 +567,50 @@ static struct crypto_alg ablk_ctr_alg = { .ivsize = AES_BLOCK_SIZE, .setkey = ablk_set_key, .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, + .decrypt = ablk_encrypt, .geniv = "chainiv", }, }, }; + +#ifdef HAS_CTR +static int ablk_rfc3686_ctr_init(struct crypto_tfm *tfm) +{ + struct cryptd_ablkcipher *cryptd_tfm; + + cryptd_tfm = cryptd_alloc_ablkcipher( + "rfc3686(__driver-ctr-aes-aesni)", 0, 0); + if (IS_ERR(cryptd_tfm)) + return PTR_ERR(cryptd_tfm); + ablk_init_common(tfm, cryptd_tfm); + return 0; +} + +static struct crypto_alg ablk_rfc3686_ctr_alg = { + .cra_name = "rfc3686(ctr(aes))", + .cra_driver_name = "rfc3686-ctr-aes-aesni", + .cra_priority = 400, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct async_aes_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(ablk_rfc3686_ctr_alg.cra_list), + .cra_init = ablk_rfc3686_ctr_init, + .cra_exit = ablk_exit, + .cra_u = { + .ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE+CTR_RFC3686_NONCE_SIZE, + .max_keysize = AES_MAX_KEY_SIZE+CTR_RFC3686_NONCE_SIZE, + .ivsize = CTR_RFC3686_IV_SIZE, + .setkey = ablk_set_key, + .encrypt = ablk_encrypt, + .decrypt = ablk_decrypt, + .geniv = "seqiv", + }, + }, +}; #endif #ifdef HAS_LRW @@ -640,13 +746,17 @@ static int __init aesni_init(void) goto blk_ecb_err; if ((err = crypto_register_alg(&blk_cbc_alg))) goto blk_cbc_err; + if ((err = crypto_register_alg(&blk_ctr_alg))) + goto blk_ctr_err; if ((err = crypto_register_alg(&ablk_ecb_alg))) goto ablk_ecb_err; if ((err = crypto_register_alg(&ablk_cbc_alg))) goto ablk_cbc_err; -#ifdef HAS_CTR if ((err = crypto_register_alg(&ablk_ctr_alg))) goto ablk_ctr_err; +#ifdef HAS_CTR + if ((err = crypto_register_alg(&ablk_rfc3686_ctr_alg))) + goto ablk_rfc3686_ctr_err; #endif #ifdef HAS_LRW if ((err = crypto_register_alg(&ablk_lrw_alg))) @@ -675,13 +785,17 @@ ablk_pcbc_err: ablk_lrw_err: #endif #ifdef HAS_CTR + crypto_unregister_alg(&ablk_rfc3686_ctr_alg); +ablk_rfc3686_ctr_err: +#endif crypto_unregister_alg(&ablk_ctr_alg); ablk_ctr_err: -#endif crypto_unregister_alg(&ablk_cbc_alg); ablk_cbc_err: crypto_unregister_alg(&ablk_ecb_alg); ablk_ecb_err: + crypto_unregister_alg(&blk_ctr_alg); +blk_ctr_err: crypto_unregister_alg(&blk_cbc_alg); blk_cbc_err: crypto_unregister_alg(&blk_ecb_alg); @@ -705,10 +819,12 @@ static void __exit aesni_exit(void) crypto_unregister_alg(&ablk_lrw_alg); #endif #ifdef HAS_CTR - crypto_unregister_alg(&ablk_ctr_alg); + crypto_unregister_alg(&ablk_rfc3686_ctr_alg); #endif + crypto_unregister_alg(&ablk_ctr_alg); crypto_unregister_alg(&ablk_cbc_alg); crypto_unregister_alg(&ablk_ecb_alg); + crypto_unregister_alg(&blk_ctr_alg); crypto_unregister_alg(&blk_cbc_alg); crypto_unregister_alg(&blk_ecb_alg); crypto_unregister_alg(&__aesni_alg); diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 56f462cf22d2..aa2c39d968fc 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -85,7 +85,6 @@ extern int acpi_ioapic; extern int acpi_noirq; extern int acpi_strict; extern int acpi_disabled; -extern int acpi_ht; extern int acpi_pci_disabled; extern int acpi_skip_timer_override; extern int acpi_use_timer_override; @@ -97,7 +96,6 @@ void acpi_pic_sci_set_trigger(unsigned int, u16); static inline void disable_acpi(void) { acpi_disabled = 1; - acpi_ht = 0; acpi_pci_disabled = 1; acpi_noirq = 1; } diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h index 2f9047cfaaca..48f99f15452e 100644 --- a/arch/x86/include/asm/cache.h +++ b/arch/x86/include/asm/cache.h @@ -7,7 +7,7 @@ #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) #define INTERNODE_CACHE_SHIFT CONFIG_X86_INTERNODE_CACHE_SHIFT #define INTERNODE_CACHE_BYTES (1 << INTERNODE_CACHE_SHIFT) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index dca9c545f44e..468145914389 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -332,6 +332,7 @@ static __always_inline __pure bool __static_cpu_has(u8 bit) #endif } +#if __GNUC__ >= 4 #define static_cpu_has(bit) \ ( \ __builtin_constant_p(boot_cpu_has(bit)) ? \ @@ -340,6 +341,12 @@ static __always_inline __pure bool __static_cpu_has(u8 bit) __static_cpu_has(bit) : \ boot_cpu_has(bit) \ ) +#else +/* + * gcc 3.x is too stupid to do the static test; fall back to dynamic. + */ +#define static_cpu_has(bit) boot_cpu_has(bit) +#endif #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ diff --git a/arch/x86/include/asm/inst.h b/arch/x86/include/asm/inst.h index 14cf526091f9..280bf7fb6aba 100644 --- a/arch/x86/include/asm/inst.h +++ b/arch/x86/include/asm/inst.h @@ -7,7 +7,66 @@ #ifdef __ASSEMBLY__ +#define REG_NUM_INVALID 100 + +#define REG_TYPE_R64 0 +#define REG_TYPE_XMM 1 +#define REG_TYPE_INVALID 100 + + .macro R64_NUM opd r64 + \opd = REG_NUM_INVALID + .ifc \r64,%rax + \opd = 0 + .endif + .ifc \r64,%rcx + \opd = 1 + .endif + .ifc \r64,%rdx + \opd = 2 + .endif + .ifc \r64,%rbx + \opd = 3 + .endif + .ifc \r64,%rsp + \opd = 4 + .endif + .ifc \r64,%rbp + \opd = 5 + .endif + .ifc \r64,%rsi + \opd = 6 + .endif + .ifc \r64,%rdi + \opd = 7 + .endif + .ifc \r64,%r8 + \opd = 8 + .endif + .ifc \r64,%r9 + \opd = 9 + .endif + .ifc \r64,%r10 + \opd = 10 + .endif + .ifc \r64,%r11 + \opd = 11 + .endif + .ifc \r64,%r12 + \opd = 12 + .endif + .ifc \r64,%r13 + \opd = 13 + .endif + .ifc \r64,%r14 + \opd = 14 + .endif + .ifc \r64,%r15 + \opd = 15 + .endif + .endm + .macro XMM_NUM opd xmm + \opd = REG_NUM_INVALID .ifc \xmm,%xmm0 \opd = 0 .endif @@ -58,13 +117,25 @@ .endif .endm + .macro REG_TYPE type reg + R64_NUM reg_type_r64 \reg + XMM_NUM reg_type_xmm \reg + .if reg_type_r64 <> REG_NUM_INVALID + \type = REG_TYPE_R64 + .elseif reg_type_xmm <> REG_NUM_INVALID + \type = REG_TYPE_XMM + .else + \type = REG_TYPE_INVALID + .endif + .endm + .macro PFX_OPD_SIZE .byte 0x66 .endm - .macro PFX_REX opd1 opd2 - .if (\opd1 | \opd2) & 8 - .byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) + .macro PFX_REX opd1 opd2 W=0 + .if ((\opd1 | \opd2) & 8) || \W + .byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3) .endif .endm @@ -145,6 +216,25 @@ .byte 0x0f, 0x38, 0xdf MODRM 0xc0 aesdeclast_opd1 aesdeclast_opd2 .endm + + .macro MOVQ_R64_XMM opd1 opd2 + REG_TYPE movq_r64_xmm_opd1_type \opd1 + .if movq_r64_xmm_opd1_type == REG_TYPE_XMM + XMM_NUM movq_r64_xmm_opd1 \opd1 + R64_NUM movq_r64_xmm_opd2 \opd2 + .else + R64_NUM movq_r64_xmm_opd1 \opd1 + XMM_NUM movq_r64_xmm_opd2 \opd2 + .endif + PFX_OPD_SIZE + PFX_REX movq_r64_xmm_opd1 movq_r64_xmm_opd2 1 + .if movq_r64_xmm_opd1_type == REG_TYPE_XMM + .byte 0x0f, 0x7e + .else + .byte 0x0f, 0x6e + .endif + MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2 + .endm #endif #endif diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h new file mode 100644 index 000000000000..4470c9ad4a3e --- /dev/null +++ b/arch/x86/include/asm/intel_scu_ipc.h @@ -0,0 +1,55 @@ +#ifndef _ASM_X86_INTEL_SCU_IPC_H_ +#define _ASM_X86_INTEL_SCU_IPC_H_ + +/* Read single register */ +int intel_scu_ipc_ioread8(u16 addr, u8 *data); + +/* Read two sequential registers */ +int intel_scu_ipc_ioread16(u16 addr, u16 *data); + +/* Read four sequential registers */ +int intel_scu_ipc_ioread32(u16 addr, u32 *data); + +/* Read a vector */ +int intel_scu_ipc_readv(u16 *addr, u8 *data, int len); + +/* Write single register */ +int intel_scu_ipc_iowrite8(u16 addr, u8 data); + +/* Write two sequential registers */ +int intel_scu_ipc_iowrite16(u16 addr, u16 data); + +/* Write four sequential registers */ +int intel_scu_ipc_iowrite32(u16 addr, u32 data); + +/* Write a vector */ +int intel_scu_ipc_writev(u16 *addr, u8 *data, int len); + +/* Update single register based on the mask */ +int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask); + +/* + * Indirect register read + * Can be used when SCCB(System Controller Configuration Block) register + * HRIM(Honor Restricted IPC Messages) is set (bit 23) + */ +int intel_scu_ipc_register_read(u32 addr, u32 *data); + +/* + * Indirect register write + * Can be used when SCCB(System Controller Configuration Block) register + * HRIM(Honor Restricted IPC Messages) is set (bit 23) + */ +int intel_scu_ipc_register_write(u32 addr, u32 data); + +/* Issue commands to the SCU with or without data */ +int intel_scu_ipc_simple_command(int cmd, int sub); +int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, + u32 *out, int outlen); +/* I2C control api */ +int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data); + +/* Update FW version */ +int intel_scu_ipc_fw_update(u8 *buffer, u32 length); + +#endif diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h index f46b79f6c16c..ff90055c7f0b 100644 --- a/arch/x86/include/asm/kvm.h +++ b/arch/x86/include/asm/kvm.h @@ -21,6 +21,7 @@ #define __KVM_HAVE_PIT_STATE2 #define __KVM_HAVE_XEN_HVM #define __KVM_HAVE_VCPU_EVENTS +#define __KVM_HAVE_DEBUGREGS /* Architectural interrupt line count. */ #define KVM_NR_INTERRUPTS 256 @@ -257,6 +258,11 @@ struct kvm_reinject_control { /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 +#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 + +/* Interrupt shadow states */ +#define KVM_X86_SHADOW_INT_MOV_SS 0x01 +#define KVM_X86_SHADOW_INT_STI 0x02 /* for KVM_GET/SET_VCPU_EVENTS */ struct kvm_vcpu_events { @@ -271,7 +277,7 @@ struct kvm_vcpu_events { __u8 injected; __u8 nr; __u8 soft; - __u8 pad; + __u8 shadow; } interrupt; struct { __u8 injected; @@ -284,4 +290,13 @@ struct kvm_vcpu_events { __u32 reserved[10]; }; +/* for KVM_GET/SET_DEBUGREGS */ +struct kvm_debugregs { + __u64 db[4]; + __u64 dr6; + __u64 dr7; + __u64 flags; + __u64 reserved[9]; +}; + #endif /* _ASM_X86_KVM_H */ diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h index 7a6f54fa13ba..0b2729bf2070 100644 --- a/arch/x86/include/asm/kvm_emulate.h +++ b/arch/x86/include/asm/kvm_emulate.h @@ -11,6 +11,8 @@ #ifndef _ASM_X86_KVM_X86_EMULATE_H #define _ASM_X86_KVM_X86_EMULATE_H +#include <asm/desc_defs.h> + struct x86_emulate_ctxt; /* @@ -63,6 +65,15 @@ struct x86_emulate_ops { unsigned int bytes, struct kvm_vcpu *vcpu, u32 *error); /* + * write_std: Write bytes of standard (non-emulated/special) memory. + * Used for descriptor writing. + * @addr: [IN ] Linear address to which to write. + * @val: [OUT] Value write to memory, zero-extended to 'u_long'. + * @bytes: [IN ] Number of bytes to write to memory. + */ + int (*write_std)(unsigned long addr, void *val, + unsigned int bytes, struct kvm_vcpu *vcpu, u32 *error); + /* * fetch: Read bytes of standard (non-emulated/special) memory. * Used for instruction fetch. * @addr: [IN ] Linear address from which to read. @@ -109,6 +120,23 @@ struct x86_emulate_ops { unsigned int bytes, struct kvm_vcpu *vcpu); + int (*pio_in_emulated)(int size, unsigned short port, void *val, + unsigned int count, struct kvm_vcpu *vcpu); + + int (*pio_out_emulated)(int size, unsigned short port, const void *val, + unsigned int count, struct kvm_vcpu *vcpu); + + bool (*get_cached_descriptor)(struct desc_struct *desc, + int seg, struct kvm_vcpu *vcpu); + void (*set_cached_descriptor)(struct desc_struct *desc, + int seg, struct kvm_vcpu *vcpu); + u16 (*get_segment_selector)(int seg, struct kvm_vcpu *vcpu); + void (*set_segment_selector)(u16 sel, int seg, struct kvm_vcpu *vcpu); + void (*get_gdt)(struct desc_ptr *dt, struct kvm_vcpu *vcpu); + ulong (*get_cr)(int cr, struct kvm_vcpu *vcpu); + void (*set_cr)(int cr, ulong val, struct kvm_vcpu *vcpu); + int (*cpl)(struct kvm_vcpu *vcpu); + void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); }; /* Type, address-of, and value of an instruction's operand. */ @@ -124,6 +152,12 @@ struct fetch_cache { unsigned long end; }; +struct read_cache { + u8 data[1024]; + unsigned long pos; + unsigned long end; +}; + struct decode_cache { u8 twobyte; u8 b; @@ -139,7 +173,7 @@ struct decode_cache { u8 seg_override; unsigned int d; unsigned long regs[NR_VCPU_REGS]; - unsigned long eip, eip_orig; + unsigned long eip; /* modrm */ u8 modrm; u8 modrm_mod; @@ -151,16 +185,15 @@ struct decode_cache { void *modrm_ptr; unsigned long modrm_val; struct fetch_cache fetch; + struct read_cache io_read; }; -#define X86_SHADOW_INT_MOV_SS 1 -#define X86_SHADOW_INT_STI 2 - struct x86_emulate_ctxt { /* Register state before/after emulation. */ struct kvm_vcpu *vcpu; unsigned long eflags; + unsigned long eip; /* eip before instruction emulation */ /* Emulated execution mode, represented by an X86EMUL_MODE value. */ int mode; u32 cs_base; @@ -168,6 +201,7 @@ struct x86_emulate_ctxt { /* interruptibility state, as a result of execution of STI or MOV SS */ int interruptibility; + bool restart; /* restart string instruction after writeback */ /* decode cache */ struct decode_cache decode; }; @@ -194,5 +228,9 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops); int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops); +int emulator_task_switch(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 tss_selector, int reason, + bool has_error_code, u32 error_code); #endif /* _ASM_X86_KVM_X86_EMULATE_H */ diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 06d9e79ca37d..76f5483cffec 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -171,15 +171,15 @@ struct kvm_pte_chain { union kvm_mmu_page_role { unsigned word; struct { - unsigned glevels:4; unsigned level:4; + unsigned cr4_pae:1; unsigned quadrant:2; unsigned pad_for_nice_hex_output:6; unsigned direct:1; unsigned access:3; unsigned invalid:1; - unsigned cr4_pge:1; unsigned nxe:1; + unsigned cr0_wp:1; }; }; @@ -187,8 +187,6 @@ struct kvm_mmu_page { struct list_head link; struct hlist_node hash_link; - struct list_head oos_link; - /* * The following two entries are used to key the shadow page in the * hash table. @@ -204,9 +202,9 @@ struct kvm_mmu_page { * in this shadow page. */ DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); - int multimapped; /* More than one parent_pte? */ - int root_count; /* Currently serving as active root */ + bool multimapped; /* More than one parent_pte? */ bool unsync; + int root_count; /* Currently serving as active root */ unsigned int unsync_children; union { u64 *parent_pte; /* !multimapped */ @@ -224,14 +222,9 @@ struct kvm_pv_mmu_op_buffer { struct kvm_pio_request { unsigned long count; - int cur_count; - gva_t guest_gva; int in; int port; int size; - int string; - int down; - int rep; }; /* @@ -320,6 +313,7 @@ struct kvm_vcpu_arch { struct kvm_queued_exception { bool pending; bool has_error_code; + bool reinject; u8 nr; u32 error_code; } exception; @@ -362,8 +356,8 @@ struct kvm_vcpu_arch { u64 *mce_banks; /* used for guest single stepping over the given code position */ - u16 singlestep_cs; unsigned long singlestep_rip; + /* fields used by HYPER-V emulation */ u64 hv_vapic; }; @@ -389,6 +383,7 @@ struct kvm_arch { unsigned int n_free_mmu_pages; unsigned int n_requested_mmu_pages; unsigned int n_alloc_mmu_pages; + atomic_t invlpg_counter; struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; /* * Hash table of struct kvm_mmu_page. @@ -461,11 +456,6 @@ struct kvm_vcpu_stat { u32 nmi_injections; }; -struct descriptor_table { - u16 limit; - unsigned long base; -} __attribute__((packed)); - struct kvm_x86_ops { int (*cpu_has_kvm_support)(void); /* __init */ int (*disabled_by_bios)(void); /* __init */ @@ -503,12 +493,11 @@ struct kvm_x86_ops { void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); - void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); - void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); - void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); - void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt); - int (*get_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long *dest); - int (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value); + void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); + void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); + void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); + void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); + void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); @@ -527,7 +516,8 @@ struct kvm_x86_ops { void (*set_irq)(struct kvm_vcpu *vcpu); void (*set_nmi)(struct kvm_vcpu *vcpu); void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, - bool has_error_code, u32 error_code); + bool has_error_code, u32 error_code, + bool reinject); int (*interrupt_allowed)(struct kvm_vcpu *vcpu); int (*nmi_allowed)(struct kvm_vcpu *vcpu); bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); @@ -541,6 +531,8 @@ struct kvm_x86_ops { int (*get_lpage_level)(void); bool (*rdtscp_supported)(void); + void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); + const struct trace_print_flags *exit_reasons_str; }; @@ -587,23 +579,14 @@ int emulate_instruction(struct kvm_vcpu *vcpu, void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context); void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address); void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address); -void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, - unsigned long *rflags); -unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr); -void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long value, - unsigned long *rflags); void kvm_enable_efer_bits(u64); int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); struct x86_emulate_ctxt; -int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, - int size, unsigned port); -int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in, - int size, unsigned long count, int down, - gva_t address, int rep, unsigned port); +int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); int kvm_emulate_halt(struct kvm_vcpu *vcpu); int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address); @@ -616,12 +599,15 @@ int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); -int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason); +int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, + bool has_error_code, u32 error_code); void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); +int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); +int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); @@ -634,6 +620,8 @@ void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); +void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); +void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2, u32 error_code); bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); @@ -649,8 +637,6 @@ int emulator_write_emulated(unsigned long addr, unsigned int bytes, struct kvm_vcpu *vcpu); -unsigned long segment_base(u16 selector); - void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new, int bytes, @@ -675,7 +661,6 @@ void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); void kvm_enable_tdp(void); void kvm_disable_tdp(void); -int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); int complete_pio(struct kvm_vcpu *vcpu); bool kvm_check_iopl(struct kvm_vcpu *vcpu); @@ -724,23 +709,6 @@ static inline void kvm_load_ldt(u16 sel) asm("lldt %0" : : "rm"(sel)); } -static inline void kvm_get_idt(struct descriptor_table *table) -{ - asm("sidt %0" : "=m"(*table)); -} - -static inline void kvm_get_gdt(struct descriptor_table *table) -{ - asm("sgdt %0" : "=m"(*table)); -} - -static inline unsigned long kvm_read_tr_base(void) -{ - u16 tr; - asm("str %0" : "=g"(tr)); - return segment_base(tr); -} - #ifdef CONFIG_X86_64 static inline unsigned long read_msr(unsigned long msr) { @@ -826,4 +794,6 @@ int kvm_cpu_get_interrupt(struct kvm_vcpu *v); void kvm_define_shared_msr(unsigned index, u32 msr); void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); +bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); + #endif /* _ASM_X86_KVM_HOST_H */ diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h index ffae1420e7d7..05eba5e9a8e8 100644 --- a/arch/x86/include/asm/kvm_para.h +++ b/arch/x86/include/asm/kvm_para.h @@ -16,10 +16,23 @@ #define KVM_FEATURE_CLOCKSOURCE 0 #define KVM_FEATURE_NOP_IO_DELAY 1 #define KVM_FEATURE_MMU_OP 2 +/* This indicates that the new set of kvmclock msrs + * are available. The use of 0x11 and 0x12 is deprecated + */ +#define KVM_FEATURE_CLOCKSOURCE2 3 + +/* The last 8 bits are used to indicate how to interpret the flags field + * in pvclock structure. If no bits are set, all flags are ignored. + */ +#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT 24 #define MSR_KVM_WALL_CLOCK 0x11 #define MSR_KVM_SYSTEM_TIME 0x12 +/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */ +#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00 +#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01 + #define KVM_MAX_MMU_OP_BATCH 32 /* Operations for KVM_HC_MMU_OP */ diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6c3fdd631ed3..f32a4301c4d4 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -225,5 +225,13 @@ extern void mcheck_intel_therm_init(void); static inline void mcheck_intel_therm_init(void) { } #endif +/* + * Used by APEI to report memory error via /dev/mcelog + */ + +struct cper_sec_mem_err; +extern void apei_mce_report_mem_error(int corrected, + struct cper_sec_mem_err *mem_err); + #endif /* __KERNEL__ */ #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index bc473acfa7f9..8c7ae4318629 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -110,6 +110,7 @@ #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 +#define MSR_AMD64_DC_CFG 0xc0011022 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 @@ -202,8 +203,9 @@ #define MSR_IA32_EBL_CR_POWERON 0x0000002a #define MSR_IA32_FEATURE_CONTROL 0x0000003a -#define FEATURE_CONTROL_LOCKED (1<<0) -#define FEATURE_CONTROL_VMXON_ENABLED (1<<2) +#define FEATURE_CONTROL_LOCKED (1<<0) +#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) +#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) #define MSR_IA32_APICBASE 0x0000001b #define MSR_IA32_APICBASE_BSP (1<<8) @@ -235,6 +237,8 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0 +#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 + /* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 1a0422348d6d..cd2a31dc5fb8 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -53,6 +53,8 @@ extern int pcibios_last_bus; extern struct pci_bus *pci_root_bus; extern struct pci_ops pci_root_ops; +void pcibios_scan_specific_bus(int busn); + /* pci-irq.c */ struct irq_info { @@ -83,7 +85,7 @@ struct irq_routing_table { extern unsigned int pcibios_irq_mask; -extern spinlock_t pci_config_lock; +extern raw_spinlock_t pci_config_lock; extern int (*pcibios_enable_irq)(struct pci_dev *dev); extern void (*pcibios_disable_irq)(struct pci_dev *dev); diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index b05400a542ff..64a8ebff06fc 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -89,7 +89,8 @@ P4_CCCR_ENABLE) /* HT mask */ -#define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY) +#define P4_CCCR_MASK_HT \ + (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY) #define P4_GEN_ESCR_EMASK(class, name, bit) \ class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) diff --git a/arch/x86/include/asm/pvclock-abi.h b/arch/x86/include/asm/pvclock-abi.h index 6d93508f2626..35f2d1948ada 100644 --- a/arch/x86/include/asm/pvclock-abi.h +++ b/arch/x86/include/asm/pvclock-abi.h @@ -29,7 +29,8 @@ struct pvclock_vcpu_time_info { u64 system_time; u32 tsc_to_system_mul; s8 tsc_shift; - u8 pad[3]; + u8 flags; + u8 pad[2]; } __attribute__((__packed__)); /* 32 bytes */ struct pvclock_wall_clock { @@ -38,5 +39,6 @@ struct pvclock_wall_clock { u32 nsec; } __attribute__((__packed__)); +#define PVCLOCK_TSC_STABLE_BIT (1 << 0) #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_PVCLOCK_ABI_H */ diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h index 53235fd5f8ce..cd02f324aa6b 100644 --- a/arch/x86/include/asm/pvclock.h +++ b/arch/x86/include/asm/pvclock.h @@ -6,6 +6,7 @@ /* some helper functions for xen and kvm pv clock sources */ cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src); +void pvclock_set_flags(u8 flags); unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src); void pvclock_read_wallclock(struct pvclock_wall_clock *wall, struct pvclock_vcpu_time_info *vcpu, diff --git a/arch/x86/include/asm/rdc321x_defs.h b/arch/x86/include/asm/rdc321x_defs.h deleted file mode 100644 index c8e9c8bed3d0..000000000000 --- a/arch/x86/include/asm/rdc321x_defs.h +++ /dev/null @@ -1,12 +0,0 @@ -#define PFX "rdc321x: " - -/* General purpose configuration and data registers */ -#define RDC3210_CFGREG_ADDR 0x0CF8 -#define RDC3210_CFGREG_DATA 0x0CFC - -#define RDC321X_GPIO_CTRL_REG1 0x48 -#define RDC321X_GPIO_CTRL_REG2 0x84 -#define RDC321X_GPIO_DATA_REG1 0x4c -#define RDC321X_GPIO_DATA_REG2 0x88 - -#define RDC321X_MAX_GPIO 58 diff --git a/arch/x86/include/asm/scatterlist.h b/arch/x86/include/asm/scatterlist.h index 75af592677ec..fb0b1874396f 100644 --- a/arch/x86/include/asm/scatterlist.h +++ b/arch/x86/include/asm/scatterlist.h @@ -1,8 +1,9 @@ #ifndef _ASM_X86_SCATTERLIST_H #define _ASM_X86_SCATTERLIST_H -#define ISA_DMA_THRESHOLD (0x00ffffff) - #include <asm-generic/scatterlist.h> +#define ISA_DMA_THRESHOLD (0x00ffffff) +#define ARCH_HAS_SG_CHAIN + #endif /* _ASM_X86_SCATTERLIST_H */ diff --git a/arch/x86/include/asm/suspend_32.h b/arch/x86/include/asm/suspend_32.h index 48dcfa62ea07..fd921c3a6841 100644 --- a/arch/x86/include/asm/suspend_32.h +++ b/arch/x86/include/asm/suspend_32.h @@ -15,6 +15,8 @@ static inline int arch_prepare_suspend(void) { return 0; } struct saved_context { u16 es, fs, gs, ss; unsigned long cr0, cr2, cr3, cr4; + u64 misc_enable; + bool misc_enable_saved; struct desc_ptr gdt; struct desc_ptr idt; u16 ldt; diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h index 06284f42b759..8d942afae681 100644 --- a/arch/x86/include/asm/suspend_64.h +++ b/arch/x86/include/asm/suspend_64.h @@ -27,6 +27,8 @@ struct saved_context { u16 ds, es, fs, gs, ss; unsigned long gs_base, gs_kernel_base, fs_base; unsigned long cr0, cr2, cr3, cr4, cr8; + u64 misc_enable; + bool misc_enable_saved; unsigned long efer; u16 gdt_pad; u16 gdt_limit; diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 38638cd2fa4c..0e831059ac5a 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -81,7 +81,9 @@ struct __attribute__ ((__packed__)) vmcb_control_area { u32 event_inj_err; u64 nested_cr3; u64 lbr_ctl; - u8 reserved_5[832]; + u64 reserved_5; + u64 next_rip; + u8 reserved_6[816]; }; @@ -115,6 +117,10 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) +#define SVM_VM_CR_VALID_MASK 0x001fULL +#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL +#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL + struct __attribute__ ((__packed__)) vmcb_seg { u16 selector; u16 attrib; @@ -238,6 +244,7 @@ struct __attribute__ ((__packed__)) vmcb { #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 +#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 #define SVM_EXIT_READ_CR0 0x000 #define SVM_EXIT_READ_CR3 0x003 diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 62ba9400cc43..f0b6e5dbc5a0 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -239,8 +239,8 @@ static inline struct thread_info *current_thread_info(void) #define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */ #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ -#define TS_POLLING 0x0004 /* true if in idle loop - and not sleeping */ +#define TS_POLLING 0x0004 /* idle task polling need_resched, + skip sending interrupt */ #define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */ #define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index c5087d796587..21899cc31e52 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -53,33 +53,29 @@ extern int cpu_to_node_map[]; /* Returns the number of the node containing CPU 'cpu' */ -static inline int cpu_to_node(int cpu) +static inline int __cpu_to_node(int cpu) { return cpu_to_node_map[cpu]; } -#define early_cpu_to_node(cpu) cpu_to_node(cpu) +#define early_cpu_to_node __cpu_to_node +#define cpu_to_node __cpu_to_node #else /* CONFIG_X86_64 */ /* Mappings between logical cpu number and node number */ DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map); -/* Returns the number of the current Node. */ -DECLARE_PER_CPU(int, node_number); -#define numa_node_id() percpu_read(node_number) - #ifdef CONFIG_DEBUG_PER_CPU_MAPS -extern int cpu_to_node(int cpu); +/* + * override generic percpu implementation of cpu_to_node + */ +extern int __cpu_to_node(int cpu); +#define cpu_to_node __cpu_to_node + extern int early_cpu_to_node(int cpu); #else /* !CONFIG_DEBUG_PER_CPU_MAPS */ -/* Returns the number of the node containing CPU 'cpu' */ -static inline int cpu_to_node(int cpu) -{ - return per_cpu(x86_cpu_to_node_map, cpu); -} - /* Same function but used if called before per_cpu areas are setup */ static inline int early_cpu_to_node(int cpu) { @@ -170,6 +166,10 @@ static inline int numa_node_id(void) { return 0; } +/* + * indicate override: + */ +#define numa_node_id numa_node_id static inline int early_cpu_to_node(int cpu) { diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index fb9a080740ec..9e6779f7cf2d 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -25,6 +25,8 @@ * */ +#include <linux/types.h> + /* * Definitions of Primary Processor-Based VM-Execution Controls. */ @@ -120,6 +122,8 @@ enum vmcs_field { GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, GUEST_IA32_PAT = 0x00002804, GUEST_IA32_PAT_HIGH = 0x00002805, + GUEST_IA32_EFER = 0x00002806, + GUEST_IA32_EFER_HIGH = 0x00002807, GUEST_PDPTR0 = 0x0000280a, GUEST_PDPTR0_HIGH = 0x0000280b, GUEST_PDPTR1 = 0x0000280c, @@ -130,6 +134,8 @@ enum vmcs_field { GUEST_PDPTR3_HIGH = 0x00002811, HOST_IA32_PAT = 0x00002c00, HOST_IA32_PAT_HIGH = 0x00002c01, + HOST_IA32_EFER = 0x00002c02, + HOST_IA32_EFER_HIGH = 0x00002c03, PIN_BASED_VM_EXEC_CONTROL = 0x00004000, CPU_BASED_VM_EXEC_CONTROL = 0x00004002, EXCEPTION_BITMAP = 0x00004004, @@ -394,6 +400,10 @@ enum vmcs_field { #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" - +struct vmx_msr_entry { + u32 index; + u32 reserved; + u64 value; +} __aligned(16); #endif diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 488be461a380..60cc4058ed5f 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -63,7 +63,6 @@ EXPORT_SYMBOL(acpi_disabled); int acpi_noirq; /* skip ACPI IRQ initialization */ int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); -int acpi_ht __initdata = 1; /* enable HT */ int acpi_lapic; int acpi_ioapic; @@ -1501,9 +1500,8 @@ void __init acpi_boot_table_init(void) /* * If acpi_disabled, bail out - * One exception: acpi=ht continues far enough to enumerate LAPICs */ - if (acpi_disabled && !acpi_ht) + if (acpi_disabled) return; /* @@ -1534,9 +1532,8 @@ int __init early_acpi_boot_init(void) { /* * If acpi_disabled, bail out - * One exception: acpi=ht continues far enough to enumerate LAPICs */ - if (acpi_disabled && !acpi_ht) + if (acpi_disabled) return 1; /* @@ -1554,9 +1551,8 @@ int __init acpi_boot_init(void) /* * If acpi_disabled, bail out - * One exception: acpi=ht continues far enough to enumerate LAPICs */ - if (acpi_disabled && !acpi_ht) + if (acpi_disabled) return 1; acpi_table_parse(ACPI_SIG_BOOT, acpi_parse_sbf); @@ -1591,21 +1587,12 @@ static int __init parse_acpi(char *arg) /* acpi=force to over-ride black-list */ else if (strcmp(arg, "force") == 0) { acpi_force = 1; - acpi_ht = 1; acpi_disabled = 0; } /* acpi=strict disables out-of-spec workarounds */ else if (strcmp(arg, "strict") == 0) { acpi_strict = 1; } - /* Limit ACPI just to boot-time to enable HT */ - else if (strcmp(arg, "ht") == 0) { - if (!acpi_force) { - printk(KERN_WARNING "acpi=ht will be removed in Linux-2.6.35\n"); - disable_acpi(); - } - acpi_ht = 1; - } /* acpi=rsdt use RSDT instead of XSDT */ else if (strcmp(arg, "rsdt") == 0) { acpi_rsdt_forced = 1; diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index f9961034e557..82e508677b91 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -162,8 +162,6 @@ static int __init acpi_sleep_setup(char *str) #endif if (strncmp(str, "old_ordering", 12) == 0) acpi_old_suspend_ordering(); - if (strncmp(str, "sci_force_enable", 16) == 0) - acpi_set_sci_en_on_resume(); str = strchr(str, ','); if (str != NULL) str += strspn(str, ", \t"); diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S index 8ded418b0593..13ab720573e3 100644 --- a/arch/x86/kernel/acpi/wakeup_32.S +++ b/arch/x86/kernel/acpi/wakeup_32.S @@ -1,4 +1,4 @@ - .section .text.page_aligned + .section .text..page_aligned #include <linux/linkage.h> #include <asm/segment.h> #include <asm/page_types.h> diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c index fa5a1474cd18..0d20286d78c6 100644 --- a/arch/x86/kernel/amd_iommu.c +++ b/arch/x86/kernel/amd_iommu.c @@ -1487,6 +1487,7 @@ static int __attach_device(struct device *dev, struct protection_domain *domain) { struct iommu_dev_data *dev_data, *alias_data; + int ret; dev_data = get_dev_data(dev); alias_data = get_dev_data(dev_data->alias); @@ -1498,13 +1499,14 @@ static int __attach_device(struct device *dev, spin_lock(&domain->lock); /* Some sanity checks */ + ret = -EBUSY; if (alias_data->domain != NULL && alias_data->domain != domain) - return -EBUSY; + goto out_unlock; if (dev_data->domain != NULL && dev_data->domain != domain) - return -EBUSY; + goto out_unlock; /* Do real assignment */ if (dev_data->alias != dev) { @@ -1520,10 +1522,14 @@ static int __attach_device(struct device *dev, atomic_inc(&dev_data->bind); + ret = 0; + +out_unlock: + /* ready */ spin_unlock(&domain->lock); - return 0; + return ret; } /* @@ -2324,10 +2330,6 @@ int __init amd_iommu_init_dma_ops(void) iommu_detected = 1; swiotlb = 0; -#ifdef CONFIG_GART_IOMMU - gart_iommu_aperture_disabled = 1; - gart_iommu_aperture = 0; -#endif /* Make the driver finally visible to the drivers */ dma_ops = &amd_iommu_dma_ops; diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c index 3bacb4d0844c..3cc63e2b8dd4 100644 --- a/arch/x86/kernel/amd_iommu_init.c +++ b/arch/x86/kernel/amd_iommu_init.c @@ -287,8 +287,12 @@ static u8 * __init iommu_map_mmio_space(u64 address) { u8 *ret; - if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) + if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { + pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", + address); + pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); return NULL; + } ret = ioremap_nocache(address, MMIO_REGION_LENGTH); if (ret != NULL) @@ -1314,7 +1318,7 @@ static int __init amd_iommu_init(void) ret = amd_iommu_init_dma_ops(); if (ret) - goto free; + goto free_disable; amd_iommu_init_api(); @@ -1332,9 +1336,10 @@ static int __init amd_iommu_init(void) out: return ret; -free: +free_disable: disable_iommus(); +free: amd_iommu_uninit_devices(); free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, @@ -1353,6 +1358,15 @@ free: free_unity_maps(); +#ifdef CONFIG_GART_IOMMU + /* + * We failed to initialize the AMD IOMMU - try fallback to GART + * if possible. + */ + gart_iommu_init(); + +#endif + goto out; } diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 192cd7ee35cc..0bcc5aeda998 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -51,6 +51,7 @@ #include <asm/smp.h> #include <asm/mce.h> #include <asm/kvm_para.h> +#include <asm/tsc.h> unsigned int num_processors; @@ -1151,8 +1152,13 @@ static void __cpuinit lapic_setup_esr(void) */ void __cpuinit setup_local_APIC(void) { - unsigned int value; - int i, j; + unsigned int value, queued; + int i, j, acked = 0; + unsigned long long tsc = 0, ntsc; + long long max_loops = cpu_khz; + + if (cpu_has_tsc) + rdtscll(tsc); if (disable_apic) { arch_disable_smp_support(); @@ -1204,13 +1210,32 @@ void __cpuinit setup_local_APIC(void) * the interrupt. Hence a vector might get locked. It was noticed * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. */ - for (i = APIC_ISR_NR - 1; i >= 0; i--) { - value = apic_read(APIC_ISR + i*0x10); - for (j = 31; j >= 0; j--) { - if (value & (1<<j)) - ack_APIC_irq(); + do { + queued = 0; + for (i = APIC_ISR_NR - 1; i >= 0; i--) + queued |= apic_read(APIC_IRR + i*0x10); + + for (i = APIC_ISR_NR - 1; i >= 0; i--) { + value = apic_read(APIC_ISR + i*0x10); + for (j = 31; j >= 0; j--) { + if (value & (1<<j)) { + ack_APIC_irq(); + acked++; + } + } } - } + if (acked > 256) { + printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", + acked); + break; + } + if (cpu_has_tsc) { + rdtscll(ntsc); + max_loops = (cpu_khz << 10) - (ntsc - tsc); + } else + max_loops--; + } while (queued && max_loops > 0); + WARN_ON(max_loops <= 0); /* * Now that we are all set up, enable the APIC diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index cc83a002786e..68e4a6f2211e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1121,9 +1121,9 @@ void __cpuinit cpu_init(void) oist = &per_cpu(orig_ist, cpu); #ifdef CONFIG_NUMA - if (cpu != 0 && percpu_read(node_number) == 0 && - cpu_to_node(cpu) != NUMA_NO_NODE) - percpu_write(node_number, cpu_to_node(cpu)); + if (cpu != 0 && percpu_read(numa_node) == 0 && + early_cpu_to_node(cpu) != NUMA_NO_NODE) + set_numa_node(early_cpu_to_node(cpu)); #endif me = current; diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index 6f3dc8fbbfdc..7ec2123838e6 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -1497,8 +1497,8 @@ static struct cpufreq_driver cpufreq_amd64_driver = { * simply keep the boost-disable flag in sync with the current global * state. */ -static int __cpuinit cpb_notify(struct notifier_block *nb, unsigned long action, - void *hcpu) +static int cpb_notify(struct notifier_block *nb, unsigned long action, + void *hcpu) { unsigned cpu = (long)hcpu; u32 lo, hi; @@ -1528,7 +1528,7 @@ static int __cpuinit cpb_notify(struct notifier_block *nb, unsigned long action, return NOTIFY_OK; } -static struct notifier_block __cpuinitdata cpb_nb = { +static struct notifier_block cpb_nb = { .notifier_call = cpb_notify, }; diff --git a/arch/x86/kernel/cpu/mcheck/Makefile b/arch/x86/kernel/cpu/mcheck/Makefile index 4ac6d48fe11b..bb34b03af252 100644 --- a/arch/x86/kernel/cpu/mcheck/Makefile +++ b/arch/x86/kernel/cpu/mcheck/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o obj-$(CONFIG_X86_THERMAL_VECTOR) += therm_throt.o + +obj-$(CONFIG_ACPI_APEI) += mce-apei.o diff --git a/arch/x86/kernel/cpu/mcheck/mce-apei.c b/arch/x86/kernel/cpu/mcheck/mce-apei.c new file mode 100644 index 000000000000..745b54f9be89 --- /dev/null +++ b/arch/x86/kernel/cpu/mcheck/mce-apei.c @@ -0,0 +1,138 @@ +/* + * Bridge between MCE and APEI + * + * On some machine, corrected memory errors are reported via APEI + * generic hardware error source (GHES) instead of corrected Machine + * Check. These corrected memory errors can be reported to user space + * through /dev/mcelog via faking a corrected Machine Check, so that + * the error memory page can be offlined by /sbin/mcelog if the error + * count for one page is beyond the threshold. + * + * For fatal MCE, save MCE record into persistent storage via ERST, so + * that the MCE record can be logged after reboot via ERST. + * + * Copyright 2010 Intel Corp. + * Author: Huang Ying <ying.huang@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/acpi.h> +#include <linux/cper.h> +#include <acpi/apei.h> +#include <asm/mce.h> + +#include "mce-internal.h" + +void apei_mce_report_mem_error(int corrected, struct cper_sec_mem_err *mem_err) +{ + struct mce m; + + /* Only corrected MC is reported */ + if (!corrected) + return; + + mce_setup(&m); + m.bank = 1; + /* Fake a memory read corrected error with unknown channel */ + m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | 0x9f; + m.addr = mem_err->physical_addr; + mce_log(&m); + mce_notify_irq(); +} +EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); + +#define CPER_CREATOR_MCE \ + UUID_LE(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ + 0x64, 0x90, 0xb8, 0x9d) +#define CPER_SECTION_TYPE_MCE \ + UUID_LE(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ + 0x04, 0x4a, 0x38, 0xfc) + +/* + * CPER specification (in UEFI specification 2.3 appendix N) requires + * byte-packed. + */ +struct cper_mce_record { + struct cper_record_header hdr; + struct cper_section_descriptor sec_hdr; + struct mce mce; +} __packed; + +int apei_write_mce(struct mce *m) +{ + struct cper_mce_record rcd; + + memset(&rcd, 0, sizeof(rcd)); + memcpy(rcd.hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE); + rcd.hdr.revision = CPER_RECORD_REV; + rcd.hdr.signature_end = CPER_SIG_END; + rcd.hdr.section_count = 1; + rcd.hdr.error_severity = CPER_SER_FATAL; + /* timestamp, platform_id, partition_id are all invalid */ + rcd.hdr.validation_bits = 0; + rcd.hdr.record_length = sizeof(rcd); + rcd.hdr.creator_id = CPER_CREATOR_MCE; + rcd.hdr.notification_type = CPER_NOTIFY_MCE; + rcd.hdr.record_id = cper_next_record_id(); + rcd.hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR; + + rcd.sec_hdr.section_offset = (void *)&rcd.mce - (void *)&rcd; + rcd.sec_hdr.section_length = sizeof(rcd.mce); + rcd.sec_hdr.revision = CPER_SEC_REV; + /* fru_id and fru_text is invalid */ + rcd.sec_hdr.validation_bits = 0; + rcd.sec_hdr.flags = CPER_SEC_PRIMARY; + rcd.sec_hdr.section_type = CPER_SECTION_TYPE_MCE; + rcd.sec_hdr.section_severity = CPER_SER_FATAL; + + memcpy(&rcd.mce, m, sizeof(*m)); + + return erst_write(&rcd.hdr); +} + +ssize_t apei_read_mce(struct mce *m, u64 *record_id) +{ + struct cper_mce_record rcd; + ssize_t len; + + len = erst_read_next(&rcd.hdr, sizeof(rcd)); + if (len <= 0) + return len; + /* Can not skip other records in storage via ERST unless clear them */ + else if (len != sizeof(rcd) || + uuid_le_cmp(rcd.hdr.creator_id, CPER_CREATOR_MCE)) { + if (printk_ratelimit()) + pr_warning( + "MCE-APEI: Can not skip the unknown record in ERST"); + return -EIO; + } + + memcpy(m, &rcd.mce, sizeof(*m)); + *record_id = rcd.hdr.record_id; + + return sizeof(*m); +} + +/* Check whether there is record in ERST */ +int apei_check_mce(void) +{ + return erst_get_record_count(); +} + +int apei_clear_mce(u64 record_id) +{ + return erst_clear(record_id); +} diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h index 32996f9fab67..fefcc69ee8b5 100644 --- a/arch/x86/kernel/cpu/mcheck/mce-internal.h +++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h @@ -28,3 +28,26 @@ extern int mce_ser; extern struct mce_bank *mce_banks; +#ifdef CONFIG_ACPI_APEI +int apei_write_mce(struct mce *m); +ssize_t apei_read_mce(struct mce *m, u64 *record_id); +int apei_check_mce(void); +int apei_clear_mce(u64 record_id); +#else +static inline int apei_write_mce(struct mce *m) +{ + return -EINVAL; +} +static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id) +{ + return 0; +} +static inline int apei_check_mce(void) +{ + return 0; +} +static inline int apei_clear_mce(u64 record_id) +{ + return -EINVAL; +} +#endif diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 7a355ddcc64b..18cc42562250 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -36,6 +36,7 @@ #include <linux/fs.h> #include <linux/mm.h> #include <linux/debugfs.h> +#include <linux/edac_mce.h> #include <asm/processor.h> #include <asm/hw_irq.h> @@ -169,6 +170,15 @@ void mce_log(struct mce *mce) entry = rcu_dereference_check_mce(mcelog.next); for (;;) { /* + * If edac_mce is enabled, it will check the error type + * and will process it, if it is a known error. + * Otherwise, the error will be sent through mcelog + * interface + */ + if (edac_mce_parse(mce)) + return; + + /* * When the buffer fills up discard new entries. * Assume that the earlier errors are the more * interesting ones: @@ -264,7 +274,7 @@ static void wait_for_panic(void) static void mce_panic(char *msg, struct mce *final, char *exp) { - int i; + int i, apei_err = 0; if (!fake_panic) { /* @@ -287,8 +297,11 @@ static void mce_panic(char *msg, struct mce *final, char *exp) struct mce *m = &mcelog.entry[i]; if (!(m->status & MCI_STATUS_VAL)) continue; - if (!(m->status & MCI_STATUS_UC)) + if (!(m->status & MCI_STATUS_UC)) { print_mce(m); + if (!apei_err) + apei_err = apei_write_mce(m); + } } /* Now print uncorrected but with the final one last */ for (i = 0; i < MCE_LOG_LEN; i++) { @@ -297,11 +310,17 @@ static void mce_panic(char *msg, struct mce *final, char *exp) continue; if (!(m->status & MCI_STATUS_UC)) continue; - if (!final || memcmp(m, final, sizeof(struct mce))) + if (!final || memcmp(m, final, sizeof(struct mce))) { print_mce(m); + if (!apei_err) + apei_err = apei_write_mce(m); + } } - if (final) + if (final) { print_mce(final); + if (!apei_err) + apei_err = apei_write_mce(final); + } if (cpu_missing) printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); print_mce_tail(); @@ -1493,6 +1512,43 @@ static void collect_tscs(void *data) rdtscll(cpu_tsc[smp_processor_id()]); } +static int mce_apei_read_done; + +/* Collect MCE record of previous boot in persistent storage via APEI ERST. */ +static int __mce_read_apei(char __user **ubuf, size_t usize) +{ + int rc; + u64 record_id; + struct mce m; + + if (usize < sizeof(struct mce)) + return -EINVAL; + + rc = apei_read_mce(&m, &record_id); + /* Error or no more MCE record */ + if (rc <= 0) { + mce_apei_read_done = 1; + return rc; + } + rc = -EFAULT; + if (copy_to_user(*ubuf, &m, sizeof(struct mce))) + return rc; + /* + * In fact, we should have cleared the record after that has + * been flushed to the disk or sent to network in + * /sbin/mcelog, but we have no interface to support that now, + * so just clear it to avoid duplication. + */ + rc = apei_clear_mce(record_id); + if (rc) { + mce_apei_read_done = 1; + return rc; + } + *ubuf += sizeof(struct mce); + + return 0; +} + static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, loff_t *off) { @@ -1506,15 +1562,19 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, return -ENOMEM; mutex_lock(&mce_read_mutex); + + if (!mce_apei_read_done) { + err = __mce_read_apei(&buf, usize); + if (err || buf != ubuf) + goto out; + } + next = rcu_dereference_check_mce(mcelog.next); /* Only supports full reads right now */ - if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { - mutex_unlock(&mce_read_mutex); - kfree(cpu_tsc); - - return -EINVAL; - } + err = -EINVAL; + if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) + goto out; err = 0; prev = 0; @@ -1562,10 +1622,15 @@ timeout: memset(&mcelog.entry[i], 0, sizeof(struct mce)); } } + + if (err) + err = -EFAULT; + +out: mutex_unlock(&mce_read_mutex); kfree(cpu_tsc); - return err ? -EFAULT : buf - ubuf; + return err ? err : buf - ubuf; } static unsigned int mce_poll(struct file *file, poll_table *wait) @@ -1573,6 +1638,8 @@ static unsigned int mce_poll(struct file *file, poll_table *wait) poll_wait(file, &mce_wait, wait); if (rcu_dereference_check_mce(mcelog.next)) return POLLIN | POLLRDNORM; + if (!mce_apei_read_done && apei_check_mce()) + return POLLIN | POLLRDNORM; return 0; } diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c index 81c499eceb21..e1a0a3bf9716 100644 --- a/arch/x86/kernel/cpu/mcheck/therm_throt.c +++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c @@ -190,7 +190,7 @@ thermal_throttle_cpu_callback(struct notifier_block *nfb, mutex_unlock(&therm_cpu_lock); break; } - return err ? NOTIFY_BAD : NOTIFY_OK; + return notifier_from_errno(err); } static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index fd4db0db3708..5db5b7d65a18 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -106,6 +106,7 @@ struct cpu_hw_events { int n_events; int n_added; + int n_txn; int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ u64 tags[X86_PMC_IDX_MAX]; struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ @@ -983,6 +984,7 @@ static int x86_pmu_enable(struct perf_event *event) out: cpuc->n_events = n; cpuc->n_added += n - n0; + cpuc->n_txn += n - n0; return 0; } @@ -1089,6 +1091,14 @@ static void x86_pmu_disable(struct perf_event *event) struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int i; + /* + * If we're called during a txn, we don't need to do anything. + * The events never got scheduled and ->cancel_txn will truncate + * the event_list. + */ + if (cpuc->group_flag & PERF_EVENT_TXN_STARTED) + return; + x86_pmu_stop(event); for (i = 0; i < cpuc->n_events; i++) { @@ -1379,6 +1389,7 @@ static void x86_pmu_start_txn(const struct pmu *pmu) struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); cpuc->group_flag |= PERF_EVENT_TXN_STARTED; + cpuc->n_txn = 0; } /* @@ -1391,6 +1402,11 @@ static void x86_pmu_cancel_txn(const struct pmu *pmu) struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); cpuc->group_flag &= ~PERF_EVENT_TXN_STARTED; + /* + * Truncate the collected events. + */ + cpuc->n_added -= cpuc->n_txn; + cpuc->n_events -= cpuc->n_txn; } /* @@ -1419,6 +1435,12 @@ static int x86_pmu_commit_txn(const struct pmu *pmu) */ memcpy(cpuc->assign, assign, n*sizeof(int)); + /* + * Clear out the txn count so that ->cancel_txn() which gets + * run after ->commit_txn() doesn't undo things. + */ + cpuc->n_txn = 0; + return 0; } @@ -1717,7 +1739,11 @@ void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int ski */ regs->bp = rewind_frame_pointer(skip + 1); regs->cs = __KERNEL_CS; - local_save_flags(regs->flags); + /* + * We abuse bit 3 to pass exact information, see perf_misc_flags + * and the comment with PERF_EFLAGS_EXACT. + */ + regs->flags = 0; } unsigned long perf_instruction_pointer(struct pt_regs *regs) diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index 424fc8de68e4..ae85d69644d1 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -465,15 +465,21 @@ out: return rc; } -static inline void p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) +static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) { - unsigned long dummy; + int overflow = 0; + u32 low, high; - rdmsrl(hwc->config_base + hwc->idx, dummy); - if (dummy & P4_CCCR_OVF) { + rdmsr(hwc->config_base + hwc->idx, low, high); + + /* we need to check high bit for unflagged overflows */ + if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) { + overflow = 1; (void)checking_wrmsrl(hwc->config_base + hwc->idx, - ((u64)dummy) & ~P4_CCCR_OVF); + ((u64)low) & ~P4_CCCR_OVF); } + + return overflow; } static inline void p4_pmu_disable_event(struct perf_event *event) @@ -584,21 +590,15 @@ static int p4_pmu_handle_irq(struct pt_regs *regs) WARN_ON_ONCE(hwc->idx != idx); - /* - * FIXME: Redundant call, actually not needed - * but just to check if we're screwed - */ - p4_pmu_clear_cccr_ovf(hwc); + /* it might be unflagged overflow */ + handled = p4_pmu_clear_cccr_ovf(hwc); val = x86_perf_event_update(event); - if (val & (1ULL << (x86_pmu.cntval_bits - 1))) + if (!handled && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) continue; - /* - * event overflow - */ - handled = 1; - data.period = event->hw.last_period; + /* event overflow for sure */ + data.period = event->hw.last_period; if (!x86_perf_event_set_period(event)) continue; @@ -670,7 +670,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu) /* * ESCR address hashing is tricky, ESCRs are not sequential - * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03e0) and + * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and * the metric between any ESCRs is laid in range [0xa0,0xe1] * * so we make ~70% filled hashtable @@ -735,8 +735,9 @@ static int p4_get_escr_idx(unsigned int addr) { unsigned int idx = P4_ESCR_MSR_IDX(addr); - if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE || - !p4_escr_table[idx])) { + if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE || + !p4_escr_table[idx] || + p4_escr_table[idx] != addr)) { WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr); return -1; } @@ -762,7 +763,7 @@ static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign { unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; unsigned long escr_mask[BITS_TO_LONGS(P4_ESCR_MSR_TABLE_SIZE)]; - int cpu = raw_smp_processor_id(); + int cpu = smp_processor_id(); struct hw_perf_event *hwc; struct p4_event_bind *bind; unsigned int i, thread, num; diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index 8b862d5900fe..1b7b31ab7d86 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -170,7 +170,7 @@ static int __cpuinit cpuid_class_cpu_callback(struct notifier_block *nfb, cpuid_device_destroy(cpu); break; } - return err ? NOTIFY_BAD : NOTIFY_OK; + return notifier_from_errno(err); } static struct notifier_block __refdata cpuid_class_cpu_notifier = diff --git a/arch/x86/kernel/init_task.c b/arch/x86/kernel/init_task.c index 3a54dcb9cd0e..43e9ccf44947 100644 --- a/arch/x86/kernel/init_task.c +++ b/arch/x86/kernel/init_task.c @@ -34,7 +34,7 @@ EXPORT_SYMBOL(init_task); /* * per-CPU TSS segments. Threads are completely 'soft' on Linux, * no more per-task TSS's. The TSS size is kept cacheline-aligned - * so they are allowed to end up in the .data.cacheline_aligned + * so they are allowed to end up in the .data..cacheline_aligned * section. Since TSS's are completely CPU-local, we want them * on exact cacheline boundaries, to eliminate cacheline ping-pong. */ diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index feaeb0d3aa4f..eb9b76c716c2 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -29,6 +29,8 @@ #define KVM_SCALE 22 static int kvmclock = 1; +static int msr_kvm_system_time = MSR_KVM_SYSTEM_TIME; +static int msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK; static int parse_no_kvmclock(char *arg) { @@ -54,7 +56,8 @@ static unsigned long kvm_get_wallclock(void) low = (int)__pa_symbol(&wall_clock); high = ((u64)__pa_symbol(&wall_clock) >> 32); - native_write_msr(MSR_KVM_WALL_CLOCK, low, high); + + native_write_msr(msr_kvm_wall_clock, low, high); vcpu_time = &get_cpu_var(hv_clock); pvclock_read_wallclock(&wall_clock, vcpu_time, &ts); @@ -130,7 +133,8 @@ static int kvm_register_clock(char *txt) high = ((u64)__pa(&per_cpu(hv_clock, cpu)) >> 32); printk(KERN_INFO "kvm-clock: cpu %d, msr %x:%x, %s\n", cpu, high, low, txt); - return native_write_msr_safe(MSR_KVM_SYSTEM_TIME, low, high); + + return native_write_msr_safe(msr_kvm_system_time, low, high); } #ifdef CONFIG_X86_LOCAL_APIC @@ -165,14 +169,14 @@ static void __init kvm_smp_prepare_boot_cpu(void) #ifdef CONFIG_KEXEC static void kvm_crash_shutdown(struct pt_regs *regs) { - native_write_msr_safe(MSR_KVM_SYSTEM_TIME, 0, 0); + native_write_msr(msr_kvm_system_time, 0, 0); native_machine_crash_shutdown(regs); } #endif static void kvm_shutdown(void) { - native_write_msr_safe(MSR_KVM_SYSTEM_TIME, 0, 0); + native_write_msr(msr_kvm_system_time, 0, 0); native_machine_shutdown(); } @@ -181,27 +185,37 @@ void __init kvmclock_init(void) if (!kvm_para_available()) return; - if (kvmclock && kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE)) { - if (kvm_register_clock("boot clock")) - return; - pv_time_ops.sched_clock = kvm_clock_read; - x86_platform.calibrate_tsc = kvm_get_tsc_khz; - x86_platform.get_wallclock = kvm_get_wallclock; - x86_platform.set_wallclock = kvm_set_wallclock; + if (kvmclock && kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE2)) { + msr_kvm_system_time = MSR_KVM_SYSTEM_TIME_NEW; + msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK_NEW; + } else if (!(kvmclock && kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE))) + return; + + printk(KERN_INFO "kvm-clock: Using msrs %x and %x", + msr_kvm_system_time, msr_kvm_wall_clock); + + if (kvm_register_clock("boot clock")) + return; + pv_time_ops.sched_clock = kvm_clock_read; + x86_platform.calibrate_tsc = kvm_get_tsc_khz; + x86_platform.get_wallclock = kvm_get_wallclock; + x86_platform.set_wallclock = kvm_set_wallclock; #ifdef CONFIG_X86_LOCAL_APIC - x86_cpuinit.setup_percpu_clockev = - kvm_setup_secondary_clock; + x86_cpuinit.setup_percpu_clockev = + kvm_setup_secondary_clock; #endif #ifdef CONFIG_SMP - smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu; + smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu; #endif - machine_ops.shutdown = kvm_shutdown; + machine_ops.shutdown = kvm_shutdown; #ifdef CONFIG_KEXEC - machine_ops.crash_shutdown = kvm_crash_shutdown; + machine_ops.crash_shutdown = kvm_crash_shutdown; #endif - kvm_get_preset_lpj(); - clocksource_register(&kvm_clock); - pv_info.paravirt_enabled = 1; - pv_info.name = "KVM"; - } + kvm_get_preset_lpj(); + clocksource_register(&kvm_clock); + pv_info.paravirt_enabled = 1; + pv_info.name = "KVM"; + + if (kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE_STABLE_BIT)) + pvclock_set_flags(PVCLOCK_TSC_STABLE_BIT); } diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 2cd8c544e41a..fa6551d36c10 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -260,6 +260,7 @@ static void microcode_dev_exit(void) } MODULE_ALIAS_MISCDEV(MICROCODE_MINOR); +MODULE_ALIAS("devname:cpu/microcode"); #else #define microcode_dev_init() 0 #define microcode_dev_exit() do { } while (0) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4d4468e9f47c..7bf2dc4c8f70 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -230,7 +230,7 @@ static int __cpuinit msr_class_cpu_callback(struct notifier_block *nfb, msr_device_destroy(cpu); break; } - return err ? NOTIFY_BAD : NOTIFY_OK; + return notifier_from_errno(err); } static struct notifier_block __refdata msr_class_cpu_notifier = { diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c index 7d2829dde20e..a5bc528d4328 100644 --- a/arch/x86/kernel/pci-swiotlb.c +++ b/arch/x86/kernel/pci-swiotlb.c @@ -31,8 +31,6 @@ static struct dma_map_ops swiotlb_dma_ops = { .free_coherent = swiotlb_free_coherent, .sync_single_for_cpu = swiotlb_sync_single_for_cpu, .sync_single_for_device = swiotlb_sync_single_for_device, - .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu, - .sync_single_range_for_device = swiotlb_sync_single_range_for_device, .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, .sync_sg_for_device = swiotlb_sync_sg_for_device, .map_sg = swiotlb_map_sg_attrs, diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c index 03801f2f761f..239427ca02af 100644 --- a/arch/x86/kernel/pvclock.c +++ b/arch/x86/kernel/pvclock.c @@ -31,8 +31,16 @@ struct pvclock_shadow_time { u32 tsc_to_nsec_mul; int tsc_shift; u32 version; + u8 flags; }; +static u8 valid_flags __read_mostly = 0; + +void pvclock_set_flags(u8 flags) +{ + valid_flags = flags; +} + /* * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction, * yielding a 64-bit result. @@ -91,6 +99,7 @@ static unsigned pvclock_get_time_values(struct pvclock_shadow_time *dst, dst->system_timestamp = src->system_time; dst->tsc_to_nsec_mul = src->tsc_to_system_mul; dst->tsc_shift = src->tsc_shift; + dst->flags = src->flags; rmb(); /* test version after fetching data */ } while ((src->version & 1) || (dst->version != src->version)); @@ -109,11 +118,14 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src) return pv_tsc_khz; } +static atomic64_t last_value = ATOMIC64_INIT(0); + cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src) { struct pvclock_shadow_time shadow; unsigned version; cycle_t ret, offset; + u64 last; do { version = pvclock_get_time_values(&shadow, src); @@ -123,6 +135,31 @@ cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src) barrier(); } while (version != src->version); + if ((valid_flags & PVCLOCK_TSC_STABLE_BIT) && + (shadow.flags & PVCLOCK_TSC_STABLE_BIT)) + return ret; + + /* + * Assumption here is that last_value, a global accumulator, always goes + * forward. If we are less than that, we should not be much smaller. + * We assume there is an error marging we're inside, and then the correction + * does not sacrifice accuracy. + * + * For reads: global may have changed between test and return, + * but this means someone else updated poked the clock at a later time. + * We just need to make sure we are not seeing a backwards event. + * + * For updates: last_value = ret is not enough, since two vcpus could be + * updating at the same time, and one of them could be slightly behind, + * making the assumption that last_value always go forward fail to hold. + */ + last = atomic64_read(&last_value); + do { + if (ret < last) + return last; + last = atomic64_cmpxchg(&last_value, last, ret); + } while (unlikely(last != ret)); + return ret; } diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index e8029896309a..b4ae4acbd031 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -676,6 +676,17 @@ static struct dmi_system_id __initdata bad_bios_dmi_table[] = { DMI_MATCH(DMI_BOARD_NAME, "DG45FC"), }, }, + /* + * The Dell Inspiron Mini 1012 has DMI_BIOS_VENDOR = "Dell Inc.", so + * match on the product name. + */ + { + .callback = dmi_low_memory_corruption, + .ident = "Phoenix BIOS", + .matches = { + DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1012"), + }, + }, #endif {} }; diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index ef6370b00e70..de3b63ae3da2 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -21,12 +21,6 @@ #include <asm/cpu.h> #include <asm/stackprotector.h> -#ifdef CONFIG_DEBUG_PER_CPU_MAPS -# define DBG(fmt, ...) pr_dbg(fmt, ##__VA_ARGS__) -#else -# define DBG(fmt, ...) do { if (0) pr_dbg(fmt, ##__VA_ARGS__); } while (0) -#endif - DEFINE_PER_CPU(int, cpu_number); EXPORT_PER_CPU_SYMBOL(cpu_number); @@ -247,7 +241,7 @@ void __init setup_per_cpu_areas(void) #endif #endif /* - * Up to this point, the boot CPU has been using .data.init + * Up to this point, the boot CPU has been using .init.data * area. Reload any changed state for the boot CPU. */ if (cpu == boot_cpu_id) @@ -265,10 +259,10 @@ void __init setup_per_cpu_areas(void) #if defined(CONFIG_X86_64) && defined(CONFIG_NUMA) /* - * make sure boot cpu node_number is right, when boot cpu is on the + * make sure boot cpu numa_node is right, when boot cpu is on the * node that doesn't have mem installed */ - per_cpu(node_number, boot_cpu_id) = cpu_to_node(boot_cpu_id); + set_cpu_numa_node(boot_cpu_id, early_cpu_to_node(boot_cpu_id)); #endif /* Setup node to cpumask map */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 763d815e27a0..c4f33b2e77d6 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -686,7 +686,7 @@ static void __cpuinit do_fork_idle(struct work_struct *work) static void __cpuinit announce_cpu(int cpu, int apicid) { static int current_node = -1; - int node = cpu_to_node(cpu); + int node = early_cpu_to_node(cpu); if (system_state == SYSTEM_BOOTING) { if (node != current_node) { @@ -1215,9 +1215,17 @@ __init void prefill_possible_map(void) if (!num_processors) num_processors = 1; - if (setup_possible_cpus == -1) - possible = num_processors + disabled_cpus; - else + i = setup_max_cpus ?: 1; + if (setup_possible_cpus == -1) { + possible = num_processors; +#ifdef CONFIG_HOTPLUG_CPU + if (setup_max_cpus) + possible += disabled_cpus; +#else + if (possible > i) + possible = i; +#endif + } else possible = setup_possible_cpus; total_cpus = max_t(int, possible, num_processors + disabled_cpus); @@ -1230,11 +1238,23 @@ __init void prefill_possible_map(void) possible = nr_cpu_ids; } +#ifdef CONFIG_HOTPLUG_CPU + if (!setup_max_cpus) +#endif + if (possible > i) { + printk(KERN_WARNING + "%d Processors exceeds max_cpus limit of %u\n", + possible, setup_max_cpus); + possible = i; + } + printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", possible, max_t(int, possible - num_processors, 0)); for (i = 0; i < possible; i++) set_cpu_possible(i, true); + for (; i < NR_CPUS; i++) + set_cpu_possible(i, false); nr_cpu_ids = possible; } diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c index cc2c60474fd0..c2f1b26141e2 100644 --- a/arch/x86/kernel/tboot.c +++ b/arch/x86/kernel/tboot.c @@ -46,6 +46,7 @@ /* Global pointer to shared data; NULL means no measured launch. */ struct tboot *tboot __read_mostly; +EXPORT_SYMBOL(tboot); /* timeout for APs (in secs) to enter wait-for-SIPI state during shutdown */ #define AP_WAIT_TIMEOUT 1 diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 2cc249718c46..d0bb52296fa3 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -97,7 +97,7 @@ SECTIONS HEAD_TEXT #ifdef CONFIG_X86_32 . = ALIGN(PAGE_SIZE); - *(.text.page_aligned) + *(.text..page_aligned) #endif . = ALIGN(8); _stext = .; @@ -305,7 +305,7 @@ SECTIONS . = ALIGN(PAGE_SIZE); .bss : AT(ADDR(.bss) - LOAD_OFFSET) { __bss_start = .; - *(.bss.page_aligned) + *(.bss..page_aligned) *(.bss) . = ALIGN(4); __bss_stop = .; diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 4dade6ac0827..5ac0bb465ed6 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -33,6 +33,7 @@ #include <asm/kvm_emulate.h> #include "x86.h" +#include "tss.h" /* * Opcode effective-address decode tables. @@ -50,6 +51,8 @@ #define DstReg (2<<1) /* Register operand. */ #define DstMem (3<<1) /* Memory operand. */ #define DstAcc (4<<1) /* Destination Accumulator */ +#define DstDI (5<<1) /* Destination is in ES:(E)DI */ +#define DstMem64 (6<<1) /* 64bit memory operand */ #define DstMask (7<<1) /* Source operand type. */ #define SrcNone (0<<4) /* No source operand. */ @@ -63,6 +66,7 @@ #define SrcOne (7<<4) /* Implied '1' */ #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ #define SrcImmU (9<<4) /* Immediate operand, unsigned */ +#define SrcSI (0xa<<4) /* Source is in the DS:RSI */ #define SrcMask (0xf<<4) /* Generic ModRM decode. */ #define ModRM (1<<8) @@ -85,6 +89,9 @@ #define Src2ImmByte (2<<29) #define Src2One (3<<29) #define Src2Imm16 (4<<29) +#define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be + in memory and second argument is located + immediately after the first one in memory. */ #define Src2Mask (7<<29) enum { @@ -147,8 +154,8 @@ static u32 opcode_table[256] = { 0, 0, 0, 0, /* 0x68 - 0x6F */ SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, - SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ - SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ + DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */ + SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */ /* 0x70 - 0x77 */ SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, @@ -173,12 +180,12 @@ static u32 opcode_table[256] = { /* 0xA0 - 0xA7 */ ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, - ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, - ByteOp | ImplicitOps | String, ImplicitOps | String, + ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String, + ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String, /* 0xA8 - 0xAF */ - 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, - ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, - ByteOp | ImplicitOps | String, ImplicitOps | String, + 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String, + ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String, + ByteOp | DstDI | String, DstDI | String, /* 0xB0 - 0xB7 */ ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, @@ -204,13 +211,13 @@ static u32 opcode_table[256] = { 0, 0, 0, 0, 0, 0, 0, 0, /* 0xE0 - 0xE7 */ 0, 0, 0, 0, - ByteOp | SrcImmUByte, SrcImmUByte, - ByteOp | SrcImmUByte, SrcImmUByte, + ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, + ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, /* 0xE8 - 0xEF */ SrcImm | Stack, SrcImm | ImplicitOps, SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps, - SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, - SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, + SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, + SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, /* 0xF0 - 0xF7 */ 0, 0, 0, 0, ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3, @@ -343,7 +350,8 @@ static u32 group_table[] = { [Group5*8] = DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, SrcMem | ModRM | Stack, 0, - SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0, + SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps, + SrcMem | ModRM | Stack, 0, [Group7*8] = 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv, SrcNone | ModRM | DstMem | Mov, 0, @@ -353,14 +361,14 @@ static u32 group_table[] = { DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, [Group9*8] = - 0, ImplicitOps | ModRM | Lock, 0, 0, 0, 0, 0, 0, + 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0, }; static u32 group2_table[] = { [Group7*8] = - SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM, + SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv, SrcNone | ModRM | DstMem | Mov, 0, - SrcMem16 | ModRM | Mov, 0, + SrcMem16 | ModRM | Mov | Priv, 0, [Group9*8] = 0, 0, 0, 0, 0, 0, 0, 0, }; @@ -562,7 +570,7 @@ static u32 group2_table[] = { #define insn_fetch(_type, _size, _eip) \ ({ unsigned long _x; \ rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ - if (rc != 0) \ + if (rc != X86EMUL_CONTINUE) \ goto done; \ (_eip) += (_size); \ (_type)_x; \ @@ -638,40 +646,40 @@ static unsigned long ss_base(struct x86_emulate_ctxt *ctxt) static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops, - unsigned long linear, u8 *dest) + unsigned long eip, u8 *dest) { struct fetch_cache *fc = &ctxt->decode.fetch; int rc; - int size; + int size, cur_size; - if (linear < fc->start || linear >= fc->end) { - size = min(15UL, PAGE_SIZE - offset_in_page(linear)); - rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL); - if (rc) + if (eip == fc->end) { + cur_size = fc->end - fc->start; + size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); + rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, + size, ctxt->vcpu, NULL); + if (rc != X86EMUL_CONTINUE) return rc; - fc->start = linear; - fc->end = linear + size; + fc->end += size; } - *dest = fc->data[linear - fc->start]; - return 0; + *dest = fc->data[eip - fc->start]; + return X86EMUL_CONTINUE; } static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops, unsigned long eip, void *dest, unsigned size) { - int rc = 0; + int rc; /* x86 instructions are limited to 15 bytes. */ - if (eip + size - ctxt->decode.eip_orig > 15) + if (eip + size - ctxt->eip > 15) return X86EMUL_UNHANDLEABLE; - eip += ctxt->cs_base; while (size--) { rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); - if (rc) + if (rc != X86EMUL_CONTINUE) return rc; } - return 0; + return X86EMUL_CONTINUE; } /* @@ -702,7 +710,7 @@ static int read_descriptor(struct x86_emulate_ctxt *ctxt, *address = 0; rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, ctxt->vcpu, NULL); - if (rc) + if (rc != X86EMUL_CONTINUE) return rc; rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, ctxt->vcpu, NULL); @@ -782,7 +790,7 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt, struct decode_cache *c = &ctxt->decode; u8 sib; int index_reg = 0, base_reg = 0, scale; - int rc = 0; + int rc = X86EMUL_CONTINUE; if (c->rex_prefix) { c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ @@ -895,7 +903,7 @@ static int decode_abs(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - int rc = 0; + int rc = X86EMUL_CONTINUE; switch (c->ad_bytes) { case 2: @@ -916,14 +924,18 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - int rc = 0; + int rc = X86EMUL_CONTINUE; int mode = ctxt->mode; int def_op_bytes, def_ad_bytes, group; - /* Shadow copy of register state. Committed on successful emulation. */ + /* we cannot decode insn before we complete previous rep insn */ + WARN_ON(ctxt->restart); + + /* Shadow copy of register state. Committed on successful emulation. */ memset(c, 0, sizeof(struct decode_cache)); - c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu); + c->eip = ctxt->eip; + c->fetch.start = c->fetch.end = c->eip; ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS); memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); @@ -1015,11 +1027,6 @@ done_prefixes: } } - if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { - kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction"); - return -1; - } - if (c->d & Group) { group = c->d & GroupMask; c->modrm = insn_fetch(u8, 1, c->eip); @@ -1046,7 +1053,7 @@ done_prefixes: rc = decode_modrm(ctxt, ops); else if (c->d & MemAbs) rc = decode_abs(ctxt, ops); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; if (!c->has_seg_override) @@ -1057,6 +1064,10 @@ done_prefixes: if (c->ad_bytes != 8) c->modrm_ea = (u32)c->modrm_ea; + + if (c->rip_relative) + c->modrm_ea += c->eip; + /* * Decode and fetch the source operand: register, memory * or immediate. @@ -1091,6 +1102,8 @@ done_prefixes: break; } c->src.type = OP_MEM; + c->src.ptr = (unsigned long *)c->modrm_ea; + c->src.val = 0; break; case SrcImm: case SrcImmU: @@ -1139,6 +1152,14 @@ done_prefixes: c->src.bytes = 1; c->src.val = 1; break; + case SrcSI: + c->src.type = OP_MEM; + c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; + c->src.ptr = (unsigned long *) + register_address(c, seg_override_base(ctxt, c), + c->regs[VCPU_REGS_RSI]); + c->src.val = 0; + break; } /* @@ -1168,6 +1189,12 @@ done_prefixes: c->src2.bytes = 1; c->src2.val = 1; break; + case Src2Mem16: + c->src2.type = OP_MEM; + c->src2.bytes = 2; + c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes); + c->src2.val = 0; + break; } /* Decode and fetch the destination operand: register or memory. */ @@ -1180,6 +1207,7 @@ done_prefixes: c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); break; case DstMem: + case DstMem64: if ((c->d & ModRM) && c->modrm_mod == 3) { c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; c->dst.type = OP_REG; @@ -1188,12 +1216,24 @@ done_prefixes: break; } c->dst.type = OP_MEM; + c->dst.ptr = (unsigned long *)c->modrm_ea; + if ((c->d & DstMask) == DstMem64) + c->dst.bytes = 8; + else + c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; + c->dst.val = 0; + if (c->d & BitOp) { + unsigned long mask = ~(c->dst.bytes * 8 - 1); + + c->dst.ptr = (void *)c->dst.ptr + + (c->src.val & mask) / 8; + } break; case DstAcc: c->dst.type = OP_REG; - c->dst.bytes = c->op_bytes; + c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; c->dst.ptr = &c->regs[VCPU_REGS_RAX]; - switch (c->op_bytes) { + switch (c->dst.bytes) { case 1: c->dst.val = *(u8 *)c->dst.ptr; break; @@ -1203,18 +1243,248 @@ done_prefixes: case 4: c->dst.val = *(u32 *)c->dst.ptr; break; + case 8: + c->dst.val = *(u64 *)c->dst.ptr; + break; } c->dst.orig_val = c->dst.val; break; + case DstDI: + c->dst.type = OP_MEM; + c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; + c->dst.ptr = (unsigned long *) + register_address(c, es_base(ctxt), + c->regs[VCPU_REGS_RDI]); + c->dst.val = 0; + break; } - if (c->rip_relative) - c->modrm_ea += c->eip; - done: return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; } +static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + unsigned int size, unsigned short port, + void *dest) +{ + struct read_cache *rc = &ctxt->decode.io_read; + + if (rc->pos == rc->end) { /* refill pio read ahead */ + struct decode_cache *c = &ctxt->decode; + unsigned int in_page, n; + unsigned int count = c->rep_prefix ? + address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; + in_page = (ctxt->eflags & EFLG_DF) ? + offset_in_page(c->regs[VCPU_REGS_RDI]) : + PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); + n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, + count); + if (n == 0) + n = 1; + rc->pos = rc->end = 0; + if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) + return 0; + rc->end = n * size; + } + + memcpy(dest, rc->data + rc->pos, size); + rc->pos += size; + return 1; +} + +static u32 desc_limit_scaled(struct desc_struct *desc) +{ + u32 limit = get_desc_limit(desc); + + return desc->g ? (limit << 12) | 0xfff : limit; +} + +static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 selector, struct desc_ptr *dt) +{ + if (selector & 1 << 2) { + struct desc_struct desc; + memset (dt, 0, sizeof *dt); + if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) + return; + + dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ + dt->address = get_desc_base(&desc); + } else + ops->get_gdt(dt, ctxt->vcpu); +} + +/* allowed just for 8 bytes segments */ +static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 selector, struct desc_struct *desc) +{ + struct desc_ptr dt; + u16 index = selector >> 3; + int ret; + u32 err; + ulong addr; + + get_descriptor_table_ptr(ctxt, ops, selector, &dt); + + if (dt.size < index * 8 + 7) { + kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); + return X86EMUL_PROPAGATE_FAULT; + } + addr = dt.address + index * 8; + ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); + if (ret == X86EMUL_PROPAGATE_FAULT) + kvm_inject_page_fault(ctxt->vcpu, addr, err); + + return ret; +} + +/* allowed just for 8 bytes segments */ +static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 selector, struct desc_struct *desc) +{ + struct desc_ptr dt; + u16 index = selector >> 3; + u32 err; + ulong addr; + int ret; + + get_descriptor_table_ptr(ctxt, ops, selector, &dt); + + if (dt.size < index * 8 + 7) { + kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); + return X86EMUL_PROPAGATE_FAULT; + } + + addr = dt.address + index * 8; + ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); + if (ret == X86EMUL_PROPAGATE_FAULT) + kvm_inject_page_fault(ctxt->vcpu, addr, err); + + return ret; +} + +static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 selector, int seg) +{ + struct desc_struct seg_desc; + u8 dpl, rpl, cpl; + unsigned err_vec = GP_VECTOR; + u32 err_code = 0; + bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ + int ret; + + memset(&seg_desc, 0, sizeof seg_desc); + + if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) + || ctxt->mode == X86EMUL_MODE_REAL) { + /* set real mode segment descriptor */ + set_desc_base(&seg_desc, selector << 4); + set_desc_limit(&seg_desc, 0xffff); + seg_desc.type = 3; + seg_desc.p = 1; + seg_desc.s = 1; + goto load; + } + + /* NULL selector is not valid for TR, CS and SS */ + if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) + && null_selector) + goto exception; + + /* TR should be in GDT only */ + if (seg == VCPU_SREG_TR && (selector & (1 << 2))) + goto exception; + + if (null_selector) /* for NULL selector skip all following checks */ + goto load; + + ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); + if (ret != X86EMUL_CONTINUE) + return ret; + + err_code = selector & 0xfffc; + err_vec = GP_VECTOR; + + /* can't load system descriptor into segment selecor */ + if (seg <= VCPU_SREG_GS && !seg_desc.s) + goto exception; + + if (!seg_desc.p) { + err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; + goto exception; + } + + rpl = selector & 3; + dpl = seg_desc.dpl; + cpl = ops->cpl(ctxt->vcpu); + + switch (seg) { + case VCPU_SREG_SS: + /* + * segment is not a writable data segment or segment + * selector's RPL != CPL or segment selector's RPL != CPL + */ + if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) + goto exception; + break; + case VCPU_SREG_CS: + if (!(seg_desc.type & 8)) + goto exception; + + if (seg_desc.type & 4) { + /* conforming */ + if (dpl > cpl) + goto exception; + } else { + /* nonconforming */ + if (rpl > cpl || dpl != cpl) + goto exception; + } + /* CS(RPL) <- CPL */ + selector = (selector & 0xfffc) | cpl; + break; + case VCPU_SREG_TR: + if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) + goto exception; + break; + case VCPU_SREG_LDTR: + if (seg_desc.s || seg_desc.type != 2) + goto exception; + break; + default: /* DS, ES, FS, or GS */ + /* + * segment is not a data or readable code segment or + * ((segment is a data or nonconforming code segment) + * and (both RPL and CPL > DPL)) + */ + if ((seg_desc.type & 0xa) == 0x8 || + (((seg_desc.type & 0xc) != 0xc) && + (rpl > dpl && cpl > dpl))) + goto exception; + break; + } + + if (seg_desc.s) { + /* mark segment as accessed */ + seg_desc.type |= 1; + ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); + if (ret != X86EMUL_CONTINUE) + return ret; + } +load: + ops->set_segment_selector(selector, seg, ctxt->vcpu); + ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); + return X86EMUL_CONTINUE; +exception: + kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code); + return X86EMUL_PROPAGATE_FAULT; +} + static inline void emulate_push(struct x86_emulate_ctxt *ctxt) { struct decode_cache *c = &ctxt->decode; @@ -1251,7 +1521,7 @@ static int emulate_popf(struct x86_emulate_ctxt *ctxt, int rc; unsigned long val, change_mask; int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; - int cpl = kvm_x86_ops->get_cpl(ctxt->vcpu); + int cpl = ops->cpl(ctxt->vcpu); rc = emulate_pop(ctxt, ops, &val, len); if (rc != X86EMUL_CONTINUE) @@ -1306,10 +1576,10 @@ static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int rc; rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) return rc; - rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, seg); + rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); return rc; } @@ -1332,7 +1602,7 @@ static int emulate_popa(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - int rc = 0; + int rc = X86EMUL_CONTINUE; int reg = VCPU_REGS_RDI; while (reg >= VCPU_REGS_RAX) { @@ -1343,7 +1613,7 @@ static int emulate_popa(struct x86_emulate_ctxt *ctxt, } rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) break; --reg; } @@ -1354,12 +1624,8 @@ static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - int rc; - rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); - if (rc != 0) - return rc; - return 0; + return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); } static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) @@ -1395,7 +1661,6 @@ static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - int rc = 0; switch (c->modrm_reg) { case 0 ... 1: /* test */ @@ -1408,11 +1673,9 @@ static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, emulate_1op("neg", c->dst, ctxt->eflags); break; default: - DPRINTF("Cannot emulate %02x\n", c->b); - rc = X86EMUL_UNHANDLEABLE; - break; + return 0; } - return rc; + return 1; } static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, @@ -1442,20 +1705,14 @@ static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, emulate_push(ctxt); break; } - return 0; + return X86EMUL_CONTINUE; } static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, - struct x86_emulate_ops *ops, - unsigned long memop) + struct x86_emulate_ops *ops) { struct decode_cache *c = &ctxt->decode; - u64 old, new; - int rc; - - rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - return rc; + u64 old = c->dst.orig_val; if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { @@ -1463,17 +1720,13 @@ static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); ctxt->eflags &= ~EFLG_ZF; - } else { - new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | + c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) | (u32) c->regs[VCPU_REGS_RBX]; - rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - return rc; ctxt->eflags |= EFLG_ZF; } - return 0; + return X86EMUL_CONTINUE; } static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, @@ -1484,14 +1737,14 @@ static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, unsigned long cs; rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); - if (rc) + if (rc != X86EMUL_CONTINUE) return rc; if (c->op_bytes == 4) c->eip = (u32)c->eip; rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); - if (rc) + if (rc != X86EMUL_CONTINUE) return rc; - rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, VCPU_SREG_CS); + rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); return rc; } @@ -1544,7 +1797,7 @@ static inline int writeback(struct x86_emulate_ctxt *ctxt, default: break; } - return 0; + return X86EMUL_CONTINUE; } static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) @@ -1598,8 +1851,11 @@ emulate_syscall(struct x86_emulate_ctxt *ctxt) u64 msr_data; /* syscall is not available in real mode */ - if (ctxt->mode == X86EMUL_MODE_REAL || ctxt->mode == X86EMUL_MODE_VM86) - return X86EMUL_UNHANDLEABLE; + if (ctxt->mode == X86EMUL_MODE_REAL || + ctxt->mode == X86EMUL_MODE_VM86) { + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + return X86EMUL_PROPAGATE_FAULT; + } setup_syscalls_segments(ctxt, &cs, &ss); @@ -1649,14 +1905,16 @@ emulate_sysenter(struct x86_emulate_ctxt *ctxt) /* inject #GP if in real mode */ if (ctxt->mode == X86EMUL_MODE_REAL) { kvm_inject_gp(ctxt->vcpu, 0); - return X86EMUL_UNHANDLEABLE; + return X86EMUL_PROPAGATE_FAULT; } /* XXX sysenter/sysexit have not been tested in 64bit mode. * Therefore, we inject an #UD. */ - if (ctxt->mode == X86EMUL_MODE_PROT64) - return X86EMUL_UNHANDLEABLE; + if (ctxt->mode == X86EMUL_MODE_PROT64) { + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + return X86EMUL_PROPAGATE_FAULT; + } setup_syscalls_segments(ctxt, &cs, &ss); @@ -1711,7 +1969,7 @@ emulate_sysexit(struct x86_emulate_ctxt *ctxt) if (ctxt->mode == X86EMUL_MODE_REAL || ctxt->mode == X86EMUL_MODE_VM86) { kvm_inject_gp(ctxt->vcpu, 0); - return X86EMUL_UNHANDLEABLE; + return X86EMUL_PROPAGATE_FAULT; } setup_syscalls_segments(ctxt, &cs, &ss); @@ -1756,7 +2014,8 @@ emulate_sysexit(struct x86_emulate_ctxt *ctxt) return X86EMUL_CONTINUE; } -static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) +static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops) { int iopl; if (ctxt->mode == X86EMUL_MODE_REAL) @@ -1764,7 +2023,7 @@ static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) if (ctxt->mode == X86EMUL_MODE_VM86) return true; iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; - return kvm_x86_ops->get_cpl(ctxt->vcpu) > iopl; + return ops->cpl(ctxt->vcpu) > iopl; } static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, @@ -1801,22 +2060,419 @@ static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops, u16 port, u16 len) { - if (emulator_bad_iopl(ctxt)) + if (emulator_bad_iopl(ctxt, ops)) if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) return false; return true; } +static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + int seg) +{ + struct desc_struct desc; + if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu)) + return get_desc_base(&desc); + else + return ~0; +} + +static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + struct tss_segment_16 *tss) +{ + struct decode_cache *c = &ctxt->decode; + + tss->ip = c->eip; + tss->flag = ctxt->eflags; + tss->ax = c->regs[VCPU_REGS_RAX]; + tss->cx = c->regs[VCPU_REGS_RCX]; + tss->dx = c->regs[VCPU_REGS_RDX]; + tss->bx = c->regs[VCPU_REGS_RBX]; + tss->sp = c->regs[VCPU_REGS_RSP]; + tss->bp = c->regs[VCPU_REGS_RBP]; + tss->si = c->regs[VCPU_REGS_RSI]; + tss->di = c->regs[VCPU_REGS_RDI]; + + tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); + tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); + tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); + tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); + tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); +} + +static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + struct tss_segment_16 *tss) +{ + struct decode_cache *c = &ctxt->decode; + int ret; + + c->eip = tss->ip; + ctxt->eflags = tss->flag | 2; + c->regs[VCPU_REGS_RAX] = tss->ax; + c->regs[VCPU_REGS_RCX] = tss->cx; + c->regs[VCPU_REGS_RDX] = tss->dx; + c->regs[VCPU_REGS_RBX] = tss->bx; + c->regs[VCPU_REGS_RSP] = tss->sp; + c->regs[VCPU_REGS_RBP] = tss->bp; + c->regs[VCPU_REGS_RSI] = tss->si; + c->regs[VCPU_REGS_RDI] = tss->di; + + /* + * SDM says that segment selectors are loaded before segment + * descriptors + */ + ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); + ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); + ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); + ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); + ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); + + /* + * Now load segment descriptors. If fault happenes at this stage + * it is handled in a context of new task + */ + ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); + if (ret != X86EMUL_CONTINUE) + return ret; + + return X86EMUL_CONTINUE; +} + +static int task_switch_16(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 tss_selector, u16 old_tss_sel, + ulong old_tss_base, struct desc_struct *new_desc) +{ + struct tss_segment_16 tss_seg; + int ret; + u32 err, new_tss_base = get_desc_base(new_desc); + + ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); + return ret; + } + + save_state_to_tss16(ctxt, ops, &tss_seg); + + ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); + return ret; + } + + ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); + return ret; + } + + if (old_tss_sel != 0xffff) { + tss_seg.prev_task_link = old_tss_sel; + + ret = ops->write_std(new_tss_base, + &tss_seg.prev_task_link, + sizeof tss_seg.prev_task_link, + ctxt->vcpu, &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); + return ret; + } + } + + return load_state_from_tss16(ctxt, ops, &tss_seg); +} + +static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + struct tss_segment_32 *tss) +{ + struct decode_cache *c = &ctxt->decode; + + tss->cr3 = ops->get_cr(3, ctxt->vcpu); + tss->eip = c->eip; + tss->eflags = ctxt->eflags; + tss->eax = c->regs[VCPU_REGS_RAX]; + tss->ecx = c->regs[VCPU_REGS_RCX]; + tss->edx = c->regs[VCPU_REGS_RDX]; + tss->ebx = c->regs[VCPU_REGS_RBX]; + tss->esp = c->regs[VCPU_REGS_RSP]; + tss->ebp = c->regs[VCPU_REGS_RBP]; + tss->esi = c->regs[VCPU_REGS_RSI]; + tss->edi = c->regs[VCPU_REGS_RDI]; + + tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); + tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); + tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); + tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); + tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); + tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); + tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); +} + +static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + struct tss_segment_32 *tss) +{ + struct decode_cache *c = &ctxt->decode; + int ret; + + ops->set_cr(3, tss->cr3, ctxt->vcpu); + c->eip = tss->eip; + ctxt->eflags = tss->eflags | 2; + c->regs[VCPU_REGS_RAX] = tss->eax; + c->regs[VCPU_REGS_RCX] = tss->ecx; + c->regs[VCPU_REGS_RDX] = tss->edx; + c->regs[VCPU_REGS_RBX] = tss->ebx; + c->regs[VCPU_REGS_RSP] = tss->esp; + c->regs[VCPU_REGS_RBP] = tss->ebp; + c->regs[VCPU_REGS_RSI] = tss->esi; + c->regs[VCPU_REGS_RDI] = tss->edi; + + /* + * SDM says that segment selectors are loaded before segment + * descriptors + */ + ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); + ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); + ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); + ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); + ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); + ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); + ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); + + /* + * Now load segment descriptors. If fault happenes at this stage + * it is handled in a context of new task + */ + ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); + if (ret != X86EMUL_CONTINUE) + return ret; + + return X86EMUL_CONTINUE; +} + +static int task_switch_32(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 tss_selector, u16 old_tss_sel, + ulong old_tss_base, struct desc_struct *new_desc) +{ + struct tss_segment_32 tss_seg; + int ret; + u32 err, new_tss_base = get_desc_base(new_desc); + + ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); + return ret; + } + + save_state_to_tss32(ctxt, ops, &tss_seg); + + ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); + return ret; + } + + ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, + &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); + return ret; + } + + if (old_tss_sel != 0xffff) { + tss_seg.prev_task_link = old_tss_sel; + + ret = ops->write_std(new_tss_base, + &tss_seg.prev_task_link, + sizeof tss_seg.prev_task_link, + ctxt->vcpu, &err); + if (ret == X86EMUL_PROPAGATE_FAULT) { + /* FIXME: need to provide precise fault address */ + kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); + return ret; + } + } + + return load_state_from_tss32(ctxt, ops, &tss_seg); +} + +static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 tss_selector, int reason, + bool has_error_code, u32 error_code) +{ + struct desc_struct curr_tss_desc, next_tss_desc; + int ret; + u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); + ulong old_tss_base = + get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR); + u32 desc_limit; + + /* FIXME: old_tss_base == ~0 ? */ + + ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); + if (ret != X86EMUL_CONTINUE) + return ret; + ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); + if (ret != X86EMUL_CONTINUE) + return ret; + + /* FIXME: check that next_tss_desc is tss */ + + if (reason != TASK_SWITCH_IRET) { + if ((tss_selector & 3) > next_tss_desc.dpl || + ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { + kvm_inject_gp(ctxt->vcpu, 0); + return X86EMUL_PROPAGATE_FAULT; + } + } + + desc_limit = desc_limit_scaled(&next_tss_desc); + if (!next_tss_desc.p || + ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || + desc_limit < 0x2b)) { + kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR, + tss_selector & 0xfffc); + return X86EMUL_PROPAGATE_FAULT; + } + + if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { + curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ + write_segment_descriptor(ctxt, ops, old_tss_sel, + &curr_tss_desc); + } + + if (reason == TASK_SWITCH_IRET) + ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; + + /* set back link to prev task only if NT bit is set in eflags + note that old_tss_sel is not used afetr this point */ + if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) + old_tss_sel = 0xffff; + + if (next_tss_desc.type & 8) + ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, + old_tss_base, &next_tss_desc); + else + ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, + old_tss_base, &next_tss_desc); + if (ret != X86EMUL_CONTINUE) + return ret; + + if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) + ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; + + if (reason != TASK_SWITCH_IRET) { + next_tss_desc.type |= (1 << 1); /* set busy flag */ + write_segment_descriptor(ctxt, ops, tss_selector, + &next_tss_desc); + } + + ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); + ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); + ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); + + if (has_error_code) { + struct decode_cache *c = &ctxt->decode; + + c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; + c->lock_prefix = 0; + c->src.val = (unsigned long) error_code; + emulate_push(ctxt); + } + + return ret; +} + +int emulator_task_switch(struct x86_emulate_ctxt *ctxt, + struct x86_emulate_ops *ops, + u16 tss_selector, int reason, + bool has_error_code, u32 error_code) +{ + struct decode_cache *c = &ctxt->decode; + int rc; + + memset(c, 0, sizeof(struct decode_cache)); + c->eip = ctxt->eip; + memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); + c->dst.type = OP_NONE; + + rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, + has_error_code, error_code); + + if (rc == X86EMUL_CONTINUE) { + memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); + kvm_rip_write(ctxt->vcpu, c->eip); + rc = writeback(ctxt, ops); + } + + return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; +} + +static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, + int reg, struct operand *op) +{ + struct decode_cache *c = &ctxt->decode; + int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; + + register_address_increment(c, &c->regs[reg], df * op->bytes); + op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]); +} + int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) { - unsigned long memop = 0; u64 msr_data; - unsigned long saved_eip = 0; struct decode_cache *c = &ctxt->decode; - unsigned int port; - int io_dir_in; - int rc = 0; + int rc = X86EMUL_CONTINUE; + int saved_dst_type = c->dst.type; ctxt->interruptibility = 0; @@ -1826,26 +2482,30 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) */ memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); - saved_eip = c->eip; + + if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; + } /* LOCK prefix is allowed only with some instructions */ - if (c->lock_prefix && !(c->d & Lock)) { + if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { kvm_queue_exception(ctxt->vcpu, UD_VECTOR); goto done; } /* Privileged instruction can be executed only in CPL=0 */ - if ((c->d & Priv) && kvm_x86_ops->get_cpl(ctxt->vcpu)) { + if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { kvm_inject_gp(ctxt->vcpu, 0); goto done; } - if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) - memop = c->modrm_ea; - if (c->rep_prefix && (c->d & String)) { + ctxt->restart = true; /* All REP prefixes have the same first termination condition */ - if (c->regs[VCPU_REGS_RCX] == 0) { + if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { + string_done: + ctxt->restart = false; kvm_rip_write(ctxt->vcpu, c->eip); goto done; } @@ -1857,25 +2517,18 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) * - if REPNE/REPNZ and ZF = 1 then done */ if ((c->b == 0xa6) || (c->b == 0xa7) || - (c->b == 0xae) || (c->b == 0xaf)) { + (c->b == 0xae) || (c->b == 0xaf)) { if ((c->rep_prefix == REPE_PREFIX) && - ((ctxt->eflags & EFLG_ZF) == 0)) { - kvm_rip_write(ctxt->vcpu, c->eip); - goto done; - } + ((ctxt->eflags & EFLG_ZF) == 0)) + goto string_done; if ((c->rep_prefix == REPNE_PREFIX) && - ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) { - kvm_rip_write(ctxt->vcpu, c->eip); - goto done; - } + ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) + goto string_done; } - c->regs[VCPU_REGS_RCX]--; - c->eip = kvm_rip_read(ctxt->vcpu); + c->eip = ctxt->eip; } if (c->src.type == OP_MEM) { - c->src.ptr = (unsigned long *)memop; - c->src.val = 0; rc = ops->read_emulated((unsigned long)c->src.ptr, &c->src.val, c->src.bytes, @@ -1885,29 +2538,25 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) c->src.orig_val = c->src.val; } + if (c->src2.type == OP_MEM) { + rc = ops->read_emulated((unsigned long)c->src2.ptr, + &c->src2.val, + c->src2.bytes, + ctxt->vcpu); + if (rc != X86EMUL_CONTINUE) + goto done; + } + if ((c->d & DstMask) == ImplicitOps) goto special_insn; - if (c->dst.type == OP_MEM) { - c->dst.ptr = (unsigned long *)memop; - c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->dst.val = 0; - if (c->d & BitOp) { - unsigned long mask = ~(c->dst.bytes * 8 - 1); - - c->dst.ptr = (void *)c->dst.ptr + - (c->src.val & mask) / 8; - } - if (!(c->d & Mov)) { - /* optimisation - avoid slow emulated read */ - rc = ops->read_emulated((unsigned long)c->dst.ptr, - &c->dst.val, - c->dst.bytes, - ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - goto done; - } + if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { + /* optimisation - avoid slow emulated read if Mov */ + rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val, + c->dst.bytes, ctxt->vcpu); + if (rc != X86EMUL_CONTINUE) + goto done; } c->dst.orig_val = c->dst.val; @@ -1926,7 +2575,7 @@ special_insn: break; case 0x07: /* pop es */ rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x08 ... 0x0d: @@ -1945,7 +2594,7 @@ special_insn: break; case 0x17: /* pop ss */ rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x18 ... 0x1d: @@ -1957,7 +2606,7 @@ special_insn: break; case 0x1f: /* pop ds */ rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x20 ... 0x25: @@ -1988,7 +2637,7 @@ special_insn: case 0x58 ... 0x5f: /* pop reg */ pop_instruction: rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x60: /* pusha */ @@ -1996,7 +2645,7 @@ special_insn: break; case 0x61: /* popa */ rc = emulate_popa(ctxt, ops); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x63: /* movsxd */ @@ -2010,47 +2659,29 @@ special_insn: break; case 0x6c: /* insb */ case 0x6d: /* insw/insd */ + c->dst.bytes = min(c->dst.bytes, 4u); if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], - (c->d & ByteOp) ? 1 : c->op_bytes)) { + c->dst.bytes)) { kvm_inject_gp(ctxt->vcpu, 0); goto done; } - if (kvm_emulate_pio_string(ctxt->vcpu, - 1, - (c->d & ByteOp) ? 1 : c->op_bytes, - c->rep_prefix ? - address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, - (ctxt->eflags & EFLG_DF), - register_address(c, es_base(ctxt), - c->regs[VCPU_REGS_RDI]), - c->rep_prefix, - c->regs[VCPU_REGS_RDX]) == 0) { - c->eip = saved_eip; - return -1; - } - return 0; + if (!pio_in_emulated(ctxt, ops, c->dst.bytes, + c->regs[VCPU_REGS_RDX], &c->dst.val)) + goto done; /* IO is needed, skip writeback */ + break; case 0x6e: /* outsb */ case 0x6f: /* outsw/outsd */ + c->src.bytes = min(c->src.bytes, 4u); if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], - (c->d & ByteOp) ? 1 : c->op_bytes)) { + c->src.bytes)) { kvm_inject_gp(ctxt->vcpu, 0); goto done; } - if (kvm_emulate_pio_string(ctxt->vcpu, - 0, - (c->d & ByteOp) ? 1 : c->op_bytes, - c->rep_prefix ? - address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, - (ctxt->eflags & EFLG_DF), - register_address(c, - seg_override_base(ctxt, c), - c->regs[VCPU_REGS_RSI]), - c->rep_prefix, - c->regs[VCPU_REGS_RDX]) == 0) { - c->eip = saved_eip; - return -1; - } - return 0; + ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], + &c->src.val, 1, ctxt->vcpu); + + c->dst.type = OP_NONE; /* nothing to writeback */ + break; case 0x70 ... 0x7f: /* jcc (short) */ if (test_cc(c->b, ctxt->eflags)) jmp_rel(c, c->src.val); @@ -2107,12 +2738,11 @@ special_insn: case 0x8c: { /* mov r/m, sreg */ struct kvm_segment segreg; - if (c->modrm_reg <= 5) + if (c->modrm_reg <= VCPU_SREG_GS) kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg); else { - printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n", - c->modrm); - goto cannot_emulate; + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; } c->dst.val = segreg.selector; break; @@ -2132,16 +2762,16 @@ special_insn: } if (c->modrm_reg == VCPU_SREG_SS) - toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS); + toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS); - rc = kvm_load_segment_descriptor(ctxt->vcpu, sel, c->modrm_reg); + rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); c->dst.type = OP_NONE; /* Disable writeback. */ break; } case 0x8f: /* pop (sole member of Grp1a) */ rc = emulate_grp1a(ctxt, ops); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0x90: /* nop / xchg r8,rax */ @@ -2175,89 +2805,16 @@ special_insn: c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; break; case 0xa4 ... 0xa5: /* movs */ - c->dst.type = OP_MEM; - c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->dst.ptr = (unsigned long *)register_address(c, - es_base(ctxt), - c->regs[VCPU_REGS_RDI]); - rc = ops->read_emulated(register_address(c, - seg_override_base(ctxt, c), - c->regs[VCPU_REGS_RSI]), - &c->dst.val, - c->dst.bytes, ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - goto done; - register_address_increment(c, &c->regs[VCPU_REGS_RSI], - (ctxt->eflags & EFLG_DF) ? -c->dst.bytes - : c->dst.bytes); - register_address_increment(c, &c->regs[VCPU_REGS_RDI], - (ctxt->eflags & EFLG_DF) ? -c->dst.bytes - : c->dst.bytes); - break; + goto mov; case 0xa6 ... 0xa7: /* cmps */ - c->src.type = OP_NONE; /* Disable writeback. */ - c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->src.ptr = (unsigned long *)register_address(c, - seg_override_base(ctxt, c), - c->regs[VCPU_REGS_RSI]); - rc = ops->read_emulated((unsigned long)c->src.ptr, - &c->src.val, - c->src.bytes, - ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - goto done; - c->dst.type = OP_NONE; /* Disable writeback. */ - c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->dst.ptr = (unsigned long *)register_address(c, - es_base(ctxt), - c->regs[VCPU_REGS_RDI]); - rc = ops->read_emulated((unsigned long)c->dst.ptr, - &c->dst.val, - c->dst.bytes, - ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - goto done; - DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); - - emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); - - register_address_increment(c, &c->regs[VCPU_REGS_RSI], - (ctxt->eflags & EFLG_DF) ? -c->src.bytes - : c->src.bytes); - register_address_increment(c, &c->regs[VCPU_REGS_RDI], - (ctxt->eflags & EFLG_DF) ? -c->dst.bytes - : c->dst.bytes); - - break; + goto cmp; case 0xaa ... 0xab: /* stos */ - c->dst.type = OP_MEM; - c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->dst.ptr = (unsigned long *)register_address(c, - es_base(ctxt), - c->regs[VCPU_REGS_RDI]); c->dst.val = c->regs[VCPU_REGS_RAX]; - register_address_increment(c, &c->regs[VCPU_REGS_RDI], - (ctxt->eflags & EFLG_DF) ? -c->dst.bytes - : c->dst.bytes); break; case 0xac ... 0xad: /* lods */ - c->dst.type = OP_REG; - c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; - c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; - rc = ops->read_emulated(register_address(c, - seg_override_base(ctxt, c), - c->regs[VCPU_REGS_RSI]), - &c->dst.val, - c->dst.bytes, - ctxt->vcpu); - if (rc != X86EMUL_CONTINUE) - goto done; - register_address_increment(c, &c->regs[VCPU_REGS_RSI], - (ctxt->eflags & EFLG_DF) ? -c->dst.bytes - : c->dst.bytes); - break; + goto mov; case 0xae ... 0xaf: /* scas */ DPRINTF("Urk! I don't handle SCAS.\n"); goto cannot_emulate; @@ -2277,7 +2834,7 @@ special_insn: break; case 0xcb: /* ret far */ rc = emulate_ret_far(ctxt, ops); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0xd0 ... 0xd1: /* Grp2 */ @@ -2290,14 +2847,10 @@ special_insn: break; case 0xe4: /* inb */ case 0xe5: /* in */ - port = c->src.val; - io_dir_in = 1; - goto do_io; + goto do_io_in; case 0xe6: /* outb */ case 0xe7: /* out */ - port = c->src.val; - io_dir_in = 0; - goto do_io; + goto do_io_out; case 0xe8: /* call (near) */ { long int rel = c->src.val; c->src.val = (unsigned long) c->eip; @@ -2308,8 +2861,9 @@ special_insn: case 0xe9: /* jmp rel */ goto jmp; case 0xea: /* jmp far */ - if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, - VCPU_SREG_CS)) + jump_far: + if (load_segment_descriptor(ctxt, ops, c->src2.val, + VCPU_SREG_CS)) goto done; c->eip = c->src.val; @@ -2321,25 +2875,29 @@ special_insn: break; case 0xec: /* in al,dx */ case 0xed: /* in (e/r)ax,dx */ - port = c->regs[VCPU_REGS_RDX]; - io_dir_in = 1; - goto do_io; + c->src.val = c->regs[VCPU_REGS_RDX]; + do_io_in: + c->dst.bytes = min(c->dst.bytes, 4u); + if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { + kvm_inject_gp(ctxt->vcpu, 0); + goto done; + } + if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, + &c->dst.val)) + goto done; /* IO is needed */ + break; case 0xee: /* out al,dx */ case 0xef: /* out (e/r)ax,dx */ - port = c->regs[VCPU_REGS_RDX]; - io_dir_in = 0; - do_io: - if (!emulator_io_permited(ctxt, ops, port, - (c->d & ByteOp) ? 1 : c->op_bytes)) { + c->src.val = c->regs[VCPU_REGS_RDX]; + do_io_out: + c->dst.bytes = min(c->dst.bytes, 4u); + if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { kvm_inject_gp(ctxt->vcpu, 0); goto done; } - if (kvm_emulate_pio(ctxt->vcpu, io_dir_in, - (c->d & ByteOp) ? 1 : c->op_bytes, - port) != 0) { - c->eip = saved_eip; - goto cannot_emulate; - } + ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, + ctxt->vcpu); + c->dst.type = OP_NONE; /* Disable writeback. */ break; case 0xf4: /* hlt */ ctxt->vcpu->arch.halt_request = 1; @@ -2350,16 +2908,15 @@ special_insn: c->dst.type = OP_NONE; /* Disable writeback. */ break; case 0xf6 ... 0xf7: /* Grp3 */ - rc = emulate_grp3(ctxt, ops); - if (rc != 0) - goto done; + if (!emulate_grp3(ctxt, ops)) + goto cannot_emulate; break; case 0xf8: /* clc */ ctxt->eflags &= ~EFLG_CF; c->dst.type = OP_NONE; /* Disable writeback. */ break; case 0xfa: /* cli */ - if (emulator_bad_iopl(ctxt)) + if (emulator_bad_iopl(ctxt, ops)) kvm_inject_gp(ctxt->vcpu, 0); else { ctxt->eflags &= ~X86_EFLAGS_IF; @@ -2367,10 +2924,10 @@ special_insn: } break; case 0xfb: /* sti */ - if (emulator_bad_iopl(ctxt)) + if (emulator_bad_iopl(ctxt, ops)) kvm_inject_gp(ctxt->vcpu, 0); else { - toggle_interruptibility(ctxt, X86_SHADOW_INT_STI); + toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI); ctxt->eflags |= X86_EFLAGS_IF; c->dst.type = OP_NONE; /* Disable writeback. */ } @@ -2383,28 +2940,55 @@ special_insn: ctxt->eflags |= EFLG_DF; c->dst.type = OP_NONE; /* Disable writeback. */ break; - case 0xfe ... 0xff: /* Grp4/Grp5 */ + case 0xfe: /* Grp4 */ + grp45: rc = emulate_grp45(ctxt, ops); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; + case 0xff: /* Grp5 */ + if (c->modrm_reg == 5) + goto jump_far; + goto grp45; } writeback: rc = writeback(ctxt, ops); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; + /* + * restore dst type in case the decoding will be reused + * (happens for string instruction ) + */ + c->dst.type = saved_dst_type; + + if ((c->d & SrcMask) == SrcSI) + string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI, + &c->src); + + if ((c->d & DstMask) == DstDI) + string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst); + + if (c->rep_prefix && (c->d & String)) { + struct read_cache *rc = &ctxt->decode.io_read; + register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); + /* + * Re-enter guest when pio read ahead buffer is empty or, + * if it is not used, after each 1024 iteration. + */ + if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || + (rc->end != 0 && rc->end == rc->pos)) + ctxt->restart = false; + } + /* Commit shadow register state. */ memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); kvm_rip_write(ctxt->vcpu, c->eip); + ops->set_rflags(ctxt->vcpu, ctxt->eflags); done: - if (rc == X86EMUL_UNHANDLEABLE) { - c->eip = saved_eip; - return -1; - } - return 0; + return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; twobyte_insn: switch (c->b) { @@ -2418,18 +3002,18 @@ twobyte_insn: goto cannot_emulate; rc = kvm_fix_hypercall(ctxt->vcpu); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; /* Let the processor re-execute the fixed hypercall */ - c->eip = kvm_rip_read(ctxt->vcpu); + c->eip = ctxt->eip; /* Disable writeback. */ c->dst.type = OP_NONE; break; case 2: /* lgdt */ rc = read_descriptor(ctxt, ops, c->src.ptr, &size, &address, c->op_bytes); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; realmode_lgdt(ctxt->vcpu, size, address); /* Disable writeback. */ @@ -2440,7 +3024,7 @@ twobyte_insn: switch (c->modrm_rm) { case 1: rc = kvm_fix_hypercall(ctxt->vcpu); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; break; default: @@ -2450,7 +3034,7 @@ twobyte_insn: rc = read_descriptor(ctxt, ops, c->src.ptr, &size, &address, c->op_bytes); - if (rc) + if (rc != X86EMUL_CONTINUE) goto done; realmode_lidt(ctxt->vcpu, size, address); } @@ -2459,15 +3043,18 @@ twobyte_insn: break; case 4: /* smsw */ c->dst.bytes = 2; - c->dst.val = realmode_get_cr(ctxt->vcpu, 0); + c->dst.val = ops->get_cr(0, ctxt->vcpu); break; case 6: /* lmsw */ - realmode_lmsw(ctxt->vcpu, (u16)c->src.val, - &ctxt->eflags); + ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) | + (c->src.val & 0x0f), ctxt->vcpu); c->dst.type = OP_NONE; break; + case 5: /* not defined */ + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; case 7: /* invlpg*/ - emulate_invlpg(ctxt->vcpu, memop); + emulate_invlpg(ctxt->vcpu, c->modrm_ea); /* Disable writeback. */ c->dst.type = OP_NONE; break; @@ -2493,54 +3080,54 @@ twobyte_insn: c->dst.type = OP_NONE; break; case 0x20: /* mov cr, reg */ - if (c->modrm_mod != 3) - goto cannot_emulate; - c->regs[c->modrm_rm] = - realmode_get_cr(ctxt->vcpu, c->modrm_reg); + switch (c->modrm_reg) { + case 1: + case 5 ... 7: + case 9 ... 15: + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; + } + c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu); c->dst.type = OP_NONE; /* no writeback */ break; case 0x21: /* mov from dr to reg */ - if (c->modrm_mod != 3) - goto cannot_emulate; - rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); - if (rc) - goto cannot_emulate; + if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && + (c->modrm_reg == 4 || c->modrm_reg == 5)) { + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; + } + emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); c->dst.type = OP_NONE; /* no writeback */ break; case 0x22: /* mov reg, cr */ - if (c->modrm_mod != 3) - goto cannot_emulate; - realmode_set_cr(ctxt->vcpu, - c->modrm_reg, c->modrm_val, &ctxt->eflags); + ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu); c->dst.type = OP_NONE; break; case 0x23: /* mov from reg to dr */ - if (c->modrm_mod != 3) - goto cannot_emulate; - rc = emulator_set_dr(ctxt, c->modrm_reg, - c->regs[c->modrm_rm]); - if (rc) - goto cannot_emulate; + if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && + (c->modrm_reg == 4 || c->modrm_reg == 5)) { + kvm_queue_exception(ctxt->vcpu, UD_VECTOR); + goto done; + } + emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]); c->dst.type = OP_NONE; /* no writeback */ break; case 0x30: /* wrmsr */ msr_data = (u32)c->regs[VCPU_REGS_RAX] | ((u64)c->regs[VCPU_REGS_RDX] << 32); - rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); - if (rc) { + if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { kvm_inject_gp(ctxt->vcpu, 0); - c->eip = kvm_rip_read(ctxt->vcpu); + goto done; } rc = X86EMUL_CONTINUE; c->dst.type = OP_NONE; break; case 0x32: /* rdmsr */ - rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); - if (rc) { + if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { kvm_inject_gp(ctxt->vcpu, 0); - c->eip = kvm_rip_read(ctxt->vcpu); + goto done; } else { c->regs[VCPU_REGS_RAX] = (u32)msr_data; c->regs[VCPU_REGS_RDX] = msr_data >> 32; @@ -2577,7 +3164,7 @@ twobyte_insn: break; case 0xa1: /* pop fs */ rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0xa3: @@ -2596,7 +3183,7 @@ twobyte_insn: break; case 0xa9: /* pop gs */ rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); - if (rc != 0) + if (rc != X86EMUL_CONTINUE) goto done; break; case 0xab: @@ -2668,16 +3255,14 @@ twobyte_insn: (u64) c->src.val; break; case 0xc7: /* Grp9 (cmpxchg8b) */ - rc = emulate_grp9(ctxt, ops, memop); - if (rc != 0) + rc = emulate_grp9(ctxt, ops); + if (rc != X86EMUL_CONTINUE) goto done; - c->dst.type = OP_NONE; break; } goto writeback; cannot_emulate: DPRINTF("Cannot emulate %02x\n", c->b); - c->eip = saved_eip; return -1; } diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c index a790fa128a9f..93825ff3338f 100644 --- a/arch/x86/kvm/i8259.c +++ b/arch/x86/kvm/i8259.c @@ -33,6 +33,29 @@ #include <linux/kvm_host.h> #include "trace.h" +static void pic_lock(struct kvm_pic *s) + __acquires(&s->lock) +{ + raw_spin_lock(&s->lock); +} + +static void pic_unlock(struct kvm_pic *s) + __releases(&s->lock) +{ + bool wakeup = s->wakeup_needed; + struct kvm_vcpu *vcpu; + + s->wakeup_needed = false; + + raw_spin_unlock(&s->lock); + + if (wakeup) { + vcpu = s->kvm->bsp_vcpu; + if (vcpu) + kvm_vcpu_kick(vcpu); + } +} + static void pic_clear_isr(struct kvm_kpic_state *s, int irq) { s->isr &= ~(1 << irq); @@ -45,19 +68,19 @@ static void pic_clear_isr(struct kvm_kpic_state *s, int irq) * Other interrupt may be delivered to PIC while lock is dropped but * it should be safe since PIC state is already updated at this stage. */ - raw_spin_unlock(&s->pics_state->lock); + pic_unlock(s->pics_state); kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq); - raw_spin_lock(&s->pics_state->lock); + pic_lock(s->pics_state); } void kvm_pic_clear_isr_ack(struct kvm *kvm) { struct kvm_pic *s = pic_irqchip(kvm); - raw_spin_lock(&s->lock); + pic_lock(s); s->pics[0].isr_ack = 0xff; s->pics[1].isr_ack = 0xff; - raw_spin_unlock(&s->lock); + pic_unlock(s); } /* @@ -158,9 +181,9 @@ static void pic_update_irq(struct kvm_pic *s) void kvm_pic_update_irq(struct kvm_pic *s) { - raw_spin_lock(&s->lock); + pic_lock(s); pic_update_irq(s); - raw_spin_unlock(&s->lock); + pic_unlock(s); } int kvm_pic_set_irq(void *opaque, int irq, int level) @@ -168,14 +191,14 @@ int kvm_pic_set_irq(void *opaque, int irq, int level) struct kvm_pic *s = opaque; int ret = -1; - raw_spin_lock(&s->lock); + pic_lock(s); if (irq >= 0 && irq < PIC_NUM_PINS) { ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); pic_update_irq(s); trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, s->pics[irq >> 3].imr, ret == 0); } - raw_spin_unlock(&s->lock); + pic_unlock(s); return ret; } @@ -205,7 +228,7 @@ int kvm_pic_read_irq(struct kvm *kvm) int irq, irq2, intno; struct kvm_pic *s = pic_irqchip(kvm); - raw_spin_lock(&s->lock); + pic_lock(s); irq = pic_get_irq(&s->pics[0]); if (irq >= 0) { pic_intack(&s->pics[0], irq); @@ -230,7 +253,7 @@ int kvm_pic_read_irq(struct kvm *kvm) intno = s->pics[0].irq_base + irq; } pic_update_irq(s); - raw_spin_unlock(&s->lock); + pic_unlock(s); return intno; } @@ -444,7 +467,7 @@ static int picdev_write(struct kvm_io_device *this, printk(KERN_ERR "PIC: non byte write\n"); return 0; } - raw_spin_lock(&s->lock); + pic_lock(s); switch (addr) { case 0x20: case 0x21: @@ -457,7 +480,7 @@ static int picdev_write(struct kvm_io_device *this, elcr_ioport_write(&s->pics[addr & 1], addr, data); break; } - raw_spin_unlock(&s->lock); + pic_unlock(s); return 0; } @@ -474,7 +497,7 @@ static int picdev_read(struct kvm_io_device *this, printk(KERN_ERR "PIC: non byte read\n"); return 0; } - raw_spin_lock(&s->lock); + pic_lock(s); switch (addr) { case 0x20: case 0x21: @@ -488,7 +511,7 @@ static int picdev_read(struct kvm_io_device *this, break; } *(unsigned char *)val = data; - raw_spin_unlock(&s->lock); + pic_unlock(s); return 0; } @@ -505,7 +528,7 @@ static void pic_irq_request(void *opaque, int level) s->output = level; if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { s->pics[0].isr_ack &= ~(1 << irq); - kvm_vcpu_kick(vcpu); + s->wakeup_needed = true; } } diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h index 34b15915754d..cd1f362f413d 100644 --- a/arch/x86/kvm/irq.h +++ b/arch/x86/kvm/irq.h @@ -63,6 +63,7 @@ struct kvm_kpic_state { struct kvm_pic { raw_spinlock_t lock; + bool wakeup_needed; unsigned pending_acks; struct kvm *kvm; struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */ diff --git a/arch/x86/kvm/kvm_timer.h b/arch/x86/kvm/kvm_timer.h index 55c7524dda54..64bc6ea78d90 100644 --- a/arch/x86/kvm/kvm_timer.h +++ b/arch/x86/kvm/kvm_timer.h @@ -10,9 +10,7 @@ struct kvm_timer { }; struct kvm_timer_ops { - bool (*is_periodic)(struct kvm_timer *); + bool (*is_periodic)(struct kvm_timer *); }; - enum hrtimer_restart kvm_timer_fn(struct hrtimer *data); - diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 19a8906bcaa2..a6f695d76928 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -148,7 +148,6 @@ module_param(oos_shadow, bool, 0644); #include <trace/events/kvm.h> -#undef TRACE_INCLUDE_FILE #define CREATE_TRACE_POINTS #include "mmutrace.h" @@ -174,12 +173,7 @@ struct kvm_shadow_walk_iterator { shadow_walk_okay(&(_walker)); \ shadow_walk_next(&(_walker))) - -struct kvm_unsync_walk { - int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk); -}; - -typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp); +typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp); static struct kmem_cache *pte_chain_cache; static struct kmem_cache *rmap_desc_cache; @@ -223,7 +217,7 @@ void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, } EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); -static int is_write_protection(struct kvm_vcpu *vcpu) +static bool is_write_protection(struct kvm_vcpu *vcpu) { return kvm_read_cr0_bits(vcpu, X86_CR0_WP); } @@ -327,7 +321,6 @@ static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, page = alloc_page(GFP_KERNEL); if (!page) return -ENOMEM; - set_page_private(page, 0); cache->objects[cache->nobjs++] = page_address(page); } return 0; @@ -438,9 +431,9 @@ static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) int i; gfn = unalias_gfn(kvm, gfn); + slot = gfn_to_memslot_unaliased(kvm, gfn); for (i = PT_DIRECTORY_LEVEL; i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { - slot = gfn_to_memslot_unaliased(kvm, gfn); write_count = slot_largepage_idx(gfn, slot, i); *write_count -= 1; WARN_ON(*write_count < 0); @@ -654,7 +647,6 @@ static void rmap_remove(struct kvm *kvm, u64 *spte) static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) { struct kvm_rmap_desc *desc; - struct kvm_rmap_desc *prev_desc; u64 *prev_spte; int i; @@ -666,7 +658,6 @@ static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) return NULL; } desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); - prev_desc = NULL; prev_spte = NULL; while (desc) { for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { @@ -794,7 +785,7 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, int retval = 0; struct kvm_memslots *slots; - slots = rcu_dereference(kvm->memslots); + slots = kvm_memslots(kvm); for (i = 0; i < slots->nmemslots; i++) { struct kvm_memory_slot *memslot = &slots->memslots[i]; @@ -925,7 +916,6 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); set_page_private(virt_to_page(sp->spt), (unsigned long)sp); list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); - INIT_LIST_HEAD(&sp->oos_link); bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); sp->multimapped = 0; sp->parent_pte = parent_pte; @@ -1009,8 +999,7 @@ static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, } -static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, - mmu_parent_walk_fn fn) +static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) { struct kvm_pte_chain *pte_chain; struct hlist_node *node; @@ -1019,8 +1008,8 @@ static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, if (!sp->multimapped && sp->parent_pte) { parent_sp = page_header(__pa(sp->parent_pte)); - fn(vcpu, parent_sp); - mmu_parent_walk(vcpu, parent_sp, fn); + fn(parent_sp); + mmu_parent_walk(parent_sp, fn); return; } hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) @@ -1028,8 +1017,8 @@ static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, if (!pte_chain->parent_ptes[i]) break; parent_sp = page_header(__pa(pte_chain->parent_ptes[i])); - fn(vcpu, parent_sp); - mmu_parent_walk(vcpu, parent_sp, fn); + fn(parent_sp); + mmu_parent_walk(parent_sp, fn); } } @@ -1066,16 +1055,15 @@ static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp) } } -static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) +static int unsync_walk_fn(struct kvm_mmu_page *sp) { kvm_mmu_update_parents_unsync(sp); return 1; } -static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu, - struct kvm_mmu_page *sp) +static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) { - mmu_parent_walk(vcpu, sp, unsync_walk_fn); + mmu_parent_walk(sp, unsync_walk_fn); kvm_mmu_update_parents_unsync(sp); } @@ -1201,6 +1189,7 @@ static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn) static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) { WARN_ON(!sp->unsync); + trace_kvm_mmu_sync_page(sp); sp->unsync = 0; --kvm->stat.mmu_unsync; } @@ -1209,12 +1198,11 @@ static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp); static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) { - if (sp->role.glevels != vcpu->arch.mmu.root_level) { + if (sp->role.cr4_pae != !!is_pae(vcpu)) { kvm_mmu_zap_page(vcpu->kvm, sp); return 1; } - trace_kvm_mmu_sync_page(sp); if (rmap_write_protect(vcpu->kvm, sp->gfn)) kvm_flush_remote_tlbs(vcpu->kvm); kvm_unlink_unsync_page(vcpu->kvm, sp); @@ -1331,6 +1319,8 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, role = vcpu->arch.mmu.base_role; role.level = level; role.direct = direct; + if (role.direct) + role.cr4_pae = 0; role.access = access; if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); @@ -1351,7 +1341,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, mmu_page_add_parent_pte(vcpu, sp, parent_pte); if (sp->unsync_children) { set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests); - kvm_mmu_mark_parents_unsync(vcpu, sp); + kvm_mmu_mark_parents_unsync(sp); } trace_kvm_mmu_get_page(sp, false); return sp; @@ -1573,13 +1563,14 @@ static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) r = 0; index = kvm_page_table_hashfn(gfn); bucket = &kvm->arch.mmu_page_hash[index]; +restart: hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) if (sp->gfn == gfn && !sp->role.direct) { pgprintk("%s: gfn %lx role %x\n", __func__, gfn, sp->role.word); r = 1; if (kvm_mmu_zap_page(kvm, sp)) - n = bucket->first; + goto restart; } return r; } @@ -1593,13 +1584,14 @@ static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) index = kvm_page_table_hashfn(gfn); bucket = &kvm->arch.mmu_page_hash[index]; +restart: hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) { if (sp->gfn == gfn && !sp->role.direct && !sp->role.invalid) { pgprintk("%s: zap %lx %x\n", __func__, gfn, sp->role.word); if (kvm_mmu_zap_page(kvm, sp)) - nn = bucket->first; + goto restart; } } } @@ -1626,20 +1618,6 @@ static void mmu_convert_notrap(struct kvm_mmu_page *sp) } } -struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva) -{ - struct page *page; - - gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); - - if (gpa == UNMAPPED_GVA) - return NULL; - - page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); - - return page; -} - /* * The function is based on mtrr_type_lookup() in * arch/x86/kernel/cpu/mtrr/generic.c @@ -1752,7 +1730,6 @@ static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) struct kvm_mmu_page *s; struct hlist_node *node, *n; - trace_kvm_mmu_unsync_page(sp); index = kvm_page_table_hashfn(sp->gfn); bucket = &vcpu->kvm->arch.mmu_page_hash[index]; /* don't unsync if pagetable is shadowed with multiple roles */ @@ -1762,10 +1739,11 @@ static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) if (s->role.word != sp->role.word) return 1; } + trace_kvm_mmu_unsync_page(sp); ++vcpu->kvm->stat.mmu_unsync; sp->unsync = 1; - kvm_mmu_mark_parents_unsync(vcpu, sp); + kvm_mmu_mark_parents_unsync(sp); mmu_convert_notrap(sp); return 0; @@ -1837,6 +1815,9 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, spte |= PT_WRITABLE_MASK; + if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK)) + spte &= ~PT_USER_MASK; + /* * Optimization: for pte sync, if spte was writable the hash * lookup is unnecessary (and expensive). Write protection @@ -1892,6 +1873,8 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, child = page_header(pte & PT64_BASE_ADDR_MASK); mmu_page_remove_parent_pte(child, sptep); + __set_spte(sptep, shadow_trap_nonpresent_pte); + kvm_flush_remote_tlbs(vcpu->kvm); } else if (pfn != spte_to_pfn(*sptep)) { pgprintk("hfn old %lx new %lx\n", spte_to_pfn(*sptep), pfn); @@ -2081,21 +2064,23 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu) hpa_t root = vcpu->arch.mmu.root_hpa; ASSERT(!VALID_PAGE(root)); - if (tdp_enabled) - direct = 1; if (mmu_check_root(vcpu, root_gfn)) return 1; + if (tdp_enabled) { + direct = 1; + root_gfn = 0; + } + spin_lock(&vcpu->kvm->mmu_lock); sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, direct, ACC_ALL, NULL); root = __pa(sp->spt); ++sp->root_count; + spin_unlock(&vcpu->kvm->mmu_lock); vcpu->arch.mmu.root_hpa = root; return 0; } direct = !is_paging(vcpu); - if (tdp_enabled) - direct = 1; for (i = 0; i < 4; ++i) { hpa_t root = vcpu->arch.mmu.pae_root[i]; @@ -2111,11 +2096,18 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu) root_gfn = 0; if (mmu_check_root(vcpu, root_gfn)) return 1; + if (tdp_enabled) { + direct = 1; + root_gfn = i << 30; + } + spin_lock(&vcpu->kvm->mmu_lock); sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, direct, ACC_ALL, NULL); root = __pa(sp->spt); ++sp->root_count; + spin_unlock(&vcpu->kvm->mmu_lock); + vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; } vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); @@ -2299,13 +2291,19 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) /* no rsvd bits for 2 level 4K page table entries */ context->rsvd_bits_mask[0][1] = 0; context->rsvd_bits_mask[0][0] = 0; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; + + if (!is_pse(vcpu)) { + context->rsvd_bits_mask[1][1] = 0; + break; + } + if (is_cpuid_PSE36()) /* 36bits PSE 4MB page */ context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); else /* 32 bits PSE 4MB page */ context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; break; case PT32E_ROOT_LEVEL: context->rsvd_bits_mask[0][2] = @@ -2318,7 +2316,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 62) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; break; case PT64_ROOT_LEVEL: context->rsvd_bits_mask[0][3] = exb_bit_rsvd | @@ -2336,7 +2334,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 20); /* large page */ - context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0]; + context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; break; } } @@ -2438,7 +2436,8 @@ static int init_kvm_softmmu(struct kvm_vcpu *vcpu) else r = paging32_init_context(vcpu); - vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level; + vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); + vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); return r; } @@ -2478,7 +2477,9 @@ int kvm_mmu_load(struct kvm_vcpu *vcpu) goto out; spin_lock(&vcpu->kvm->mmu_lock); kvm_mmu_free_some_pages(vcpu); + spin_unlock(&vcpu->kvm->mmu_lock); r = mmu_alloc_roots(vcpu); + spin_lock(&vcpu->kvm->mmu_lock); mmu_sync_roots(vcpu); spin_unlock(&vcpu->kvm->mmu_lock); if (r) @@ -2527,7 +2528,7 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, } ++vcpu->kvm->stat.mmu_pte_updated; - if (sp->role.glevels == PT32_ROOT_LEVEL) + if (!sp->role.cr4_pae) paging32_update_pte(vcpu, sp, spte, new); else paging64_update_pte(vcpu, sp, spte, new); @@ -2562,36 +2563,11 @@ static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) } static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, - const u8 *new, int bytes) + u64 gpte) { gfn_t gfn; - int r; - u64 gpte = 0; pfn_t pfn; - if (bytes != 4 && bytes != 8) - return; - - /* - * Assume that the pte write on a page table of the same type - * as the current vcpu paging mode. This is nearly always true - * (might be false while changing modes). Note it is verified later - * by update_pte(). - */ - if (is_pae(vcpu)) { - /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ - if ((bytes == 4) && (gpa % 4 == 0)) { - r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8); - if (r) - return; - memcpy((void *)&gpte + (gpa % 8), new, 4); - } else if ((bytes == 8) && (gpa % 8 == 0)) { - memcpy((void *)&gpte, new, 8); - } - } else { - if ((bytes == 4) && (gpa % 4 == 0)) - memcpy((void *)&gpte, new, 4); - } if (!is_present_gpte(gpte)) return; gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; @@ -2640,10 +2616,46 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, int flooded = 0; int npte; int r; + int invlpg_counter; pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); - mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes); + + invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); + + /* + * Assume that the pte write on a page table of the same type + * as the current vcpu paging mode. This is nearly always true + * (might be false while changing modes). Note it is verified later + * by update_pte(). + */ + if ((is_pae(vcpu) && bytes == 4) || !new) { + /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ + if (is_pae(vcpu)) { + gpa &= ~(gpa_t)7; + bytes = 8; + } + r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); + if (r) + gentry = 0; + new = (const u8 *)&gentry; + } + + switch (bytes) { + case 4: + gentry = *(const u32 *)new; + break; + case 8: + gentry = *(const u64 *)new; + break; + default: + gentry = 0; + break; + } + + mmu_guess_page_from_pte_write(vcpu, gpa, gentry); spin_lock(&vcpu->kvm->mmu_lock); + if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) + gentry = 0; kvm_mmu_access_page(vcpu, gfn); kvm_mmu_free_some_pages(vcpu); ++vcpu->kvm->stat.mmu_pte_write; @@ -2662,10 +2674,12 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, } index = kvm_page_table_hashfn(gfn); bucket = &vcpu->kvm->arch.mmu_page_hash[index]; + +restart: hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) { if (sp->gfn != gfn || sp->role.direct || sp->role.invalid) continue; - pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8; + pte_size = sp->role.cr4_pae ? 8 : 4; misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); misaligned |= bytes < 4; if (misaligned || flooded) { @@ -2682,14 +2696,14 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, pgprintk("misaligned: gpa %llx bytes %d role %x\n", gpa, bytes, sp->role.word); if (kvm_mmu_zap_page(vcpu->kvm, sp)) - n = bucket->first; + goto restart; ++vcpu->kvm->stat.mmu_flooded; continue; } page_offset = offset; level = sp->role.level; npte = 1; - if (sp->role.glevels == PT32_ROOT_LEVEL) { + if (!sp->role.cr4_pae) { page_offset <<= 1; /* 32->64 */ /* * A 32-bit pde maps 4MB while the shadow pdes map @@ -2707,20 +2721,11 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, continue; } spte = &sp->spt[page_offset / sizeof(*spte)]; - if ((gpa & (pte_size - 1)) || (bytes < pte_size)) { - gentry = 0; - r = kvm_read_guest_atomic(vcpu->kvm, - gpa & ~(u64)(pte_size - 1), - &gentry, pte_size); - new = (const void *)&gentry; - if (r < 0) - new = NULL; - } while (npte--) { entry = *spte; mmu_pte_write_zap_pte(vcpu, sp, spte); - if (new) - mmu_pte_write_new_pte(vcpu, sp, spte, new); + if (gentry) + mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); mmu_pte_write_flush_tlb(vcpu, entry, *spte); ++spte; } @@ -2900,22 +2905,23 @@ void kvm_mmu_zap_all(struct kvm *kvm) struct kvm_mmu_page *sp, *node; spin_lock(&kvm->mmu_lock); +restart: list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) if (kvm_mmu_zap_page(kvm, sp)) - node = container_of(kvm->arch.active_mmu_pages.next, - struct kvm_mmu_page, link); + goto restart; + spin_unlock(&kvm->mmu_lock); kvm_flush_remote_tlbs(kvm); } -static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm) +static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm) { struct kvm_mmu_page *page; page = container_of(kvm->arch.active_mmu_pages.prev, struct kvm_mmu_page, link); - kvm_mmu_zap_page(kvm, page); + return kvm_mmu_zap_page(kvm, page) + 1; } static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) @@ -2927,7 +2933,7 @@ static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) spin_lock(&kvm_lock); list_for_each_entry(kvm, &vm_list, vm_list) { - int npages, idx; + int npages, idx, freed_pages; idx = srcu_read_lock(&kvm->srcu); spin_lock(&kvm->mmu_lock); @@ -2935,8 +2941,8 @@ static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask) kvm->arch.n_free_mmu_pages; cache_count += npages; if (!kvm_freed && nr_to_scan > 0 && npages > 0) { - kvm_mmu_remove_one_alloc_mmu_page(kvm); - cache_count--; + freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm); + cache_count -= freed_pages; kvm_freed = kvm; } nr_to_scan--; @@ -3011,7 +3017,8 @@ unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) unsigned int nr_pages = 0; struct kvm_memslots *slots; - slots = rcu_dereference(kvm->memslots); + slots = kvm_memslots(kvm); + for (i = 0; i < slots->nmemslots; i++) nr_pages += slots->memslots[i].npages; @@ -3174,8 +3181,7 @@ static gva_t canonicalize(gva_t gva) } -typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp, - u64 *sptep); +typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep); static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, inspect_spte_fn fn) @@ -3191,7 +3197,7 @@ static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, child = page_header(ent & PT64_BASE_ADDR_MASK); __mmu_spte_walk(kvm, child, fn); } else - fn(kvm, sp, &sp->spt[i]); + fn(kvm, &sp->spt[i]); } } } @@ -3282,11 +3288,13 @@ static void audit_mappings(struct kvm_vcpu *vcpu) static int count_rmaps(struct kvm_vcpu *vcpu) { + struct kvm *kvm = vcpu->kvm; + struct kvm_memslots *slots; int nmaps = 0; int i, j, k, idx; idx = srcu_read_lock(&kvm->srcu); - slots = rcu_dereference(kvm->memslots); + slots = kvm_memslots(kvm); for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { struct kvm_memory_slot *m = &slots->memslots[i]; struct kvm_rmap_desc *d; @@ -3315,7 +3323,7 @@ static int count_rmaps(struct kvm_vcpu *vcpu) return nmaps; } -void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep) +void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) { unsigned long *rmapp; struct kvm_mmu_page *rev_sp; @@ -3331,14 +3339,14 @@ void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep) printk(KERN_ERR "%s: no memslot for gfn %ld\n", audit_msg, gfn); printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", - audit_msg, sptep - rev_sp->spt, + audit_msg, (long int)(sptep - rev_sp->spt), rev_sp->gfn); dump_stack(); return; } rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt], - is_large_pte(*sptep)); + rev_sp->role.level); if (!*rmapp) { if (!printk_ratelimit()) return; @@ -3373,7 +3381,7 @@ static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) continue; if (!(ent & PT_WRITABLE_MASK)) continue; - inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]); + inspect_spte_has_rmap(vcpu->kvm, &pt[i]); } } return; diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h index 3e4a5c6ca2a9..42f07b1bfbc9 100644 --- a/arch/x86/kvm/mmutrace.h +++ b/arch/x86/kvm/mmutrace.h @@ -6,14 +6,12 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvmmmu -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE mmutrace #define KVM_MMU_PAGE_FIELDS \ __field(__u64, gfn) \ __field(__u32, role) \ __field(__u32, root_count) \ - __field(__u32, unsync) + __field(bool, unsync) #define KVM_MMU_PAGE_ASSIGN(sp) \ __entry->gfn = sp->gfn; \ @@ -30,14 +28,14 @@ \ role.word = __entry->role; \ \ - trace_seq_printf(p, "sp gfn %llx %u/%u q%u%s %s%s %spge" \ + trace_seq_printf(p, "sp gfn %llx %u%s q%u%s %s%s" \ " %snxe root %u %s%c", \ - __entry->gfn, role.level, role.glevels, \ + __entry->gfn, role.level, \ + role.cr4_pae ? " pae" : "", \ role.quadrant, \ role.direct ? " direct" : "", \ access_str[role.access], \ role.invalid ? " invalid" : "", \ - role.cr4_pge ? "" : "!", \ role.nxe ? "" : "!", \ __entry->root_count, \ __entry->unsync ? "unsync" : "sync", 0); \ @@ -94,15 +92,15 @@ TRACE_EVENT( TP_printk("pte %llx level %u", __entry->pte, __entry->level) ); -/* We set a pte accessed bit */ -TRACE_EVENT( - kvm_mmu_set_accessed_bit, +DECLARE_EVENT_CLASS(kvm_mmu_set_bit_class, + TP_PROTO(unsigned long table_gfn, unsigned index, unsigned size), + TP_ARGS(table_gfn, index, size), TP_STRUCT__entry( __field(__u64, gpa) - ), + ), TP_fast_assign( __entry->gpa = ((u64)table_gfn << PAGE_SHIFT) @@ -112,22 +110,20 @@ TRACE_EVENT( TP_printk("gpa %llx", __entry->gpa) ); -/* We set a pte dirty bit */ -TRACE_EVENT( - kvm_mmu_set_dirty_bit, +/* We set a pte accessed bit */ +DEFINE_EVENT(kvm_mmu_set_bit_class, kvm_mmu_set_accessed_bit, + TP_PROTO(unsigned long table_gfn, unsigned index, unsigned size), - TP_ARGS(table_gfn, index, size), - TP_STRUCT__entry( - __field(__u64, gpa) - ), + TP_ARGS(table_gfn, index, size) +); - TP_fast_assign( - __entry->gpa = ((u64)table_gfn << PAGE_SHIFT) - + index * size; - ), +/* We set a pte dirty bit */ +DEFINE_EVENT(kvm_mmu_set_bit_class, kvm_mmu_set_dirty_bit, - TP_printk("gpa %llx", __entry->gpa) + TP_PROTO(unsigned long table_gfn, unsigned index, unsigned size), + + TP_ARGS(table_gfn, index, size) ); TRACE_EVENT( @@ -166,55 +162,45 @@ TRACE_EVENT( __entry->created ? "new" : "existing") ); -TRACE_EVENT( - kvm_mmu_sync_page, +DECLARE_EVENT_CLASS(kvm_mmu_page_class, + TP_PROTO(struct kvm_mmu_page *sp), TP_ARGS(sp), TP_STRUCT__entry( KVM_MMU_PAGE_FIELDS - ), + ), TP_fast_assign( KVM_MMU_PAGE_ASSIGN(sp) - ), + ), TP_printk("%s", KVM_MMU_PAGE_PRINTK()) ); -TRACE_EVENT( - kvm_mmu_unsync_page, +DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_sync_page, TP_PROTO(struct kvm_mmu_page *sp), - TP_ARGS(sp), - - TP_STRUCT__entry( - KVM_MMU_PAGE_FIELDS - ), - TP_fast_assign( - KVM_MMU_PAGE_ASSIGN(sp) - ), - - TP_printk("%s", KVM_MMU_PAGE_PRINTK()) + TP_ARGS(sp) ); -TRACE_EVENT( - kvm_mmu_zap_page, +DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_unsync_page, TP_PROTO(struct kvm_mmu_page *sp), - TP_ARGS(sp), - TP_STRUCT__entry( - KVM_MMU_PAGE_FIELDS - ), + TP_ARGS(sp) +); - TP_fast_assign( - KVM_MMU_PAGE_ASSIGN(sp) - ), +DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_zap_page, + TP_PROTO(struct kvm_mmu_page *sp), - TP_printk("%s", KVM_MMU_PAGE_PRINTK()) + TP_ARGS(sp) ); - #endif /* _TRACE_KVMMMU_H */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE mmutrace + /* This part must be outside protection */ #include <trace/define_trace.h> diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 81eab9a50e6a..89d66ca4d87c 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -170,7 +170,7 @@ walk: goto access_error; #if PTTYPE == 64 - if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK)) + if (fetch_fault && (pte & PT64_NX_MASK)) goto access_error; #endif @@ -190,10 +190,10 @@ walk: if ((walker->level == PT_PAGE_TABLE_LEVEL) || ((walker->level == PT_DIRECTORY_LEVEL) && - (pte & PT_PAGE_SIZE_MASK) && + is_large_pte(pte) && (PTTYPE == 64 || is_pse(vcpu))) || ((walker->level == PT_PDPE_LEVEL) && - (pte & PT_PAGE_SIZE_MASK) && + is_large_pte(pte) && is_long_mode(vcpu))) { int lvl = walker->level; @@ -258,11 +258,17 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, pt_element_t gpte; unsigned pte_access; pfn_t pfn; + u64 new_spte; gpte = *(const pt_element_t *)pte; if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { - if (!is_present_gpte(gpte)) - __set_spte(spte, shadow_notrap_nonpresent_pte); + if (!is_present_gpte(gpte)) { + if (page->unsync) + new_spte = shadow_trap_nonpresent_pte; + else + new_spte = shadow_notrap_nonpresent_pte; + __set_spte(spte, new_spte); + } return; } pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); @@ -457,6 +463,7 @@ out_unlock: static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) { struct kvm_shadow_walk_iterator iterator; + gpa_t pte_gpa = -1; int level; u64 *sptep; int need_flush = 0; @@ -467,9 +474,16 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) level = iterator.level; sptep = iterator.sptep; - if (level == PT_PAGE_TABLE_LEVEL || - ((level == PT_DIRECTORY_LEVEL && is_large_pte(*sptep))) || - ((level == PT_PDPE_LEVEL && is_large_pte(*sptep)))) { + if (is_last_spte(*sptep, level)) { + struct kvm_mmu_page *sp = page_header(__pa(sptep)); + int offset, shift; + + shift = PAGE_SHIFT - + (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; + offset = sp->role.quadrant << shift; + + pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; + pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); if (is_shadow_present_pte(*sptep)) { rmap_remove(vcpu->kvm, sptep); @@ -487,7 +501,17 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) if (need_flush) kvm_flush_remote_tlbs(vcpu->kvm); + + atomic_inc(&vcpu->kvm->arch.invlpg_counter); + spin_unlock(&vcpu->kvm->mmu_lock); + + if (pte_gpa == -1) + return; + + if (mmu_topup_memory_caches(vcpu)) + return; + kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); } static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, @@ -551,12 +575,15 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) { int i, offset, nr_present; bool reset_host_protection; + gpa_t first_pte_gpa; offset = nr_present = 0; if (PTTYPE == 32) offset = sp->role.quadrant << PT64_LEVEL_BITS; + first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); + for (i = 0; i < PT64_ENT_PER_PAGE; i++) { unsigned pte_access; pt_element_t gpte; @@ -566,8 +593,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) if (!is_shadow_present_pte(sp->spt[i])) continue; - pte_gpa = gfn_to_gpa(sp->gfn); - pte_gpa += (i+offset) * sizeof(pt_element_t); + pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, sizeof(pt_element_t))) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 737361fcd503..ce438e0fdd26 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -28,6 +28,7 @@ #include <linux/ftrace_event.h> #include <linux/slab.h> +#include <asm/tlbflush.h> #include <asm/desc.h> #include <asm/virtext.h> @@ -44,10 +45,11 @@ MODULE_LICENSE("GPL"); #define SEG_TYPE_LDT 2 #define SEG_TYPE_BUSY_TSS16 3 -#define SVM_FEATURE_NPT (1 << 0) -#define SVM_FEATURE_LBRV (1 << 1) -#define SVM_FEATURE_SVML (1 << 2) -#define SVM_FEATURE_PAUSE_FILTER (1 << 10) +#define SVM_FEATURE_NPT (1 << 0) +#define SVM_FEATURE_LBRV (1 << 1) +#define SVM_FEATURE_SVML (1 << 2) +#define SVM_FEATURE_NRIP (1 << 3) +#define SVM_FEATURE_PAUSE_FILTER (1 << 10) #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ @@ -55,6 +57,8 @@ MODULE_LICENSE("GPL"); #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) +static bool erratum_383_found __read_mostly; + static const u32 host_save_user_msrs[] = { #ifdef CONFIG_X86_64 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, @@ -70,6 +74,7 @@ struct kvm_vcpu; struct nested_state { struct vmcb *hsave; u64 hsave_msr; + u64 vm_cr_msr; u64 vmcb; /* These are the merged vectors */ @@ -77,6 +82,7 @@ struct nested_state { /* gpa pointers to the real vectors */ u64 vmcb_msrpm; + u64 vmcb_iopm; /* A VMEXIT is required but not yet emulated */ bool exit_required; @@ -91,6 +97,9 @@ struct nested_state { }; +#define MSRPM_OFFSETS 16 +static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; + struct vcpu_svm { struct kvm_vcpu vcpu; struct vmcb *vmcb; @@ -110,13 +119,39 @@ struct vcpu_svm { struct nested_state nested; bool nmi_singlestep; + + unsigned int3_injected; + unsigned long int3_rip; +}; + +#define MSR_INVALID 0xffffffffU + +static struct svm_direct_access_msrs { + u32 index; /* Index of the MSR */ + bool always; /* True if intercept is always on */ +} direct_access_msrs[] = { + { .index = MSR_K6_STAR, .always = true }, + { .index = MSR_IA32_SYSENTER_CS, .always = true }, +#ifdef CONFIG_X86_64 + { .index = MSR_GS_BASE, .always = true }, + { .index = MSR_FS_BASE, .always = true }, + { .index = MSR_KERNEL_GS_BASE, .always = true }, + { .index = MSR_LSTAR, .always = true }, + { .index = MSR_CSTAR, .always = true }, + { .index = MSR_SYSCALL_MASK, .always = true }, +#endif + { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, + { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, + { .index = MSR_IA32_LASTINTFROMIP, .always = false }, + { .index = MSR_IA32_LASTINTTOIP, .always = false }, + { .index = MSR_INVALID, .always = false }, }; /* enable NPT for AMD64 and X86 with PAE */ #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) static bool npt_enabled = true; #else -static bool npt_enabled = false; +static bool npt_enabled; #endif static int npt = 1; @@ -129,6 +164,7 @@ static void svm_flush_tlb(struct kvm_vcpu *vcpu); static void svm_complete_interrupts(struct vcpu_svm *svm); static int nested_svm_exit_handled(struct vcpu_svm *svm); +static int nested_svm_intercept(struct vcpu_svm *svm); static int nested_svm_vmexit(struct vcpu_svm *svm); static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, bool has_error_code, u32 error_code); @@ -163,8 +199,8 @@ static unsigned long iopm_base; struct kvm_ldttss_desc { u16 limit0; u16 base0; - unsigned base1 : 8, type : 5, dpl : 2, p : 1; - unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; + unsigned base1:8, type:5, dpl:2, p:1; + unsigned limit1:4, zero0:3, g:1, base2:8; u32 base3; u32 zero1; } __attribute__((packed)); @@ -194,6 +230,27 @@ static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; #define MSRS_RANGE_SIZE 2048 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) +static u32 svm_msrpm_offset(u32 msr) +{ + u32 offset; + int i; + + for (i = 0; i < NUM_MSR_MAPS; i++) { + if (msr < msrpm_ranges[i] || + msr >= msrpm_ranges[i] + MSRS_IN_RANGE) + continue; + + offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ + offset += (i * MSRS_RANGE_SIZE); /* add range offset */ + + /* Now we have the u8 offset - but need the u32 offset */ + return offset / 4; + } + + /* MSR not in any range */ + return MSR_INVALID; +} + #define MAX_INST_SIZE 15 static inline u32 svm_has(u32 feat) @@ -213,7 +270,7 @@ static inline void stgi(void) static inline void invlpga(unsigned long addr, u32 asid) { - asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); + asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); } static inline void force_new_asid(struct kvm_vcpu *vcpu) @@ -235,23 +292,6 @@ static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) vcpu->arch.efer = efer; } -static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, - bool has_error_code, u32 error_code) -{ - struct vcpu_svm *svm = to_svm(vcpu); - - /* If we are within a nested VM we'd better #VMEXIT and let the - guest handle the exception */ - if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) - return; - - svm->vmcb->control.event_inj = nr - | SVM_EVTINJ_VALID - | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) - | SVM_EVTINJ_TYPE_EXEPT; - svm->vmcb->control.event_inj_err = error_code; -} - static int is_external_interrupt(u32 info) { info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; @@ -264,7 +304,7 @@ static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) u32 ret = 0; if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) - ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS; + ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; return ret & mask; } @@ -283,6 +323,9 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); + if (svm->vmcb->control.next_rip != 0) + svm->next_rip = svm->vmcb->control.next_rip; + if (!svm->next_rip) { if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != EMULATE_DONE) @@ -297,6 +340,68 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu) svm_set_interrupt_shadow(vcpu, 0); } +static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, + bool has_error_code, u32 error_code, + bool reinject) +{ + struct vcpu_svm *svm = to_svm(vcpu); + + /* + * If we are within a nested VM we'd better #VMEXIT and let the guest + * handle the exception + */ + if (!reinject && + nested_svm_check_exception(svm, nr, has_error_code, error_code)) + return; + + if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) { + unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); + + /* + * For guest debugging where we have to reinject #BP if some + * INT3 is guest-owned: + * Emulate nRIP by moving RIP forward. Will fail if injection + * raises a fault that is not intercepted. Still better than + * failing in all cases. + */ + skip_emulated_instruction(&svm->vcpu); + rip = kvm_rip_read(&svm->vcpu); + svm->int3_rip = rip + svm->vmcb->save.cs.base; + svm->int3_injected = rip - old_rip; + } + + svm->vmcb->control.event_inj = nr + | SVM_EVTINJ_VALID + | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) + | SVM_EVTINJ_TYPE_EXEPT; + svm->vmcb->control.event_inj_err = error_code; +} + +static void svm_init_erratum_383(void) +{ + u32 low, high; + int err; + u64 val; + + /* Only Fam10h is affected */ + if (boot_cpu_data.x86 != 0x10) + return; + + /* Use _safe variants to not break nested virtualization */ + val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); + if (err) + return; + + val |= (1ULL << 47); + + low = lower_32_bits(val); + high = upper_32_bits(val); + + native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); + + erratum_383_found = true; +} + static int has_svm(void) { const char *msg; @@ -319,7 +424,7 @@ static int svm_hardware_enable(void *garbage) struct svm_cpu_data *sd; uint64_t efer; - struct descriptor_table gdt_descr; + struct desc_ptr gdt_descr; struct desc_struct *gdt; int me = raw_smp_processor_id(); @@ -344,14 +449,16 @@ static int svm_hardware_enable(void *garbage) sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; sd->next_asid = sd->max_asid + 1; - kvm_get_gdt(&gdt_descr); - gdt = (struct desc_struct *)gdt_descr.base; + native_store_gdt(&gdt_descr); + gdt = (struct desc_struct *)gdt_descr.address; sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); wrmsrl(MSR_EFER, efer | EFER_SVME); wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); + svm_init_erratum_383(); + return 0; } @@ -391,42 +498,98 @@ err_1: } +static bool valid_msr_intercept(u32 index) +{ + int i; + + for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) + if (direct_access_msrs[i].index == index) + return true; + + return false; +} + static void set_msr_interception(u32 *msrpm, unsigned msr, int read, int write) { + u8 bit_read, bit_write; + unsigned long tmp; + u32 offset; + + /* + * If this warning triggers extend the direct_access_msrs list at the + * beginning of the file + */ + WARN_ON(!valid_msr_intercept(msr)); + + offset = svm_msrpm_offset(msr); + bit_read = 2 * (msr & 0x0f); + bit_write = 2 * (msr & 0x0f) + 1; + tmp = msrpm[offset]; + + BUG_ON(offset == MSR_INVALID); + + read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); + write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); + + msrpm[offset] = tmp; +} + +static void svm_vcpu_init_msrpm(u32 *msrpm) +{ int i; - for (i = 0; i < NUM_MSR_MAPS; i++) { - if (msr >= msrpm_ranges[i] && - msr < msrpm_ranges[i] + MSRS_IN_RANGE) { - u32 msr_offset = (i * MSRS_IN_RANGE + msr - - msrpm_ranges[i]) * 2; - - u32 *base = msrpm + (msr_offset / 32); - u32 msr_shift = msr_offset % 32; - u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); - *base = (*base & ~(0x3 << msr_shift)) | - (mask << msr_shift); + memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); + + for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { + if (!direct_access_msrs[i].always) + continue; + + set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); + } +} + +static void add_msr_offset(u32 offset) +{ + int i; + + for (i = 0; i < MSRPM_OFFSETS; ++i) { + + /* Offset already in list? */ + if (msrpm_offsets[i] == offset) return; - } + + /* Slot used by another offset? */ + if (msrpm_offsets[i] != MSR_INVALID) + continue; + + /* Add offset to list */ + msrpm_offsets[i] = offset; + + return; } + + /* + * If this BUG triggers the msrpm_offsets table has an overflow. Just + * increase MSRPM_OFFSETS in this case. + */ BUG(); } -static void svm_vcpu_init_msrpm(u32 *msrpm) +static void init_msrpm_offsets(void) { - memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); + int i; -#ifdef CONFIG_X86_64 - set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); - set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); - set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); - set_msr_interception(msrpm, MSR_LSTAR, 1, 1); - set_msr_interception(msrpm, MSR_CSTAR, 1, 1); - set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); -#endif - set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); - set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); + memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); + + for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { + u32 offset; + + offset = svm_msrpm_offset(direct_access_msrs[i].index); + BUG_ON(offset == MSR_INVALID); + + add_msr_offset(offset); + } } static void svm_enable_lbrv(struct vcpu_svm *svm) @@ -467,6 +630,8 @@ static __init int svm_hardware_setup(void) memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; + init_msrpm_offsets(); + if (boot_cpu_has(X86_FEATURE_NX)) kvm_enable_efer_bits(EFER_NX); @@ -523,7 +688,7 @@ static void init_seg(struct vmcb_seg *seg) { seg->selector = 0; seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | - SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ + SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ seg->limit = 0xffff; seg->base = 0; } @@ -543,16 +708,16 @@ static void init_vmcb(struct vcpu_svm *svm) svm->vcpu.fpu_active = 1; - control->intercept_cr_read = INTERCEPT_CR0_MASK | + control->intercept_cr_read = INTERCEPT_CR0_MASK | INTERCEPT_CR3_MASK | INTERCEPT_CR4_MASK; - control->intercept_cr_write = INTERCEPT_CR0_MASK | + control->intercept_cr_write = INTERCEPT_CR0_MASK | INTERCEPT_CR3_MASK | INTERCEPT_CR4_MASK | INTERCEPT_CR8_MASK; - control->intercept_dr_read = INTERCEPT_DR0_MASK | + control->intercept_dr_read = INTERCEPT_DR0_MASK | INTERCEPT_DR1_MASK | INTERCEPT_DR2_MASK | INTERCEPT_DR3_MASK | @@ -561,7 +726,7 @@ static void init_vmcb(struct vcpu_svm *svm) INTERCEPT_DR6_MASK | INTERCEPT_DR7_MASK; - control->intercept_dr_write = INTERCEPT_DR0_MASK | + control->intercept_dr_write = INTERCEPT_DR0_MASK | INTERCEPT_DR1_MASK | INTERCEPT_DR2_MASK | INTERCEPT_DR3_MASK | @@ -575,7 +740,7 @@ static void init_vmcb(struct vcpu_svm *svm) (1 << MC_VECTOR); - control->intercept = (1ULL << INTERCEPT_INTR) | + control->intercept = (1ULL << INTERCEPT_INTR) | (1ULL << INTERCEPT_NMI) | (1ULL << INTERCEPT_SMI) | (1ULL << INTERCEPT_SELECTIVE_CR0) | @@ -636,7 +801,8 @@ static void init_vmcb(struct vcpu_svm *svm) save->rip = 0x0000fff0; svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; - /* This is the guest-visible cr0 value. + /* + * This is the guest-visible cr0 value. * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. */ svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; @@ -729,6 +895,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) svm_vcpu_init_msrpm(svm->msrpm); svm->nested.msrpm = page_address(nested_msrpm_pages); + svm_vcpu_init_msrpm(svm->nested.msrpm); svm->vmcb = page_address(page); clear_page(svm->vmcb); @@ -882,7 +1049,8 @@ static void svm_get_segment(struct kvm_vcpu *vcpu, var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; - /* AMD's VMCB does not have an explicit unusable field, so emulate it + /* + * AMD's VMCB does not have an explicit unusable field, so emulate it * for cross vendor migration purposes by "not present" */ var->unusable = !var->present || (var->type == 0); @@ -918,7 +1086,8 @@ static void svm_get_segment(struct kvm_vcpu *vcpu, var->type |= 0x1; break; case VCPU_SREG_SS: - /* On AMD CPUs sometimes the DB bit in the segment + /* + * On AMD CPUs sometimes the DB bit in the segment * descriptor is left as 1, although the whole segment has * been made unusable. Clear it here to pass an Intel VMX * entry check when cross vendor migrating. @@ -936,36 +1105,36 @@ static int svm_get_cpl(struct kvm_vcpu *vcpu) return save->cpl; } -static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { struct vcpu_svm *svm = to_svm(vcpu); - dt->limit = svm->vmcb->save.idtr.limit; - dt->base = svm->vmcb->save.idtr.base; + dt->size = svm->vmcb->save.idtr.limit; + dt->address = svm->vmcb->save.idtr.base; } -static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { struct vcpu_svm *svm = to_svm(vcpu); - svm->vmcb->save.idtr.limit = dt->limit; - svm->vmcb->save.idtr.base = dt->base ; + svm->vmcb->save.idtr.limit = dt->size; + svm->vmcb->save.idtr.base = dt->address ; } -static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { struct vcpu_svm *svm = to_svm(vcpu); - dt->limit = svm->vmcb->save.gdtr.limit; - dt->base = svm->vmcb->save.gdtr.base; + dt->size = svm->vmcb->save.gdtr.limit; + dt->address = svm->vmcb->save.gdtr.base; } -static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { struct vcpu_svm *svm = to_svm(vcpu); - svm->vmcb->save.gdtr.limit = dt->limit; - svm->vmcb->save.gdtr.base = dt->base ; + svm->vmcb->save.gdtr.limit = dt->size; + svm->vmcb->save.gdtr.base = dt->address ; } static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) @@ -978,6 +1147,7 @@ static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) static void update_cr0_intercept(struct vcpu_svm *svm) { + struct vmcb *vmcb = svm->vmcb; ulong gcr0 = svm->vcpu.arch.cr0; u64 *hcr0 = &svm->vmcb->save.cr0; @@ -989,11 +1159,25 @@ static void update_cr0_intercept(struct vcpu_svm *svm) if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { - svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; - svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; + vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; + vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; + if (is_nested(svm)) { + struct vmcb *hsave = svm->nested.hsave; + + hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; + hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; + vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read; + vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write; + } } else { svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; + if (is_nested(svm)) { + struct vmcb *hsave = svm->nested.hsave; + + hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK; + hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK; + } } } @@ -1001,6 +1185,27 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) { struct vcpu_svm *svm = to_svm(vcpu); + if (is_nested(svm)) { + /* + * We are here because we run in nested mode, the host kvm + * intercepts cr0 writes but the l1 hypervisor does not. + * But the L1 hypervisor may intercept selective cr0 writes. + * This needs to be checked here. + */ + unsigned long old, new; + + /* Remove bits that would trigger a real cr0 write intercept */ + old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; + new = cr0 & SVM_CR0_SELECTIVE_MASK; + + if (old == new) { + /* cr0 write with ts and mp unchanged */ + svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; + if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) + return; + } + } + #ifdef CONFIG_X86_64 if (vcpu->arch.efer & EFER_LME) { if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { @@ -1134,70 +1339,11 @@ static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) svm->vmcb->control.asid = sd->next_asid++; } -static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest) +static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) { struct vcpu_svm *svm = to_svm(vcpu); - switch (dr) { - case 0 ... 3: - *dest = vcpu->arch.db[dr]; - break; - case 4: - if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) - return EMULATE_FAIL; /* will re-inject UD */ - /* fall through */ - case 6: - if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) - *dest = vcpu->arch.dr6; - else - *dest = svm->vmcb->save.dr6; - break; - case 5: - if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) - return EMULATE_FAIL; /* will re-inject UD */ - /* fall through */ - case 7: - if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) - *dest = vcpu->arch.dr7; - else - *dest = svm->vmcb->save.dr7; - break; - } - - return EMULATE_DONE; -} - -static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value) -{ - struct vcpu_svm *svm = to_svm(vcpu); - - switch (dr) { - case 0 ... 3: - vcpu->arch.db[dr] = value; - if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) - vcpu->arch.eff_db[dr] = value; - break; - case 4: - if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) - return EMULATE_FAIL; /* will re-inject UD */ - /* fall through */ - case 6: - vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1; - break; - case 5: - if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) - return EMULATE_FAIL; /* will re-inject UD */ - /* fall through */ - case 7: - vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1; - if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { - svm->vmcb->save.dr7 = vcpu->arch.dr7; - vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK); - } - break; - } - - return EMULATE_DONE; + svm->vmcb->save.dr7 = value; } static int pf_interception(struct vcpu_svm *svm) @@ -1234,7 +1380,7 @@ static int db_interception(struct vcpu_svm *svm) } if (svm->vcpu.guest_debug & - (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){ + (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { kvm_run->exit_reason = KVM_EXIT_DEBUG; kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; @@ -1268,7 +1414,22 @@ static int ud_interception(struct vcpu_svm *svm) static void svm_fpu_activate(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); - svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); + u32 excp; + + if (is_nested(svm)) { + u32 h_excp, n_excp; + + h_excp = svm->nested.hsave->control.intercept_exceptions; + n_excp = svm->nested.intercept_exceptions; + h_excp &= ~(1 << NM_VECTOR); + excp = h_excp | n_excp; + } else { + excp = svm->vmcb->control.intercept_exceptions; + excp &= ~(1 << NM_VECTOR); + } + + svm->vmcb->control.intercept_exceptions = excp; + svm->vcpu.fpu_active = 1; update_cr0_intercept(svm); } @@ -1279,8 +1440,59 @@ static int nm_interception(struct vcpu_svm *svm) return 1; } -static int mc_interception(struct vcpu_svm *svm) +static bool is_erratum_383(void) { + int err, i; + u64 value; + + if (!erratum_383_found) + return false; + + value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); + if (err) + return false; + + /* Bit 62 may or may not be set for this mce */ + value &= ~(1ULL << 62); + + if (value != 0xb600000000010015ULL) + return false; + + /* Clear MCi_STATUS registers */ + for (i = 0; i < 6; ++i) + native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); + + value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); + if (!err) { + u32 low, high; + + value &= ~(1ULL << 2); + low = lower_32_bits(value); + high = upper_32_bits(value); + + native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); + } + + /* Flush tlb to evict multi-match entries */ + __flush_tlb_all(); + + return true; +} + +static void svm_handle_mce(struct vcpu_svm *svm) +{ + if (is_erratum_383()) { + /* + * Erratum 383 triggered. Guest state is corrupt so kill the + * guest. + */ + pr_err("KVM: Guest triggered AMD Erratum 383\n"); + + set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests); + + return; + } + /* * On an #MC intercept the MCE handler is not called automatically in * the host. So do it by hand here. @@ -1289,6 +1501,11 @@ static int mc_interception(struct vcpu_svm *svm) "int $0x12\n"); /* not sure if we ever come back to this point */ + return; +} + +static int mc_interception(struct vcpu_svm *svm) +{ return 1; } @@ -1309,29 +1526,23 @@ static int shutdown_interception(struct vcpu_svm *svm) static int io_interception(struct vcpu_svm *svm) { + struct kvm_vcpu *vcpu = &svm->vcpu; u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ int size, in, string; unsigned port; ++svm->vcpu.stat.io_exits; - - svm->next_rip = svm->vmcb->control.exit_info_2; - string = (io_info & SVM_IOIO_STR_MASK) != 0; - - if (string) { - if (emulate_instruction(&svm->vcpu, - 0, 0, 0) == EMULATE_DO_MMIO) - return 0; - return 1; - } - in = (io_info & SVM_IOIO_TYPE_MASK) != 0; + if (string || in) + return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO); + port = io_info >> 16; size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; - + svm->next_rip = svm->vmcb->control.exit_info_2; skip_emulated_instruction(&svm->vcpu); - return kvm_emulate_pio(&svm->vcpu, in, size, port); + + return kvm_fast_pio_out(vcpu, size, port); } static int nmi_interception(struct vcpu_svm *svm) @@ -1384,6 +1595,8 @@ static int nested_svm_check_permissions(struct vcpu_svm *svm) static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, bool has_error_code, u32 error_code) { + int vmexit; + if (!is_nested(svm)) return 0; @@ -1392,21 +1605,28 @@ static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, svm->vmcb->control.exit_info_1 = error_code; svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; - return nested_svm_exit_handled(svm); + vmexit = nested_svm_intercept(svm); + if (vmexit == NESTED_EXIT_DONE) + svm->nested.exit_required = true; + + return vmexit; } -static inline int nested_svm_intr(struct vcpu_svm *svm) +/* This function returns true if it is save to enable the irq window */ +static inline bool nested_svm_intr(struct vcpu_svm *svm) { if (!is_nested(svm)) - return 0; + return true; if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) - return 0; + return true; if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) - return 0; + return false; - svm->vmcb->control.exit_code = SVM_EXIT_INTR; + svm->vmcb->control.exit_code = SVM_EXIT_INTR; + svm->vmcb->control.exit_info_1 = 0; + svm->vmcb->control.exit_info_2 = 0; if (svm->nested.intercept & 1ULL) { /* @@ -1417,21 +1637,40 @@ static inline int nested_svm_intr(struct vcpu_svm *svm) */ svm->nested.exit_required = true; trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); - return 1; + return false; } - return 0; + return true; } -static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx) +/* This function returns true if it is save to enable the nmi window */ +static inline bool nested_svm_nmi(struct vcpu_svm *svm) +{ + if (!is_nested(svm)) + return true; + + if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) + return true; + + svm->vmcb->control.exit_code = SVM_EXIT_NMI; + svm->nested.exit_required = true; + + return false; +} + +static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) { struct page *page; + might_sleep(); + page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); if (is_error_page(page)) goto error; - return kmap_atomic(page, idx); + *_page = page; + + return kmap(page); error: kvm_release_page_clean(page); @@ -1440,61 +1679,55 @@ error: return NULL; } -static void nested_svm_unmap(void *addr, enum km_type idx) +static void nested_svm_unmap(struct page *page) { - struct page *page; + kunmap(page); + kvm_release_page_dirty(page); +} - if (!addr) - return; +static int nested_svm_intercept_ioio(struct vcpu_svm *svm) +{ + unsigned port; + u8 val, bit; + u64 gpa; - page = kmap_atomic_to_page(addr); + if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) + return NESTED_EXIT_HOST; - kunmap_atomic(addr, idx); - kvm_release_page_dirty(page); + port = svm->vmcb->control.exit_info_1 >> 16; + gpa = svm->nested.vmcb_iopm + (port / 8); + bit = port % 8; + val = 0; + + if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) + val &= (1 << bit); + + return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; } -static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm) +static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) { - u32 param = svm->vmcb->control.exit_info_1 & 1; - u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; - bool ret = false; - u32 t0, t1; - u8 *msrpm; + u32 offset, msr, value; + int write, mask; if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) - return false; + return NESTED_EXIT_HOST; - msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); + msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; + offset = svm_msrpm_offset(msr); + write = svm->vmcb->control.exit_info_1 & 1; + mask = 1 << ((2 * (msr & 0xf)) + write); - if (!msrpm) - goto out; + if (offset == MSR_INVALID) + return NESTED_EXIT_DONE; - switch (msr) { - case 0 ... 0x1fff: - t0 = (msr * 2) % 8; - t1 = msr / 8; - break; - case 0xc0000000 ... 0xc0001fff: - t0 = (8192 + msr - 0xc0000000) * 2; - t1 = (t0 / 8); - t0 %= 8; - break; - case 0xc0010000 ... 0xc0011fff: - t0 = (16384 + msr - 0xc0010000) * 2; - t1 = (t0 / 8); - t0 %= 8; - break; - default: - ret = true; - goto out; - } - - ret = msrpm[t1] & ((1 << param) << t0); + /* Offset is in 32 bit units but need in 8 bit units */ + offset *= 4; -out: - nested_svm_unmap(msrpm, KM_USER0); + if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) + return NESTED_EXIT_DONE; - return ret; + return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; } static int nested_svm_exit_special(struct vcpu_svm *svm) @@ -1504,17 +1737,21 @@ static int nested_svm_exit_special(struct vcpu_svm *svm) switch (exit_code) { case SVM_EXIT_INTR: case SVM_EXIT_NMI: + case SVM_EXIT_EXCP_BASE + MC_VECTOR: return NESTED_EXIT_HOST; - /* For now we are always handling NPFs when using them */ case SVM_EXIT_NPF: + /* For now we are always handling NPFs when using them */ if (npt_enabled) return NESTED_EXIT_HOST; break; - /* When we're shadowing, trap PFs */ case SVM_EXIT_EXCP_BASE + PF_VECTOR: + /* When we're shadowing, trap PFs */ if (!npt_enabled) return NESTED_EXIT_HOST; break; + case SVM_EXIT_EXCP_BASE + NM_VECTOR: + nm_interception(svm); + break; default: break; } @@ -1525,7 +1762,7 @@ static int nested_svm_exit_special(struct vcpu_svm *svm) /* * If this function returns true, this #vmexit was already handled */ -static int nested_svm_exit_handled(struct vcpu_svm *svm) +static int nested_svm_intercept(struct vcpu_svm *svm) { u32 exit_code = svm->vmcb->control.exit_code; int vmexit = NESTED_EXIT_HOST; @@ -1534,6 +1771,9 @@ static int nested_svm_exit_handled(struct vcpu_svm *svm) case SVM_EXIT_MSR: vmexit = nested_svm_exit_handled_msr(svm); break; + case SVM_EXIT_IOIO: + vmexit = nested_svm_intercept_ioio(svm); + break; case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); if (svm->nested.intercept_cr_read & cr_bits) @@ -1564,6 +1804,10 @@ static int nested_svm_exit_handled(struct vcpu_svm *svm) vmexit = NESTED_EXIT_DONE; break; } + case SVM_EXIT_ERR: { + vmexit = NESTED_EXIT_DONE; + break; + } default: { u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); if (svm->nested.intercept & exit_bits) @@ -1571,9 +1815,17 @@ static int nested_svm_exit_handled(struct vcpu_svm *svm) } } - if (vmexit == NESTED_EXIT_DONE) { + return vmexit; +} + +static int nested_svm_exit_handled(struct vcpu_svm *svm) +{ + int vmexit; + + vmexit = nested_svm_intercept(svm); + + if (vmexit == NESTED_EXIT_DONE) nested_svm_vmexit(svm); - } return vmexit; } @@ -1615,6 +1867,7 @@ static int nested_svm_vmexit(struct vcpu_svm *svm) struct vmcb *nested_vmcb; struct vmcb *hsave = svm->nested.hsave; struct vmcb *vmcb = svm->vmcb; + struct page *page; trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, vmcb->control.exit_info_1, @@ -1622,10 +1875,13 @@ static int nested_svm_vmexit(struct vcpu_svm *svm) vmcb->control.exit_int_info, vmcb->control.exit_int_info_err); - nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0); + nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); if (!nested_vmcb) return 1; + /* Exit nested SVM mode */ + svm->nested.vmcb = 0; + /* Give the current vmcb to the guest */ disable_gif(svm); @@ -1635,9 +1891,10 @@ static int nested_svm_vmexit(struct vcpu_svm *svm) nested_vmcb->save.ds = vmcb->save.ds; nested_vmcb->save.gdtr = vmcb->save.gdtr; nested_vmcb->save.idtr = vmcb->save.idtr; - if (npt_enabled) - nested_vmcb->save.cr3 = vmcb->save.cr3; + nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); + nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; nested_vmcb->save.cr2 = vmcb->save.cr2; + nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; nested_vmcb->save.rflags = vmcb->save.rflags; nested_vmcb->save.rip = vmcb->save.rip; nested_vmcb->save.rsp = vmcb->save.rsp; @@ -1709,10 +1966,7 @@ static int nested_svm_vmexit(struct vcpu_svm *svm) svm->vmcb->save.cpl = 0; svm->vmcb->control.exit_int_info = 0; - /* Exit nested SVM mode */ - svm->nested.vmcb = 0; - - nested_svm_unmap(nested_vmcb, KM_USER0); + nested_svm_unmap(page); kvm_mmu_reset_context(&svm->vcpu); kvm_mmu_load(&svm->vcpu); @@ -1722,19 +1976,33 @@ static int nested_svm_vmexit(struct vcpu_svm *svm) static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) { - u32 *nested_msrpm; + /* + * This function merges the msr permission bitmaps of kvm and the + * nested vmcb. It is omptimized in that it only merges the parts where + * the kvm msr permission bitmap may contain zero bits + */ int i; - nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); - if (!nested_msrpm) - return false; + if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) + return true; - for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) - svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; + for (i = 0; i < MSRPM_OFFSETS; i++) { + u32 value, p; + u64 offset; - svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); + if (msrpm_offsets[i] == 0xffffffff) + break; + + p = msrpm_offsets[i]; + offset = svm->nested.vmcb_msrpm + (p * 4); - nested_svm_unmap(nested_msrpm, KM_USER0); + if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) + return false; + + svm->nested.msrpm[p] = svm->msrpm[p] | value; + } + + svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); return true; } @@ -1744,26 +2012,34 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm) struct vmcb *nested_vmcb; struct vmcb *hsave = svm->nested.hsave; struct vmcb *vmcb = svm->vmcb; + struct page *page; + u64 vmcb_gpa; + + vmcb_gpa = svm->vmcb->save.rax; - nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); + nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); if (!nested_vmcb) return false; - /* nested_vmcb is our indicator if nested SVM is activated */ - svm->nested.vmcb = svm->vmcb->save.rax; - - trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb, + trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa, nested_vmcb->save.rip, nested_vmcb->control.int_ctl, nested_vmcb->control.event_inj, nested_vmcb->control.nested_ctl); + trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read, + nested_vmcb->control.intercept_cr_write, + nested_vmcb->control.intercept_exceptions, + nested_vmcb->control.intercept); + /* Clear internal status */ kvm_clear_exception_queue(&svm->vcpu); kvm_clear_interrupt_queue(&svm->vcpu); - /* Save the old vmcb, so we don't need to pick what we save, but - can restore everything when a VMEXIT occurs */ + /* + * Save the old vmcb, so we don't need to pick what we save, but can + * restore everything when a VMEXIT occurs + */ hsave->save.es = vmcb->save.es; hsave->save.cs = vmcb->save.cs; hsave->save.ss = vmcb->save.ss; @@ -1803,14 +2079,17 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm) if (npt_enabled) { svm->vmcb->save.cr3 = nested_vmcb->save.cr3; svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; - } else { + } else kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); - kvm_mmu_reset_context(&svm->vcpu); - } + + /* Guest paging mode is active - reset mmu */ + kvm_mmu_reset_context(&svm->vcpu); + svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); + /* In case we don't even reach vcpu_run, the fields are not updated */ svm->vmcb->save.rax = nested_vmcb->save.rax; svm->vmcb->save.rsp = nested_vmcb->save.rsp; @@ -1819,22 +2098,8 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm) svm->vmcb->save.dr6 = nested_vmcb->save.dr6; svm->vmcb->save.cpl = nested_vmcb->save.cpl; - /* We don't want a nested guest to be more powerful than the guest, - so all intercepts are ORed */ - svm->vmcb->control.intercept_cr_read |= - nested_vmcb->control.intercept_cr_read; - svm->vmcb->control.intercept_cr_write |= - nested_vmcb->control.intercept_cr_write; - svm->vmcb->control.intercept_dr_read |= - nested_vmcb->control.intercept_dr_read; - svm->vmcb->control.intercept_dr_write |= - nested_vmcb->control.intercept_dr_write; - svm->vmcb->control.intercept_exceptions |= - nested_vmcb->control.intercept_exceptions; - - svm->vmcb->control.intercept |= nested_vmcb->control.intercept; - - svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; + svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; + svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; /* cache intercepts */ svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; @@ -1851,13 +2116,43 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm) else svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; + if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { + /* We only want the cr8 intercept bits of the guest */ + svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK; + svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; + } + + /* We don't want to see VMMCALLs from a nested guest */ + svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL); + + /* + * We don't want a nested guest to be more powerful than the guest, so + * all intercepts are ORed + */ + svm->vmcb->control.intercept_cr_read |= + nested_vmcb->control.intercept_cr_read; + svm->vmcb->control.intercept_cr_write |= + nested_vmcb->control.intercept_cr_write; + svm->vmcb->control.intercept_dr_read |= + nested_vmcb->control.intercept_dr_read; + svm->vmcb->control.intercept_dr_write |= + nested_vmcb->control.intercept_dr_write; + svm->vmcb->control.intercept_exceptions |= + nested_vmcb->control.intercept_exceptions; + + svm->vmcb->control.intercept |= nested_vmcb->control.intercept; + + svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; svm->vmcb->control.int_state = nested_vmcb->control.int_state; svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; - nested_svm_unmap(nested_vmcb, KM_USER0); + nested_svm_unmap(page); + + /* nested_vmcb is our indicator if nested SVM is activated */ + svm->nested.vmcb = vmcb_gpa; enable_gif(svm); @@ -1883,6 +2178,7 @@ static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) static int vmload_interception(struct vcpu_svm *svm) { struct vmcb *nested_vmcb; + struct page *page; if (nested_svm_check_permissions(svm)) return 1; @@ -1890,12 +2186,12 @@ static int vmload_interception(struct vcpu_svm *svm) svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; skip_emulated_instruction(&svm->vcpu); - nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); + nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); if (!nested_vmcb) return 1; nested_svm_vmloadsave(nested_vmcb, svm->vmcb); - nested_svm_unmap(nested_vmcb, KM_USER0); + nested_svm_unmap(page); return 1; } @@ -1903,6 +2199,7 @@ static int vmload_interception(struct vcpu_svm *svm) static int vmsave_interception(struct vcpu_svm *svm) { struct vmcb *nested_vmcb; + struct page *page; if (nested_svm_check_permissions(svm)) return 1; @@ -1910,12 +2207,12 @@ static int vmsave_interception(struct vcpu_svm *svm) svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; skip_emulated_instruction(&svm->vcpu); - nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); + nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); if (!nested_vmcb) return 1; nested_svm_vmloadsave(svm->vmcb, nested_vmcb); - nested_svm_unmap(nested_vmcb, KM_USER0); + nested_svm_unmap(page); return 1; } @@ -2018,6 +2315,8 @@ static int task_switch_interception(struct vcpu_svm *svm) svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; uint32_t idt_v = svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; + bool has_error_code = false; + u32 error_code = 0; tss_selector = (u16)svm->vmcb->control.exit_info_1; @@ -2038,6 +2337,12 @@ static int task_switch_interception(struct vcpu_svm *svm) svm->vcpu.arch.nmi_injected = false; break; case SVM_EXITINTINFO_TYPE_EXEPT: + if (svm->vmcb->control.exit_info_2 & + (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { + has_error_code = true; + error_code = + (u32)svm->vmcb->control.exit_info_2; + } kvm_clear_exception_queue(&svm->vcpu); break; case SVM_EXITINTINFO_TYPE_INTR: @@ -2054,7 +2359,14 @@ static int task_switch_interception(struct vcpu_svm *svm) (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) skip_emulated_instruction(&svm->vcpu); - return kvm_task_switch(&svm->vcpu, tss_selector, reason); + if (kvm_task_switch(&svm->vcpu, tss_selector, reason, + has_error_code, error_code) == EMULATE_FAIL) { + svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; + svm->vcpu.run->internal.ndata = 0; + return 0; + } + return 1; } static int cpuid_interception(struct vcpu_svm *svm) @@ -2145,9 +2457,11 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) case MSR_IA32_SYSENTER_ESP: *data = svm->sysenter_esp; break; - /* Nobody will change the following 5 values in the VMCB so - we can safely return them on rdmsr. They will always be 0 - until LBRV is implemented. */ + /* + * Nobody will change the following 5 values in the VMCB so we can + * safely return them on rdmsr. They will always be 0 until LBRV is + * implemented. + */ case MSR_IA32_DEBUGCTLMSR: *data = svm->vmcb->save.dbgctl; break; @@ -2167,7 +2481,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) *data = svm->nested.hsave_msr; break; case MSR_VM_CR: - *data = 0; + *data = svm->nested.vm_cr_msr; break; case MSR_IA32_UCODE_REV: *data = 0x01000065; @@ -2197,6 +2511,31 @@ static int rdmsr_interception(struct vcpu_svm *svm) return 1; } +static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) +{ + struct vcpu_svm *svm = to_svm(vcpu); + int svm_dis, chg_mask; + + if (data & ~SVM_VM_CR_VALID_MASK) + return 1; + + chg_mask = SVM_VM_CR_VALID_MASK; + + if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) + chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); + + svm->nested.vm_cr_msr &= ~chg_mask; + svm->nested.vm_cr_msr |= (data & chg_mask); + + svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; + + /* check for svm_disable while efer.svme is set */ + if (svm_dis && (vcpu->arch.efer & EFER_SVME)) + return 1; + + return 0; +} + static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) { struct vcpu_svm *svm = to_svm(vcpu); @@ -2263,6 +2602,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) svm->nested.hsave_msr = data; break; case MSR_VM_CR: + return svm_set_vm_cr(vcpu, data); case MSR_VM_IGNNE: pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); break; @@ -2326,16 +2666,16 @@ static int pause_interception(struct vcpu_svm *svm) } static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { - [SVM_EXIT_READ_CR0] = emulate_on_interception, - [SVM_EXIT_READ_CR3] = emulate_on_interception, - [SVM_EXIT_READ_CR4] = emulate_on_interception, - [SVM_EXIT_READ_CR8] = emulate_on_interception, + [SVM_EXIT_READ_CR0] = emulate_on_interception, + [SVM_EXIT_READ_CR3] = emulate_on_interception, + [SVM_EXIT_READ_CR4] = emulate_on_interception, + [SVM_EXIT_READ_CR8] = emulate_on_interception, [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, - [SVM_EXIT_WRITE_CR0] = emulate_on_interception, - [SVM_EXIT_WRITE_CR3] = emulate_on_interception, - [SVM_EXIT_WRITE_CR4] = emulate_on_interception, - [SVM_EXIT_WRITE_CR8] = cr8_write_interception, - [SVM_EXIT_READ_DR0] = emulate_on_interception, + [SVM_EXIT_WRITE_CR0] = emulate_on_interception, + [SVM_EXIT_WRITE_CR3] = emulate_on_interception, + [SVM_EXIT_WRITE_CR4] = emulate_on_interception, + [SVM_EXIT_WRITE_CR8] = cr8_write_interception, + [SVM_EXIT_READ_DR0] = emulate_on_interception, [SVM_EXIT_READ_DR1] = emulate_on_interception, [SVM_EXIT_READ_DR2] = emulate_on_interception, [SVM_EXIT_READ_DR3] = emulate_on_interception, @@ -2354,15 +2694,14 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, - [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, - [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, - [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, - [SVM_EXIT_INTR] = intr_interception, + [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, + [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, + [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, + [SVM_EXIT_INTR] = intr_interception, [SVM_EXIT_NMI] = nmi_interception, [SVM_EXIT_SMI] = nop_on_interception, [SVM_EXIT_INIT] = nop_on_interception, [SVM_EXIT_VINTR] = interrupt_window_interception, - /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ [SVM_EXIT_CPUID] = cpuid_interception, [SVM_EXIT_IRET] = iret_interception, [SVM_EXIT_INVD] = emulate_on_interception, @@ -2370,7 +2709,7 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { [SVM_EXIT_HLT] = halt_interception, [SVM_EXIT_INVLPG] = invlpg_interception, [SVM_EXIT_INVLPGA] = invlpga_interception, - [SVM_EXIT_IOIO] = io_interception, + [SVM_EXIT_IOIO] = io_interception, [SVM_EXIT_MSR] = msr_interception, [SVM_EXIT_TASK_SWITCH] = task_switch_interception, [SVM_EXIT_SHUTDOWN] = shutdown_interception, @@ -2393,7 +2732,12 @@ static int handle_exit(struct kvm_vcpu *vcpu) struct kvm_run *kvm_run = vcpu->run; u32 exit_code = svm->vmcb->control.exit_code; - trace_kvm_exit(exit_code, svm->vmcb->save.rip); + trace_kvm_exit(exit_code, vcpu); + + if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) + vcpu->arch.cr0 = svm->vmcb->save.cr0; + if (npt_enabled) + vcpu->arch.cr3 = svm->vmcb->save.cr3; if (unlikely(svm->nested.exit_required)) { nested_svm_vmexit(svm); @@ -2422,11 +2766,6 @@ static int handle_exit(struct kvm_vcpu *vcpu) svm_complete_interrupts(svm); - if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) - vcpu->arch.cr0 = svm->vmcb->save.cr0; - if (npt_enabled) - vcpu->arch.cr3 = svm->vmcb->save.cr3; - if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; kvm_run->fail_entry.hardware_entry_failure_reason @@ -2511,6 +2850,9 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) { struct vcpu_svm *svm = to_svm(vcpu); + if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) + return; + if (irr == -1) return; @@ -2522,8 +2864,12 @@ static int svm_nmi_allowed(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); struct vmcb *vmcb = svm->vmcb; - return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && - !(svm->vcpu.arch.hflags & HF_NMI_MASK); + int ret; + ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && + !(svm->vcpu.arch.hflags & HF_NMI_MASK); + ret = ret && gif_set(svm) && nested_svm_nmi(svm); + + return ret; } static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) @@ -2568,13 +2914,13 @@ static void enable_irq_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); - nested_svm_intr(svm); - - /* In case GIF=0 we can't rely on the CPU to tell us when - * GIF becomes 1, because that's a separate STGI/VMRUN intercept. - * The next time we get that intercept, this function will be - * called again though and we'll get the vintr intercept. */ - if (gif_set(svm)) { + /* + * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes + * 1, because that's a separate STGI/VMRUN intercept. The next time we + * get that intercept, this function will be called again though and + * we'll get the vintr intercept. + */ + if (gif_set(svm) && nested_svm_intr(svm)) { svm_set_vintr(svm); svm_inject_irq(svm, 0x0); } @@ -2588,9 +2934,10 @@ static void enable_nmi_window(struct kvm_vcpu *vcpu) == HF_NMI_MASK) return; /* IRET will cause a vm exit */ - /* Something prevents NMI from been injected. Single step over - possible problem (IRET or exception injection or interrupt - shadow) */ + /* + * Something prevents NMI from been injected. Single step over possible + * problem (IRET or exception injection or interrupt shadow) + */ svm->nmi_singlestep = true; svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); update_db_intercept(vcpu); @@ -2614,6 +2961,9 @@ static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); + if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) + return; + if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; kvm_set_cr8(vcpu, cr8); @@ -2625,6 +2975,9 @@ static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) struct vcpu_svm *svm = to_svm(vcpu); u64 cr8; + if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) + return; + cr8 = kvm_get_cr8(vcpu); svm->vmcb->control.int_ctl &= ~V_TPR_MASK; svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; @@ -2635,6 +2988,9 @@ static void svm_complete_interrupts(struct vcpu_svm *svm) u8 vector; int type; u32 exitintinfo = svm->vmcb->control.exit_int_info; + unsigned int3_injected = svm->int3_injected; + + svm->int3_injected = 0; if (svm->vcpu.arch.hflags & HF_IRET_MASK) svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); @@ -2654,18 +3010,25 @@ static void svm_complete_interrupts(struct vcpu_svm *svm) svm->vcpu.arch.nmi_injected = true; break; case SVM_EXITINTINFO_TYPE_EXEPT: - /* In case of software exception do not reinject an exception - vector, but re-execute and instruction instead */ - if (is_nested(svm)) - break; - if (kvm_exception_is_soft(vector)) + /* + * In case of software exceptions, do not reinject the vector, + * but re-execute the instruction instead. Rewind RIP first + * if we emulated INT3 before. + */ + if (kvm_exception_is_soft(vector)) { + if (vector == BP_VECTOR && int3_injected && + kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) + kvm_rip_write(&svm->vcpu, + kvm_rip_read(&svm->vcpu) - + int3_injected); break; + } if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { u32 err = svm->vmcb->control.exit_int_info_err; - kvm_queue_exception_e(&svm->vcpu, vector, err); + kvm_requeue_exception_e(&svm->vcpu, vector, err); } else - kvm_queue_exception(&svm->vcpu, vector); + kvm_requeue_exception(&svm->vcpu, vector); break; case SVM_EXITINTINFO_TYPE_INTR: kvm_queue_interrupt(&svm->vcpu, vector, false); @@ -2688,6 +3051,10 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) u16 gs_selector; u16 ldt_selector; + svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; + svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; + svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; + /* * A vmexit emulation is required before the vcpu can be executed * again. @@ -2695,10 +3062,6 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) if (unlikely(svm->nested.exit_required)) return; - svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; - svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; - svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; - pre_svm_run(svm); sync_lapic_to_cr8(vcpu); @@ -2811,6 +3174,14 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); } + + /* + * We need to handle MC intercepts here before the vcpu has a chance to + * change the physical cpu + */ + if (unlikely(svm->vmcb->control.exit_code == + SVM_EXIT_EXCP_BASE + MC_VECTOR)) + svm_handle_mce(svm); } #undef R @@ -2879,25 +3250,39 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu) { } +static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) +{ + switch (func) { + case 0x8000000A: + entry->eax = 1; /* SVM revision 1 */ + entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper + ASID emulation to nested SVM */ + entry->ecx = 0; /* Reserved */ + entry->edx = 0; /* Do not support any additional features */ + + break; + } +} + static const struct trace_print_flags svm_exit_reasons_str[] = { - { SVM_EXIT_READ_CR0, "read_cr0" }, - { SVM_EXIT_READ_CR3, "read_cr3" }, - { SVM_EXIT_READ_CR4, "read_cr4" }, - { SVM_EXIT_READ_CR8, "read_cr8" }, - { SVM_EXIT_WRITE_CR0, "write_cr0" }, - { SVM_EXIT_WRITE_CR3, "write_cr3" }, - { SVM_EXIT_WRITE_CR4, "write_cr4" }, - { SVM_EXIT_WRITE_CR8, "write_cr8" }, - { SVM_EXIT_READ_DR0, "read_dr0" }, - { SVM_EXIT_READ_DR1, "read_dr1" }, - { SVM_EXIT_READ_DR2, "read_dr2" }, - { SVM_EXIT_READ_DR3, "read_dr3" }, - { SVM_EXIT_WRITE_DR0, "write_dr0" }, - { SVM_EXIT_WRITE_DR1, "write_dr1" }, - { SVM_EXIT_WRITE_DR2, "write_dr2" }, - { SVM_EXIT_WRITE_DR3, "write_dr3" }, - { SVM_EXIT_WRITE_DR5, "write_dr5" }, - { SVM_EXIT_WRITE_DR7, "write_dr7" }, + { SVM_EXIT_READ_CR0, "read_cr0" }, + { SVM_EXIT_READ_CR3, "read_cr3" }, + { SVM_EXIT_READ_CR4, "read_cr4" }, + { SVM_EXIT_READ_CR8, "read_cr8" }, + { SVM_EXIT_WRITE_CR0, "write_cr0" }, + { SVM_EXIT_WRITE_CR3, "write_cr3" }, + { SVM_EXIT_WRITE_CR4, "write_cr4" }, + { SVM_EXIT_WRITE_CR8, "write_cr8" }, + { SVM_EXIT_READ_DR0, "read_dr0" }, + { SVM_EXIT_READ_DR1, "read_dr1" }, + { SVM_EXIT_READ_DR2, "read_dr2" }, + { SVM_EXIT_READ_DR3, "read_dr3" }, + { SVM_EXIT_WRITE_DR0, "write_dr0" }, + { SVM_EXIT_WRITE_DR1, "write_dr1" }, + { SVM_EXIT_WRITE_DR2, "write_dr2" }, + { SVM_EXIT_WRITE_DR3, "write_dr3" }, + { SVM_EXIT_WRITE_DR5, "write_dr5" }, + { SVM_EXIT_WRITE_DR7, "write_dr7" }, { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, @@ -2946,8 +3331,10 @@ static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); - update_cr0_intercept(svm); svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; + if (is_nested(svm)) + svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR; + update_cr0_intercept(svm); } static struct kvm_x86_ops svm_x86_ops = { @@ -2986,8 +3373,7 @@ static struct kvm_x86_ops svm_x86_ops = { .set_idt = svm_set_idt, .get_gdt = svm_get_gdt, .set_gdt = svm_set_gdt, - .get_dr = svm_get_dr, - .set_dr = svm_set_dr, + .set_dr7 = svm_set_dr7, .cache_reg = svm_cache_reg, .get_rflags = svm_get_rflags, .set_rflags = svm_set_rflags, @@ -3023,12 +3409,14 @@ static struct kvm_x86_ops svm_x86_ops = { .cpuid_update = svm_cpuid_update, .rdtscp_supported = svm_rdtscp_supported, + + .set_supported_cpuid = svm_set_supported_cpuid, }; static int __init svm_init(void) { return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), - THIS_MODULE); + __alignof__(struct vcpu_svm), THIS_MODULE); } static void __exit svm_exit(void) diff --git a/arch/x86/kvm/timer.c b/arch/x86/kvm/timer.c index eea40439066c..4ddadb1a5ffe 100644 --- a/arch/x86/kvm/timer.c +++ b/arch/x86/kvm/timer.c @@ -12,7 +12,8 @@ static int __kvm_timer_fn(struct kvm_vcpu *vcpu, struct kvm_timer *ktimer) /* * There is a race window between reading and incrementing, but we do * not care about potentially loosing timer events in the !reinject - * case anyway. + * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked + * in vcpu_enter_guest. */ if (ktimer->reinject || !atomic_read(&ktimer->pending)) { atomic_inc(&ktimer->pending); diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 6ad30a29f044..a6544b8e7c0f 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -5,8 +5,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm -#define TRACE_INCLUDE_PATH arch/x86/kvm -#define TRACE_INCLUDE_FILE trace /* * Tracepoint for guest mode entry. @@ -184,8 +182,8 @@ TRACE_EVENT(kvm_apic, * Tracepoint for kvm guest exit: */ TRACE_EVENT(kvm_exit, - TP_PROTO(unsigned int exit_reason, unsigned long guest_rip), - TP_ARGS(exit_reason, guest_rip), + TP_PROTO(unsigned int exit_reason, struct kvm_vcpu *vcpu), + TP_ARGS(exit_reason, vcpu), TP_STRUCT__entry( __field( unsigned int, exit_reason ) @@ -194,7 +192,7 @@ TRACE_EVENT(kvm_exit, TP_fast_assign( __entry->exit_reason = exit_reason; - __entry->guest_rip = guest_rip; + __entry->guest_rip = kvm_rip_read(vcpu); ), TP_printk("reason %s rip 0x%lx", @@ -221,6 +219,38 @@ TRACE_EVENT(kvm_inj_virq, TP_printk("irq %u", __entry->irq) ); +#define EXS(x) { x##_VECTOR, "#" #x } + +#define kvm_trace_sym_exc \ + EXS(DE), EXS(DB), EXS(BP), EXS(OF), EXS(BR), EXS(UD), EXS(NM), \ + EXS(DF), EXS(TS), EXS(NP), EXS(SS), EXS(GP), EXS(PF), \ + EXS(MF), EXS(MC) + +/* + * Tracepoint for kvm interrupt injection: + */ +TRACE_EVENT(kvm_inj_exception, + TP_PROTO(unsigned exception, bool has_error, unsigned error_code), + TP_ARGS(exception, has_error, error_code), + + TP_STRUCT__entry( + __field( u8, exception ) + __field( u8, has_error ) + __field( u32, error_code ) + ), + + TP_fast_assign( + __entry->exception = exception; + __entry->has_error = has_error; + __entry->error_code = error_code; + ), + + TP_printk("%s (0x%x)", + __print_symbolic(__entry->exception, kvm_trace_sym_exc), + /* FIXME: don't print error_code if not present */ + __entry->has_error ? __entry->error_code : 0) +); + /* * Tracepoint for page fault. */ @@ -413,12 +443,34 @@ TRACE_EVENT(kvm_nested_vmrun, ), TP_printk("rip: 0x%016llx vmcb: 0x%016llx nrip: 0x%016llx int_ctl: 0x%08x " - "event_inj: 0x%08x npt: %s\n", + "event_inj: 0x%08x npt: %s", __entry->rip, __entry->vmcb, __entry->nested_rip, __entry->int_ctl, __entry->event_inj, __entry->npt ? "on" : "off") ); +TRACE_EVENT(kvm_nested_intercepts, + TP_PROTO(__u16 cr_read, __u16 cr_write, __u32 exceptions, __u64 intercept), + TP_ARGS(cr_read, cr_write, exceptions, intercept), + + TP_STRUCT__entry( + __field( __u16, cr_read ) + __field( __u16, cr_write ) + __field( __u32, exceptions ) + __field( __u64, intercept ) + ), + + TP_fast_assign( + __entry->cr_read = cr_read; + __entry->cr_write = cr_write; + __entry->exceptions = exceptions; + __entry->intercept = intercept; + ), + + TP_printk("cr_read: %04x cr_write: %04x excp: %08x intercept: %016llx", + __entry->cr_read, __entry->cr_write, __entry->exceptions, + __entry->intercept) +); /* * Tracepoint for #VMEXIT while nested */ @@ -447,7 +499,7 @@ TRACE_EVENT(kvm_nested_vmexit, __entry->exit_int_info_err = exit_int_info_err; ), TP_printk("rip: 0x%016llx reason: %s ext_inf1: 0x%016llx " - "ext_inf2: 0x%016llx ext_int: 0x%08x ext_int_err: 0x%08x\n", + "ext_inf2: 0x%016llx ext_int: 0x%08x ext_int_err: 0x%08x", __entry->rip, ftrace_print_symbols_seq(p, __entry->exit_code, kvm_x86_ops->exit_reasons_str), @@ -482,7 +534,7 @@ TRACE_EVENT(kvm_nested_vmexit_inject, ), TP_printk("reason: %s ext_inf1: 0x%016llx " - "ext_inf2: 0x%016llx ext_int: 0x%08x ext_int_err: 0x%08x\n", + "ext_inf2: 0x%016llx ext_int: 0x%08x ext_int_err: 0x%08x", ftrace_print_symbols_seq(p, __entry->exit_code, kvm_x86_ops->exit_reasons_str), __entry->exit_info1, __entry->exit_info2, @@ -504,7 +556,7 @@ TRACE_EVENT(kvm_nested_intr_vmexit, __entry->rip = rip ), - TP_printk("rip: 0x%016llx\n", __entry->rip) + TP_printk("rip: 0x%016llx", __entry->rip) ); /* @@ -526,7 +578,7 @@ TRACE_EVENT(kvm_invlpga, __entry->address = address; ), - TP_printk("rip: 0x%016llx asid: %d address: 0x%016llx\n", + TP_printk("rip: 0x%016llx asid: %d address: 0x%016llx", __entry->rip, __entry->asid, __entry->address) ); @@ -547,11 +599,102 @@ TRACE_EVENT(kvm_skinit, __entry->slb = slb; ), - TP_printk("rip: 0x%016llx slb: 0x%08x\n", + TP_printk("rip: 0x%016llx slb: 0x%08x", __entry->rip, __entry->slb) ); +#define __print_insn(insn, ilen) ({ \ + int i; \ + const char *ret = p->buffer + p->len; \ + \ + for (i = 0; i < ilen; ++i) \ + trace_seq_printf(p, " %02x", insn[i]); \ + trace_seq_printf(p, "%c", 0); \ + ret; \ + }) + +#define KVM_EMUL_INSN_F_CR0_PE (1 << 0) +#define KVM_EMUL_INSN_F_EFL_VM (1 << 1) +#define KVM_EMUL_INSN_F_CS_D (1 << 2) +#define KVM_EMUL_INSN_F_CS_L (1 << 3) + +#define kvm_trace_symbol_emul_flags \ + { 0, "real" }, \ + { KVM_EMUL_INSN_F_CR0_PE \ + | KVM_EMUL_INSN_F_EFL_VM, "vm16" }, \ + { KVM_EMUL_INSN_F_CR0_PE, "prot16" }, \ + { KVM_EMUL_INSN_F_CR0_PE \ + | KVM_EMUL_INSN_F_CS_D, "prot32" }, \ + { KVM_EMUL_INSN_F_CR0_PE \ + | KVM_EMUL_INSN_F_CS_L, "prot64" } + +#define kei_decode_mode(mode) ({ \ + u8 flags = 0xff; \ + switch (mode) { \ + case X86EMUL_MODE_REAL: \ + flags = 0; \ + break; \ + case X86EMUL_MODE_VM86: \ + flags = KVM_EMUL_INSN_F_EFL_VM; \ + break; \ + case X86EMUL_MODE_PROT16: \ + flags = KVM_EMUL_INSN_F_CR0_PE; \ + break; \ + case X86EMUL_MODE_PROT32: \ + flags = KVM_EMUL_INSN_F_CR0_PE \ + | KVM_EMUL_INSN_F_CS_D; \ + break; \ + case X86EMUL_MODE_PROT64: \ + flags = KVM_EMUL_INSN_F_CR0_PE \ + | KVM_EMUL_INSN_F_CS_L; \ + break; \ + } \ + flags; \ + }) + +TRACE_EVENT(kvm_emulate_insn, + TP_PROTO(struct kvm_vcpu *vcpu, __u8 failed), + TP_ARGS(vcpu, failed), + + TP_STRUCT__entry( + __field( __u64, rip ) + __field( __u32, csbase ) + __field( __u8, len ) + __array( __u8, insn, 15 ) + __field( __u8, flags ) + __field( __u8, failed ) + ), + + TP_fast_assign( + __entry->rip = vcpu->arch.emulate_ctxt.decode.fetch.start; + __entry->csbase = kvm_x86_ops->get_segment_base(vcpu, VCPU_SREG_CS); + __entry->len = vcpu->arch.emulate_ctxt.decode.eip + - vcpu->arch.emulate_ctxt.decode.fetch.start; + memcpy(__entry->insn, + vcpu->arch.emulate_ctxt.decode.fetch.data, + 15); + __entry->flags = kei_decode_mode(vcpu->arch.emulate_ctxt.mode); + __entry->failed = failed; + ), + + TP_printk("%x:%llx:%s (%s)%s", + __entry->csbase, __entry->rip, + __print_insn(__entry->insn, __entry->len), + __print_symbolic(__entry->flags, + kvm_trace_symbol_emul_flags), + __entry->failed ? " failed" : "" + ) + ); + +#define trace_kvm_emulate_insn_start(vcpu) trace_kvm_emulate_insn(vcpu, 0) +#define trace_kvm_emulate_insn_failed(vcpu) trace_kvm_emulate_insn(vcpu, 1) + #endif /* _TRACE_KVM_H */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH arch/x86/kvm +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace + /* This part must be outside protection */ #include <trace/define_trace.h> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index edca080407a5..859a01a07dbf 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -27,6 +27,7 @@ #include <linux/moduleparam.h> #include <linux/ftrace_event.h> #include <linux/slab.h> +#include <linux/tboot.h> #include "kvm_cache_regs.h" #include "x86.h" @@ -98,6 +99,8 @@ module_param(ple_gap, int, S_IRUGO); static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; module_param(ple_window, int, S_IRUGO); +#define NR_AUTOLOAD_MSRS 1 + struct vmcs { u32 revision_id; u32 abort; @@ -125,6 +128,11 @@ struct vcpu_vmx { u64 msr_guest_kernel_gs_base; #endif struct vmcs *vmcs; + struct msr_autoload { + unsigned nr; + struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; + struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; + } msr_autoload; struct { int loaded; u16 fs_sel, gs_sel, ldt_sel; @@ -234,56 +242,56 @@ static const u32 vmx_msr_index[] = { }; #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) -static inline int is_page_fault(u32 intr_info) +static inline bool is_page_fault(u32 intr_info) { return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | INTR_INFO_VALID_MASK)) == (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); } -static inline int is_no_device(u32 intr_info) +static inline bool is_no_device(u32 intr_info) { return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | INTR_INFO_VALID_MASK)) == (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); } -static inline int is_invalid_opcode(u32 intr_info) +static inline bool is_invalid_opcode(u32 intr_info) { return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | INTR_INFO_VALID_MASK)) == (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); } -static inline int is_external_interrupt(u32 intr_info) +static inline bool is_external_interrupt(u32 intr_info) { return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); } -static inline int is_machine_check(u32 intr_info) +static inline bool is_machine_check(u32 intr_info) { return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | INTR_INFO_VALID_MASK)) == (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); } -static inline int cpu_has_vmx_msr_bitmap(void) +static inline bool cpu_has_vmx_msr_bitmap(void) { return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; } -static inline int cpu_has_vmx_tpr_shadow(void) +static inline bool cpu_has_vmx_tpr_shadow(void) { return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; } -static inline int vm_need_tpr_shadow(struct kvm *kvm) +static inline bool vm_need_tpr_shadow(struct kvm *kvm) { return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); } -static inline int cpu_has_secondary_exec_ctrls(void) +static inline bool cpu_has_secondary_exec_ctrls(void) { return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; @@ -303,80 +311,80 @@ static inline bool cpu_has_vmx_flexpriority(void) static inline bool cpu_has_vmx_ept_execute_only(void) { - return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT); + return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; } static inline bool cpu_has_vmx_eptp_uncacheable(void) { - return !!(vmx_capability.ept & VMX_EPTP_UC_BIT); + return vmx_capability.ept & VMX_EPTP_UC_BIT; } static inline bool cpu_has_vmx_eptp_writeback(void) { - return !!(vmx_capability.ept & VMX_EPTP_WB_BIT); + return vmx_capability.ept & VMX_EPTP_WB_BIT; } static inline bool cpu_has_vmx_ept_2m_page(void) { - return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT); + return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; } static inline bool cpu_has_vmx_ept_1g_page(void) { - return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT); + return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; } -static inline int cpu_has_vmx_invept_individual_addr(void) +static inline bool cpu_has_vmx_invept_individual_addr(void) { - return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT); + return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; } -static inline int cpu_has_vmx_invept_context(void) +static inline bool cpu_has_vmx_invept_context(void) { - return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT); + return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; } -static inline int cpu_has_vmx_invept_global(void) +static inline bool cpu_has_vmx_invept_global(void) { - return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT); + return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; } -static inline int cpu_has_vmx_ept(void) +static inline bool cpu_has_vmx_ept(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_EPT; } -static inline int cpu_has_vmx_unrestricted_guest(void) +static inline bool cpu_has_vmx_unrestricted_guest(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_UNRESTRICTED_GUEST; } -static inline int cpu_has_vmx_ple(void) +static inline bool cpu_has_vmx_ple(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PAUSE_LOOP_EXITING; } -static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) +static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) { return flexpriority_enabled && irqchip_in_kernel(kvm); } -static inline int cpu_has_vmx_vpid(void) +static inline bool cpu_has_vmx_vpid(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_VPID; } -static inline int cpu_has_vmx_rdtscp(void) +static inline bool cpu_has_vmx_rdtscp(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_RDTSCP; } -static inline int cpu_has_virtual_nmis(void) +static inline bool cpu_has_virtual_nmis(void) { return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; } @@ -595,16 +603,56 @@ static void update_exception_bitmap(struct kvm_vcpu *vcpu) vmcs_write32(EXCEPTION_BITMAP, eb); } +static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) +{ + unsigned i; + struct msr_autoload *m = &vmx->msr_autoload; + + for (i = 0; i < m->nr; ++i) + if (m->guest[i].index == msr) + break; + + if (i == m->nr) + return; + --m->nr; + m->guest[i] = m->guest[m->nr]; + m->host[i] = m->host[m->nr]; + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); + vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); +} + +static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, + u64 guest_val, u64 host_val) +{ + unsigned i; + struct msr_autoload *m = &vmx->msr_autoload; + + for (i = 0; i < m->nr; ++i) + if (m->guest[i].index == msr) + break; + + if (i == m->nr) { + ++m->nr; + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); + vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); + } + + m->guest[i].index = msr; + m->guest[i].value = guest_val; + m->host[i].index = msr; + m->host[i].value = host_val; +} + static void reload_tss(void) { /* * VT restores TR but not its size. Useless. */ - struct descriptor_table gdt; + struct desc_ptr gdt; struct desc_struct *descs; - kvm_get_gdt(&gdt); - descs = (void *)gdt.base; + native_store_gdt(&gdt); + descs = (void *)gdt.address; descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ load_TR_desc(); } @@ -631,9 +679,57 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) guest_efer |= host_efer & ignore_bits; vmx->guest_msrs[efer_offset].data = guest_efer; vmx->guest_msrs[efer_offset].mask = ~ignore_bits; + + clear_atomic_switch_msr(vmx, MSR_EFER); + /* On ept, can't emulate nx, and must switch nx atomically */ + if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { + guest_efer = vmx->vcpu.arch.efer; + if (!(guest_efer & EFER_LMA)) + guest_efer &= ~EFER_LME; + add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); + return false; + } + return true; } +static unsigned long segment_base(u16 selector) +{ + struct desc_ptr gdt; + struct desc_struct *d; + unsigned long table_base; + unsigned long v; + + if (!(selector & ~3)) + return 0; + + native_store_gdt(&gdt); + table_base = gdt.address; + + if (selector & 4) { /* from ldt */ + u16 ldt_selector = kvm_read_ldt(); + + if (!(ldt_selector & ~3)) + return 0; + + table_base = segment_base(ldt_selector); + } + d = (struct desc_struct *)(table_base + (selector & ~7)); + v = get_desc_base(d); +#ifdef CONFIG_X86_64 + if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) + v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; +#endif + return v; +} + +static inline unsigned long kvm_read_tr_base(void) +{ + u16 tr; + asm("str %0" : "=g"(tr)); + return segment_base(tr); +} + static void vmx_save_host_state(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); @@ -758,7 +854,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) } if (vcpu->cpu != cpu) { - struct descriptor_table dt; + struct desc_ptr dt; unsigned long sysenter_esp; vcpu->cpu = cpu; @@ -767,8 +863,8 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) * processors. */ vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ - kvm_get_gdt(&dt); - vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ + native_store_gdt(&dt); + vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */ rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ @@ -846,9 +942,9 @@ static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) int ret = 0; if (interruptibility & GUEST_INTR_STATE_STI) - ret |= X86_SHADOW_INT_STI; + ret |= KVM_X86_SHADOW_INT_STI; if (interruptibility & GUEST_INTR_STATE_MOV_SS) - ret |= X86_SHADOW_INT_MOV_SS; + ret |= KVM_X86_SHADOW_INT_MOV_SS; return ret & mask; } @@ -860,9 +956,9 @@ static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); - if (mask & X86_SHADOW_INT_MOV_SS) + if (mask & KVM_X86_SHADOW_INT_MOV_SS) interruptibility |= GUEST_INTR_STATE_MOV_SS; - if (mask & X86_SHADOW_INT_STI) + else if (mask & KVM_X86_SHADOW_INT_STI) interruptibility |= GUEST_INTR_STATE_STI; if ((interruptibility != interruptibility_old)) @@ -882,7 +978,8 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu) } static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, - bool has_error_code, u32 error_code) + bool has_error_code, u32 error_code, + bool reinject) { struct vcpu_vmx *vmx = to_vmx(vcpu); u32 intr_info = nr | INTR_INFO_VALID_MASK; @@ -1176,9 +1273,16 @@ static __init int vmx_disabled_by_bios(void) u64 msr; rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); - return (msr & (FEATURE_CONTROL_LOCKED | - FEATURE_CONTROL_VMXON_ENABLED)) - == FEATURE_CONTROL_LOCKED; + if (msr & FEATURE_CONTROL_LOCKED) { + if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) + && tboot_enabled()) + return 1; + if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) + && !tboot_enabled()) + return 1; + } + + return 0; /* locked but not enabled */ } @@ -1186,21 +1290,23 @@ static int hardware_enable(void *garbage) { int cpu = raw_smp_processor_id(); u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); - u64 old; + u64 old, test_bits; if (read_cr4() & X86_CR4_VMXE) return -EBUSY; INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); rdmsrl(MSR_IA32_FEATURE_CONTROL, old); - if ((old & (FEATURE_CONTROL_LOCKED | - FEATURE_CONTROL_VMXON_ENABLED)) - != (FEATURE_CONTROL_LOCKED | - FEATURE_CONTROL_VMXON_ENABLED)) + + test_bits = FEATURE_CONTROL_LOCKED; + test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + if (tboot_enabled()) + test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; + + if ((old & test_bits) != test_bits) { /* enable and lock */ - wrmsrl(MSR_IA32_FEATURE_CONTROL, old | - FEATURE_CONTROL_LOCKED | - FEATURE_CONTROL_VMXON_ENABLED); + wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); + } write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) @@ -1521,7 +1627,7 @@ static gva_t rmode_tss_base(struct kvm *kvm) struct kvm_memslots *slots; gfn_t base_gfn; - slots = rcu_dereference(kvm->memslots); + slots = kvm_memslots(kvm); base_gfn = kvm->memslots->memslots[0].base_gfn + kvm->memslots->memslots[0].npages - 3; return base_gfn << PAGE_SHIFT; @@ -1649,6 +1755,7 @@ static void exit_lmode(struct kvm_vcpu *vcpu) vmcs_write32(VM_ENTRY_CONTROLS, vmcs_read32(VM_ENTRY_CONTROLS) & ~VM_ENTRY_IA32E_MODE); + vmx_set_efer(vcpu, vcpu->arch.efer); } #endif @@ -1934,28 +2041,28 @@ static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) *l = (ar >> 13) & 1; } -static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { - dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); - dt->base = vmcs_readl(GUEST_IDTR_BASE); + dt->size = vmcs_read32(GUEST_IDTR_LIMIT); + dt->address = vmcs_readl(GUEST_IDTR_BASE); } -static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { - vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); - vmcs_writel(GUEST_IDTR_BASE, dt->base); + vmcs_write32(GUEST_IDTR_LIMIT, dt->size); + vmcs_writel(GUEST_IDTR_BASE, dt->address); } -static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { - dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); - dt->base = vmcs_readl(GUEST_GDTR_BASE); + dt->size = vmcs_read32(GUEST_GDTR_LIMIT); + dt->address = vmcs_readl(GUEST_GDTR_BASE); } -static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) +static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) { - vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); - vmcs_writel(GUEST_GDTR_BASE, dt->base); + vmcs_write32(GUEST_GDTR_LIMIT, dt->size); + vmcs_writel(GUEST_GDTR_BASE, dt->address); } static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) @@ -2296,6 +2403,16 @@ static void allocate_vpid(struct vcpu_vmx *vmx) spin_unlock(&vmx_vpid_lock); } +static void free_vpid(struct vcpu_vmx *vmx) +{ + if (!enable_vpid) + return; + spin_lock(&vmx_vpid_lock); + if (vmx->vpid != 0) + __clear_bit(vmx->vpid, vmx_vpid_bitmap); + spin_unlock(&vmx_vpid_lock); +} + static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) { int f = sizeof(unsigned long); @@ -2334,7 +2451,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) u32 junk; u64 host_pat, tsc_this, tsc_base; unsigned long a; - struct descriptor_table dt; + struct desc_ptr dt; int i; unsigned long kvm_vmx_return; u32 exec_control; @@ -2415,14 +2532,16 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ - kvm_get_idt(&dt); - vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ + native_store_idt(&dt); + vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); + vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); + vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); @@ -2947,22 +3066,20 @@ static int handle_io(struct kvm_vcpu *vcpu) int size, in, string; unsigned port; - ++vcpu->stat.io_exits; exit_qualification = vmcs_readl(EXIT_QUALIFICATION); string = (exit_qualification & 16) != 0; + in = (exit_qualification & 8) != 0; - if (string) { - if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO) - return 0; - return 1; - } + ++vcpu->stat.io_exits; - size = (exit_qualification & 7) + 1; - in = (exit_qualification & 8) != 0; - port = exit_qualification >> 16; + if (string || in) + return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO); + port = exit_qualification >> 16; + size = (exit_qualification & 7) + 1; skip_emulated_instruction(vcpu); - return kvm_emulate_pio(vcpu, in, size, port); + + return kvm_fast_pio_out(vcpu, size, port); } static void @@ -3053,19 +3170,9 @@ static int handle_cr(struct kvm_vcpu *vcpu) return 0; } -static int check_dr_alias(struct kvm_vcpu *vcpu) -{ - if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { - kvm_queue_exception(vcpu, UD_VECTOR); - return -1; - } - return 0; -} - static int handle_dr(struct kvm_vcpu *vcpu) { unsigned long exit_qualification; - unsigned long val; int dr, reg; /* Do not handle if the CPL > 0, will trigger GP on re-entry */ @@ -3100,67 +3207,20 @@ static int handle_dr(struct kvm_vcpu *vcpu) dr = exit_qualification & DEBUG_REG_ACCESS_NUM; reg = DEBUG_REG_ACCESS_REG(exit_qualification); if (exit_qualification & TYPE_MOV_FROM_DR) { - switch (dr) { - case 0 ... 3: - val = vcpu->arch.db[dr]; - break; - case 4: - if (check_dr_alias(vcpu) < 0) - return 1; - /* fall through */ - case 6: - val = vcpu->arch.dr6; - break; - case 5: - if (check_dr_alias(vcpu) < 0) - return 1; - /* fall through */ - default: /* 7 */ - val = vcpu->arch.dr7; - break; - } - kvm_register_write(vcpu, reg, val); - } else { - val = vcpu->arch.regs[reg]; - switch (dr) { - case 0 ... 3: - vcpu->arch.db[dr] = val; - if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) - vcpu->arch.eff_db[dr] = val; - break; - case 4: - if (check_dr_alias(vcpu) < 0) - return 1; - /* fall through */ - case 6: - if (val & 0xffffffff00000000ULL) { - kvm_inject_gp(vcpu, 0); - return 1; - } - vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; - break; - case 5: - if (check_dr_alias(vcpu) < 0) - return 1; - /* fall through */ - default: /* 7 */ - if (val & 0xffffffff00000000ULL) { - kvm_inject_gp(vcpu, 0); - return 1; - } - vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; - if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { - vmcs_writel(GUEST_DR7, vcpu->arch.dr7); - vcpu->arch.switch_db_regs = - (val & DR7_BP_EN_MASK); - } - break; - } - } + unsigned long val; + if (!kvm_get_dr(vcpu, dr, &val)) + kvm_register_write(vcpu, reg, val); + } else + kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]); skip_emulated_instruction(vcpu); return 1; } +static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) +{ + vmcs_writel(GUEST_DR7, val); +} + static int handle_cpuid(struct kvm_vcpu *vcpu) { kvm_emulate_cpuid(vcpu); @@ -3292,6 +3352,8 @@ static int handle_task_switch(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); unsigned long exit_qualification; + bool has_error_code = false; + u32 error_code = 0; u16 tss_selector; int reason, type, idt_v; @@ -3314,6 +3376,13 @@ static int handle_task_switch(struct kvm_vcpu *vcpu) kvm_clear_interrupt_queue(vcpu); break; case INTR_TYPE_HARD_EXCEPTION: + if (vmx->idt_vectoring_info & + VECTORING_INFO_DELIVER_CODE_MASK) { + has_error_code = true; + error_code = + vmcs_read32(IDT_VECTORING_ERROR_CODE); + } + /* fall through */ case INTR_TYPE_SOFT_EXCEPTION: kvm_clear_exception_queue(vcpu); break; @@ -3328,8 +3397,13 @@ static int handle_task_switch(struct kvm_vcpu *vcpu) type != INTR_TYPE_NMI_INTR)) skip_emulated_instruction(vcpu); - if (!kvm_task_switch(vcpu, tss_selector, reason)) + if (kvm_task_switch(vcpu, tss_selector, reason, + has_error_code, error_code) == EMULATE_FAIL) { + vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; + vcpu->run->internal.ndata = 0; return 0; + } /* clear all local breakpoint enable flags */ vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); @@ -3574,7 +3648,7 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu) u32 exit_reason = vmx->exit_reason; u32 vectoring_info = vmx->idt_vectoring_info; - trace_kvm_exit(exit_reason, kvm_rip_read(vcpu)); + trace_kvm_exit(exit_reason, vcpu); /* If guest state is invalid, start emulating */ if (vmx->emulation_required && emulate_invalid_guest_state) @@ -3923,10 +3997,7 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); - spin_lock(&vmx_vpid_lock); - if (vmx->vpid != 0) - __clear_bit(vmx->vpid, vmx_vpid_bitmap); - spin_unlock(&vmx_vpid_lock); + free_vpid(vmx); vmx_free_vmcs(vcpu); kfree(vmx->guest_msrs); kvm_vcpu_uninit(vcpu); @@ -3988,6 +4059,7 @@ free_msrs: uninit_vcpu: kvm_vcpu_uninit(&vmx->vcpu); free_vcpu: + free_vpid(vmx); kmem_cache_free(kvm_vcpu_cache, vmx); return ERR_PTR(err); } @@ -4118,6 +4190,10 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu) } } +static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) +{ +} + static struct kvm_x86_ops vmx_x86_ops = { .cpu_has_kvm_support = cpu_has_kvm_support, .disabled_by_bios = vmx_disabled_by_bios, @@ -4154,6 +4230,7 @@ static struct kvm_x86_ops vmx_x86_ops = { .set_idt = vmx_set_idt, .get_gdt = vmx_get_gdt, .set_gdt = vmx_set_gdt, + .set_dr7 = vmx_set_dr7, .cache_reg = vmx_cache_reg, .get_rflags = vmx_get_rflags, .set_rflags = vmx_set_rflags, @@ -4189,6 +4266,8 @@ static struct kvm_x86_ops vmx_x86_ops = { .cpuid_update = vmx_cpuid_update, .rdtscp_supported = vmx_rdtscp_supported, + + .set_supported_cpuid = vmx_set_supported_cpuid, }; static int __init vmx_init(void) @@ -4236,7 +4315,8 @@ static int __init vmx_init(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); + r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), + __alignof__(struct vcpu_vmx), THIS_MODULE); if (r) goto out3; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index dd9bc8fb81ab..05d571f6f196 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -42,7 +42,7 @@ #include <linux/slab.h> #include <linux/perf_event.h> #include <trace/events/kvm.h> -#undef TRACE_INCLUDE_FILE + #define CREATE_TRACE_POINTS #include "trace.h" @@ -224,34 +224,6 @@ static void drop_user_return_notifiers(void *ignore) kvm_on_user_return(&smsr->urn); } -unsigned long segment_base(u16 selector) -{ - struct descriptor_table gdt; - struct desc_struct *d; - unsigned long table_base; - unsigned long v; - - if (selector == 0) - return 0; - - kvm_get_gdt(&gdt); - table_base = gdt.base; - - if (selector & 4) { /* from ldt */ - u16 ldt_selector = kvm_read_ldt(); - - table_base = segment_base(ldt_selector); - } - d = (struct desc_struct *)(table_base + (selector & ~7)); - v = get_desc_base(d); -#ifdef CONFIG_X86_64 - if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) - v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; -#endif - return v; -} -EXPORT_SYMBOL_GPL(segment_base); - u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) { if (irqchip_in_kernel(vcpu->kvm)) @@ -293,7 +265,8 @@ static int exception_class(int vector) } static void kvm_multiple_exception(struct kvm_vcpu *vcpu, - unsigned nr, bool has_error, u32 error_code) + unsigned nr, bool has_error, u32 error_code, + bool reinject) { u32 prev_nr; int class1, class2; @@ -304,6 +277,7 @@ static void kvm_multiple_exception(struct kvm_vcpu *vcpu, vcpu->arch.exception.has_error_code = has_error; vcpu->arch.exception.nr = nr; vcpu->arch.exception.error_code = error_code; + vcpu->arch.exception.reinject = reinject; return; } @@ -332,10 +306,16 @@ static void kvm_multiple_exception(struct kvm_vcpu *vcpu, void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) { - kvm_multiple_exception(vcpu, nr, false, 0); + kvm_multiple_exception(vcpu, nr, false, 0, false); } EXPORT_SYMBOL_GPL(kvm_queue_exception); +void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) +{ + kvm_multiple_exception(vcpu, nr, false, 0, true); +} +EXPORT_SYMBOL_GPL(kvm_requeue_exception); + void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, u32 error_code) { @@ -352,10 +332,16 @@ EXPORT_SYMBOL_GPL(kvm_inject_nmi); void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) { - kvm_multiple_exception(vcpu, nr, true, error_code); + kvm_multiple_exception(vcpu, nr, true, error_code, false); } EXPORT_SYMBOL_GPL(kvm_queue_exception_e); +void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) +{ + kvm_multiple_exception(vcpu, nr, true, error_code, true); +} +EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); + /* * Checks if cpl <= required_cpl; if true, return true. Otherwise queue * a #GP and return false. @@ -476,7 +462,6 @@ void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) } kvm_x86_ops->set_cr0(vcpu, cr0); - vcpu->arch.cr0 = cr0; kvm_mmu_reset_context(vcpu); return; @@ -485,7 +470,7 @@ EXPORT_SYMBOL_GPL(kvm_set_cr0); void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) { - kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f)); + kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); } EXPORT_SYMBOL_GPL(kvm_lmsw); @@ -517,7 +502,6 @@ void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) } kvm_x86_ops->set_cr4(vcpu, cr4); vcpu->arch.cr4 = cr4; - vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; kvm_mmu_reset_context(vcpu); } EXPORT_SYMBOL_GPL(kvm_set_cr4); @@ -592,6 +576,80 @@ unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) } EXPORT_SYMBOL_GPL(kvm_get_cr8); +int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) +{ + switch (dr) { + case 0 ... 3: + vcpu->arch.db[dr] = val; + if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) + vcpu->arch.eff_db[dr] = val; + break; + case 4: + if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + /* fall through */ + case 6: + if (val & 0xffffffff00000000ULL) { + kvm_inject_gp(vcpu, 0); + return 1; + } + vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; + break; + case 5: + if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + /* fall through */ + default: /* 7 */ + if (val & 0xffffffff00000000ULL) { + kvm_inject_gp(vcpu, 0); + return 1; + } + vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; + if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { + kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); + vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); + } + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(kvm_set_dr); + +int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) +{ + switch (dr) { + case 0 ... 3: + *val = vcpu->arch.db[dr]; + break; + case 4: + if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + /* fall through */ + case 6: + *val = vcpu->arch.dr6; + break; + case 5: + if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + /* fall through */ + default: /* 7 */ + *val = vcpu->arch.dr7; + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(kvm_get_dr); + static inline u32 bit(int bitno) { return 1 << (bitno & 31); @@ -606,9 +664,10 @@ static inline u32 bit(int bitno) * kvm-specific. Those are put in the beginning of the list. */ -#define KVM_SAVE_MSRS_BEGIN 5 +#define KVM_SAVE_MSRS_BEGIN 7 static u32 msrs_to_save[] = { MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, + MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, HV_X64_MSR_APIC_ASSIST_PAGE, MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, @@ -625,48 +684,42 @@ static u32 emulated_msrs[] = { MSR_IA32_MISC_ENABLE, }; -static void set_efer(struct kvm_vcpu *vcpu, u64 efer) +static int set_efer(struct kvm_vcpu *vcpu, u64 efer) { - if (efer & efer_reserved_bits) { - kvm_inject_gp(vcpu, 0); - return; - } + if (efer & efer_reserved_bits) + return 1; if (is_paging(vcpu) - && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) { - kvm_inject_gp(vcpu, 0); - return; - } + && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) + return 1; if (efer & EFER_FFXSR) { struct kvm_cpuid_entry2 *feat; feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); - if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { - kvm_inject_gp(vcpu, 0); - return; - } + if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) + return 1; } if (efer & EFER_SVME) { struct kvm_cpuid_entry2 *feat; feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); - if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { - kvm_inject_gp(vcpu, 0); - return; - } + if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) + return 1; } - kvm_x86_ops->set_efer(vcpu, efer); - efer &= ~EFER_LMA; efer |= vcpu->arch.efer & EFER_LMA; + kvm_x86_ops->set_efer(vcpu, efer); + vcpu->arch.efer = efer; vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; kvm_mmu_reset_context(vcpu); + + return 0; } void kvm_enable_efer_bits(u64 mask) @@ -696,14 +749,22 @@ static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) { - static int version; + int version; + int r; struct pvclock_wall_clock wc; struct timespec boot; if (!wall_clock) return; - version++; + r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); + if (r) + return; + + if (version & 1) + ++version; /* first time write, random junk */ + + ++version; kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); @@ -796,6 +857,8 @@ static void kvm_write_guest_time(struct kvm_vcpu *v) vcpu->hv_clock.system_time = ts.tv_nsec + (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset; + vcpu->hv_clock.flags = 0; + /* * The interface expects us to write an even number signaling that the * update is finished. Since the guest won't see the intermediate @@ -1087,10 +1150,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) { switch (msr) { case MSR_EFER: - set_efer(vcpu, data); - break; + return set_efer(vcpu, data); case MSR_K7_HWCR: data &= ~(u64)0x40; /* ignore flush filter disable */ + data &= ~(u64)0x100; /* ignore ignne emulation enable */ if (data != 0) { pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", data); @@ -1133,10 +1196,12 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) case MSR_IA32_MISC_ENABLE: vcpu->arch.ia32_misc_enable_msr = data; break; + case MSR_KVM_WALL_CLOCK_NEW: case MSR_KVM_WALL_CLOCK: vcpu->kvm->arch.wall_clock = data; kvm_write_wall_clock(vcpu->kvm, data); break; + case MSR_KVM_SYSTEM_TIME_NEW: case MSR_KVM_SYSTEM_TIME: { if (vcpu->arch.time_page) { kvm_release_page_dirty(vcpu->arch.time_page); @@ -1408,9 +1473,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) data = vcpu->arch.efer; break; case MSR_KVM_WALL_CLOCK: + case MSR_KVM_WALL_CLOCK_NEW: data = vcpu->kvm->arch.wall_clock; break; case MSR_KVM_SYSTEM_TIME: + case MSR_KVM_SYSTEM_TIME_NEW: data = vcpu->arch.time; break; case MSR_IA32_P5_MC_ADDR: @@ -1549,6 +1616,7 @@ int kvm_dev_ioctl_check_extension(long ext) case KVM_CAP_HYPERV_VAPIC: case KVM_CAP_HYPERV_SPIN: case KVM_CAP_PCI_SEGMENT: + case KVM_CAP_DEBUGREGS: case KVM_CAP_X86_ROBUST_SINGLESTEP: r = 1; break; @@ -1769,6 +1837,7 @@ static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, { int r; + vcpu_load(vcpu); r = -E2BIG; if (cpuid->nent < vcpu->arch.cpuid_nent) goto out; @@ -1780,6 +1849,7 @@ static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, out: cpuid->nent = vcpu->arch.cpuid_nent; + vcpu_put(vcpu); return r; } @@ -1910,6 +1980,24 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, } break; } + case KVM_CPUID_SIGNATURE: { + char signature[12] = "KVMKVMKVM\0\0"; + u32 *sigptr = (u32 *)signature; + entry->eax = 0; + entry->ebx = sigptr[0]; + entry->ecx = sigptr[1]; + entry->edx = sigptr[2]; + break; + } + case KVM_CPUID_FEATURES: + entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | + (1 << KVM_FEATURE_NOP_IO_DELAY) | + (1 << KVM_FEATURE_CLOCKSOURCE2) | + (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); + entry->ebx = 0; + entry->ecx = 0; + entry->edx = 0; + break; case 0x80000000: entry->eax = min(entry->eax, 0x8000001a); break; @@ -1918,6 +2006,9 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->ecx &= kvm_supported_word6_x86_features; break; } + + kvm_x86_ops->set_supported_cpuid(function, entry); + put_cpu(); } @@ -1953,6 +2044,23 @@ static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) do_cpuid_ent(&cpuid_entries[nent], func, 0, &nent, cpuid->nent); + + + + r = -E2BIG; + if (nent >= cpuid->nent) + goto out_free; + + do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, + cpuid->nent); + + r = -E2BIG; + if (nent >= cpuid->nent) + goto out_free; + + do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, + cpuid->nent); + r = -E2BIG; if (nent >= cpuid->nent) goto out_free; @@ -2032,6 +2140,7 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, int r; unsigned bank_num = mcg_cap & 0xff, bank; + vcpu_load(vcpu); r = -EINVAL; if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) goto out; @@ -2046,6 +2155,7 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, for (bank = 0; bank < bank_num; bank++) vcpu->arch.mce_banks[bank*4] = ~(u64)0; out: + vcpu_put(vcpu); return r; } @@ -2105,14 +2215,20 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, { vcpu_load(vcpu); - events->exception.injected = vcpu->arch.exception.pending; + events->exception.injected = + vcpu->arch.exception.pending && + !kvm_exception_is_soft(vcpu->arch.exception.nr); events->exception.nr = vcpu->arch.exception.nr; events->exception.has_error_code = vcpu->arch.exception.has_error_code; events->exception.error_code = vcpu->arch.exception.error_code; - events->interrupt.injected = vcpu->arch.interrupt.pending; + events->interrupt.injected = + vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; events->interrupt.nr = vcpu->arch.interrupt.nr; - events->interrupt.soft = vcpu->arch.interrupt.soft; + events->interrupt.soft = 0; + events->interrupt.shadow = + kvm_x86_ops->get_interrupt_shadow(vcpu, + KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); events->nmi.injected = vcpu->arch.nmi_injected; events->nmi.pending = vcpu->arch.nmi_pending; @@ -2121,7 +2237,8 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, events->sipi_vector = vcpu->arch.sipi_vector; events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING - | KVM_VCPUEVENT_VALID_SIPI_VECTOR); + | KVM_VCPUEVENT_VALID_SIPI_VECTOR + | KVM_VCPUEVENT_VALID_SHADOW); vcpu_put(vcpu); } @@ -2130,7 +2247,8 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, struct kvm_vcpu_events *events) { if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING - | KVM_VCPUEVENT_VALID_SIPI_VECTOR)) + | KVM_VCPUEVENT_VALID_SIPI_VECTOR + | KVM_VCPUEVENT_VALID_SHADOW)) return -EINVAL; vcpu_load(vcpu); @@ -2145,6 +2263,9 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, vcpu->arch.interrupt.soft = events->interrupt.soft; if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) kvm_pic_clear_isr_ack(vcpu->kvm); + if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) + kvm_x86_ops->set_interrupt_shadow(vcpu, + events->interrupt.shadow); vcpu->arch.nmi_injected = events->nmi.injected; if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) @@ -2159,6 +2280,36 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, return 0; } +static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, + struct kvm_debugregs *dbgregs) +{ + vcpu_load(vcpu); + + memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); + dbgregs->dr6 = vcpu->arch.dr6; + dbgregs->dr7 = vcpu->arch.dr7; + dbgregs->flags = 0; + + vcpu_put(vcpu); +} + +static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, + struct kvm_debugregs *dbgregs) +{ + if (dbgregs->flags) + return -EINVAL; + + vcpu_load(vcpu); + + memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); + vcpu->arch.dr6 = dbgregs->dr6; + vcpu->arch.dr7 = dbgregs->dr7; + + vcpu_put(vcpu); + + return 0; +} + long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { @@ -2313,7 +2464,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = -EFAULT; if (copy_from_user(&mce, argp, sizeof mce)) goto out; + vcpu_load(vcpu); r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); + vcpu_put(vcpu); break; } case KVM_GET_VCPU_EVENTS: { @@ -2337,6 +2490,29 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); break; } + case KVM_GET_DEBUGREGS: { + struct kvm_debugregs dbgregs; + + kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); + + r = -EFAULT; + if (copy_to_user(argp, &dbgregs, + sizeof(struct kvm_debugregs))) + break; + r = 0; + break; + } + case KVM_SET_DEBUGREGS: { + struct kvm_debugregs dbgregs; + + r = -EFAULT; + if (copy_from_user(&dbgregs, argp, + sizeof(struct kvm_debugregs))) + break; + + r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); + break; + } default: r = -EINVAL; } @@ -2390,7 +2566,7 @@ gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn) struct kvm_mem_alias *alias; struct kvm_mem_aliases *aliases; - aliases = rcu_dereference(kvm->arch.aliases); + aliases = kvm_aliases(kvm); for (i = 0; i < aliases->naliases; ++i) { alias = &aliases->aliases[i]; @@ -2409,7 +2585,7 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) struct kvm_mem_alias *alias; struct kvm_mem_aliases *aliases; - aliases = rcu_dereference(kvm->arch.aliases); + aliases = kvm_aliases(kvm); for (i = 0; i < aliases->naliases; ++i) { alias = &aliases->aliases[i]; @@ -2804,11 +2980,13 @@ long kvm_arch_vm_ioctl(struct file *filp, r = -EFAULT; if (copy_from_user(&irq_event, argp, sizeof irq_event)) goto out; + r = -ENXIO; if (irqchip_in_kernel(kvm)) { __s32 status; status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, irq_event.irq, irq_event.level); if (ioctl == KVM_IRQ_LINE_STATUS) { + r = -EFAULT; irq_event.status = status; if (copy_to_user(argp, &irq_event, sizeof irq_event)) @@ -3024,6 +3202,18 @@ static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); } +static void kvm_set_segment(struct kvm_vcpu *vcpu, + struct kvm_segment *var, int seg) +{ + kvm_x86_ops->set_segment(vcpu, var, seg); +} + +void kvm_get_segment(struct kvm_vcpu *vcpu, + struct kvm_segment *var, int seg) +{ + kvm_x86_ops->get_segment(vcpu, var, seg); +} + gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) { u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; @@ -3104,14 +3294,17 @@ static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error); } -static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, - struct kvm_vcpu *vcpu, u32 *error) +static int kvm_write_guest_virt_system(gva_t addr, void *val, + unsigned int bytes, + struct kvm_vcpu *vcpu, + u32 *error) { void *data = val; int r = X86EMUL_CONTINUE; while (bytes) { - gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error); + gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, + PFERR_WRITE_MASK, error); unsigned offset = addr & (PAGE_SIZE-1); unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); int ret; @@ -3134,7 +3327,6 @@ out: return r; } - static int emulator_read_emulated(unsigned long addr, void *val, unsigned int bytes, @@ -3237,9 +3429,9 @@ mmio: } int emulator_write_emulated(unsigned long addr, - const void *val, - unsigned int bytes, - struct kvm_vcpu *vcpu) + const void *val, + unsigned int bytes, + struct kvm_vcpu *vcpu) { /* Crossing a page boundary? */ if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { @@ -3257,45 +3449,150 @@ int emulator_write_emulated(unsigned long addr, } EXPORT_SYMBOL_GPL(emulator_write_emulated); +#define CMPXCHG_TYPE(t, ptr, old, new) \ + (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) + +#ifdef CONFIG_X86_64 +# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) +#else +# define CMPXCHG64(ptr, old, new) \ + (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) +#endif + static int emulator_cmpxchg_emulated(unsigned long addr, const void *old, const void *new, unsigned int bytes, struct kvm_vcpu *vcpu) { - printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); -#ifndef CONFIG_X86_64 - /* guests cmpxchg8b have to be emulated atomically */ - if (bytes == 8) { - gpa_t gpa; - struct page *page; - char *kaddr; - u64 val; + gpa_t gpa; + struct page *page; + char *kaddr; + bool exchanged; - gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); + /* guests cmpxchg8b have to be emulated atomically */ + if (bytes > 8 || (bytes & (bytes - 1))) + goto emul_write; - if (gpa == UNMAPPED_GVA || - (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) - goto emul_write; + gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); - if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) - goto emul_write; + if (gpa == UNMAPPED_GVA || + (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) + goto emul_write; - val = *(u64 *)new; + if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) + goto emul_write; - page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); + page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); - kaddr = kmap_atomic(page, KM_USER0); - set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); - kunmap_atomic(kaddr, KM_USER0); - kvm_release_page_dirty(page); + kaddr = kmap_atomic(page, KM_USER0); + kaddr += offset_in_page(gpa); + switch (bytes) { + case 1: + exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); + break; + case 2: + exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); + break; + case 4: + exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); + break; + case 8: + exchanged = CMPXCHG64(kaddr, old, new); + break; + default: + BUG(); } + kunmap_atomic(kaddr, KM_USER0); + kvm_release_page_dirty(page); + + if (!exchanged) + return X86EMUL_CMPXCHG_FAILED; + + kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); + + return X86EMUL_CONTINUE; + emul_write: -#endif + printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); return emulator_write_emulated(addr, new, bytes, vcpu); } +static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) +{ + /* TODO: String I/O for in kernel device */ + int r; + + if (vcpu->arch.pio.in) + r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, + vcpu->arch.pio.size, pd); + else + r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, + vcpu->arch.pio.port, vcpu->arch.pio.size, + pd); + return r; +} + + +static int emulator_pio_in_emulated(int size, unsigned short port, void *val, + unsigned int count, struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.pio.count) + goto data_avail; + + trace_kvm_pio(1, port, size, 1); + + vcpu->arch.pio.port = port; + vcpu->arch.pio.in = 1; + vcpu->arch.pio.count = count; + vcpu->arch.pio.size = size; + + if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { + data_avail: + memcpy(val, vcpu->arch.pio_data, size * count); + vcpu->arch.pio.count = 0; + return 1; + } + + vcpu->run->exit_reason = KVM_EXIT_IO; + vcpu->run->io.direction = KVM_EXIT_IO_IN; + vcpu->run->io.size = size; + vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; + vcpu->run->io.count = count; + vcpu->run->io.port = port; + + return 0; +} + +static int emulator_pio_out_emulated(int size, unsigned short port, + const void *val, unsigned int count, + struct kvm_vcpu *vcpu) +{ + trace_kvm_pio(0, port, size, 1); + + vcpu->arch.pio.port = port; + vcpu->arch.pio.in = 0; + vcpu->arch.pio.count = count; + vcpu->arch.pio.size = size; + + memcpy(vcpu->arch.pio_data, val, size * count); + + if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { + vcpu->arch.pio.count = 0; + return 1; + } + + vcpu->run->exit_reason = KVM_EXIT_IO; + vcpu->run->io.direction = KVM_EXIT_IO_OUT; + vcpu->run->io.size = size; + vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; + vcpu->run->io.count = count; + vcpu->run->io.port = port; + + return 0; +} + static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) { return kvm_x86_ops->get_segment_base(vcpu, seg); @@ -3316,14 +3613,14 @@ int emulate_clts(struct kvm_vcpu *vcpu) int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) { - return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest); + return kvm_get_dr(ctxt->vcpu, dr, dest); } int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) { unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; - return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask); + return kvm_set_dr(ctxt->vcpu, dr, value & mask); } void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) @@ -3344,12 +3641,167 @@ void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) } EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); +static u64 mk_cr_64(u64 curr_cr, u32 new_val) +{ + return (curr_cr & ~((1ULL << 32) - 1)) | new_val; +} + +static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) +{ + unsigned long value; + + switch (cr) { + case 0: + value = kvm_read_cr0(vcpu); + break; + case 2: + value = vcpu->arch.cr2; + break; + case 3: + value = vcpu->arch.cr3; + break; + case 4: + value = kvm_read_cr4(vcpu); + break; + case 8: + value = kvm_get_cr8(vcpu); + break; + default: + vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); + return 0; + } + + return value; +} + +static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) +{ + switch (cr) { + case 0: + kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); + break; + case 2: + vcpu->arch.cr2 = val; + break; + case 3: + kvm_set_cr3(vcpu, val); + break; + case 4: + kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); + break; + case 8: + kvm_set_cr8(vcpu, val & 0xfUL); + break; + default: + vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); + } +} + +static int emulator_get_cpl(struct kvm_vcpu *vcpu) +{ + return kvm_x86_ops->get_cpl(vcpu); +} + +static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) +{ + kvm_x86_ops->get_gdt(vcpu, dt); +} + +static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg, + struct kvm_vcpu *vcpu) +{ + struct kvm_segment var; + + kvm_get_segment(vcpu, &var, seg); + + if (var.unusable) + return false; + + if (var.g) + var.limit >>= 12; + set_desc_limit(desc, var.limit); + set_desc_base(desc, (unsigned long)var.base); + desc->type = var.type; + desc->s = var.s; + desc->dpl = var.dpl; + desc->p = var.present; + desc->avl = var.avl; + desc->l = var.l; + desc->d = var.db; + desc->g = var.g; + + return true; +} + +static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg, + struct kvm_vcpu *vcpu) +{ + struct kvm_segment var; + + /* needed to preserve selector */ + kvm_get_segment(vcpu, &var, seg); + + var.base = get_desc_base(desc); + var.limit = get_desc_limit(desc); + if (desc->g) + var.limit = (var.limit << 12) | 0xfff; + var.type = desc->type; + var.present = desc->p; + var.dpl = desc->dpl; + var.db = desc->d; + var.s = desc->s; + var.l = desc->l; + var.g = desc->g; + var.avl = desc->avl; + var.present = desc->p; + var.unusable = !var.present; + var.padding = 0; + + kvm_set_segment(vcpu, &var, seg); + return; +} + +static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) +{ + struct kvm_segment kvm_seg; + + kvm_get_segment(vcpu, &kvm_seg, seg); + return kvm_seg.selector; +} + +static void emulator_set_segment_selector(u16 sel, int seg, + struct kvm_vcpu *vcpu) +{ + struct kvm_segment kvm_seg; + + kvm_get_segment(vcpu, &kvm_seg, seg); + kvm_seg.selector = sel; + kvm_set_segment(vcpu, &kvm_seg, seg); +} + +static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) +{ + kvm_x86_ops->set_rflags(vcpu, rflags); +} + static struct x86_emulate_ops emulate_ops = { .read_std = kvm_read_guest_virt_system, + .write_std = kvm_write_guest_virt_system, .fetch = kvm_fetch_guest_virt, .read_emulated = emulator_read_emulated, .write_emulated = emulator_write_emulated, .cmpxchg_emulated = emulator_cmpxchg_emulated, + .pio_in_emulated = emulator_pio_in_emulated, + .pio_out_emulated = emulator_pio_out_emulated, + .get_cached_descriptor = emulator_get_cached_descriptor, + .set_cached_descriptor = emulator_set_cached_descriptor, + .get_segment_selector = emulator_get_segment_selector, + .set_segment_selector = emulator_set_segment_selector, + .get_gdt = emulator_get_gdt, + .get_cr = emulator_get_cr, + .set_cr = emulator_set_cr, + .cpl = emulator_get_cpl, + .set_rflags = emulator_set_rflags, }; static void cache_all_regs(struct kvm_vcpu *vcpu) @@ -3380,14 +3832,14 @@ int emulate_instruction(struct kvm_vcpu *vcpu, cache_all_regs(vcpu); vcpu->mmio_is_write = 0; - vcpu->arch.pio.string = 0; if (!(emulation_type & EMULTYPE_NO_DECODE)) { int cs_db, cs_l; kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); vcpu->arch.emulate_ctxt.vcpu = vcpu; - vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu); + vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); + vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); vcpu->arch.emulate_ctxt.mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) @@ -3396,6 +3848,7 @@ int emulate_instruction(struct kvm_vcpu *vcpu, ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); + trace_kvm_emulate_insn_start(vcpu); /* Only allow emulation of specific instructions on #UD * (namely VMMCALL, sysenter, sysexit, syscall)*/ @@ -3428,6 +3881,7 @@ int emulate_instruction(struct kvm_vcpu *vcpu, ++vcpu->stat.insn_emulation; if (r) { ++vcpu->stat.insn_emulation_fail; + trace_kvm_emulate_insn_failed(vcpu); if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) return EMULATE_DONE; return EMULATE_FAIL; @@ -3439,16 +3893,20 @@ int emulate_instruction(struct kvm_vcpu *vcpu, return EMULATE_DONE; } +restart: r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); shadow_mask = vcpu->arch.emulate_ctxt.interruptibility; if (r == 0) kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask); - if (vcpu->arch.pio.string) + if (vcpu->arch.pio.count) { + if (!vcpu->arch.pio.in) + vcpu->arch.pio.count = 0; return EMULATE_DO_MMIO; + } - if ((r || vcpu->mmio_is_write) && run) { + if (r || vcpu->mmio_is_write) { run->exit_reason = KVM_EXIT_MMIO; run->mmio.phys_addr = vcpu->mmio_phys_addr; memcpy(run->mmio.data, vcpu->mmio_data, 8); @@ -3458,222 +3916,41 @@ int emulate_instruction(struct kvm_vcpu *vcpu, if (r) { if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) - return EMULATE_DONE; + goto done; if (!vcpu->mmio_needed) { + ++vcpu->stat.insn_emulation_fail; + trace_kvm_emulate_insn_failed(vcpu); kvm_report_emulation_failure(vcpu, "mmio"); return EMULATE_FAIL; } return EMULATE_DO_MMIO; } - kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); - if (vcpu->mmio_is_write) { vcpu->mmio_needed = 0; return EMULATE_DO_MMIO; } - return EMULATE_DONE; -} -EXPORT_SYMBOL_GPL(emulate_instruction); - -static int pio_copy_data(struct kvm_vcpu *vcpu) -{ - void *p = vcpu->arch.pio_data; - gva_t q = vcpu->arch.pio.guest_gva; - unsigned bytes; - int ret; - u32 error_code; - - bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; - if (vcpu->arch.pio.in) - ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code); - else - ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code); - - if (ret == X86EMUL_PROPAGATE_FAULT) - kvm_inject_page_fault(vcpu, q, error_code); - - return ret; -} - -int complete_pio(struct kvm_vcpu *vcpu) -{ - struct kvm_pio_request *io = &vcpu->arch.pio; - long delta; - int r; - unsigned long val; - - if (!io->string) { - if (io->in) { - val = kvm_register_read(vcpu, VCPU_REGS_RAX); - memcpy(&val, vcpu->arch.pio_data, io->size); - kvm_register_write(vcpu, VCPU_REGS_RAX, val); - } - } else { - if (io->in) { - r = pio_copy_data(vcpu); - if (r) - goto out; - } - - delta = 1; - if (io->rep) { - delta *= io->cur_count; - /* - * The size of the register should really depend on - * current address size. - */ - val = kvm_register_read(vcpu, VCPU_REGS_RCX); - val -= delta; - kvm_register_write(vcpu, VCPU_REGS_RCX, val); - } - if (io->down) - delta = -delta; - delta *= io->size; - if (io->in) { - val = kvm_register_read(vcpu, VCPU_REGS_RDI); - val += delta; - kvm_register_write(vcpu, VCPU_REGS_RDI, val); - } else { - val = kvm_register_read(vcpu, VCPU_REGS_RSI); - val += delta; - kvm_register_write(vcpu, VCPU_REGS_RSI, val); - } - } -out: - io->count -= io->cur_count; - io->cur_count = 0; - - return 0; -} - -static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) -{ - /* TODO: String I/O for in kernel device */ - int r; - - if (vcpu->arch.pio.in) - r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, - vcpu->arch.pio.size, pd); - else - r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, - vcpu->arch.pio.port, vcpu->arch.pio.size, - pd); - return r; -} +done: + if (vcpu->arch.exception.pending) + vcpu->arch.emulate_ctxt.restart = false; -static int pio_string_write(struct kvm_vcpu *vcpu) -{ - struct kvm_pio_request *io = &vcpu->arch.pio; - void *pd = vcpu->arch.pio_data; - int i, r = 0; + if (vcpu->arch.emulate_ctxt.restart) + goto restart; - for (i = 0; i < io->cur_count; i++) { - if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, - io->port, io->size, pd)) { - r = -EOPNOTSUPP; - break; - } - pd += io->size; - } - return r; -} - -int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port) -{ - unsigned long val; - - trace_kvm_pio(!in, port, size, 1); - - vcpu->run->exit_reason = KVM_EXIT_IO; - vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; - vcpu->run->io.size = vcpu->arch.pio.size = size; - vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; - vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; - vcpu->run->io.port = vcpu->arch.pio.port = port; - vcpu->arch.pio.in = in; - vcpu->arch.pio.string = 0; - vcpu->arch.pio.down = 0; - vcpu->arch.pio.rep = 0; - - if (!vcpu->arch.pio.in) { - val = kvm_register_read(vcpu, VCPU_REGS_RAX); - memcpy(vcpu->arch.pio_data, &val, 4); - } - - if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { - complete_pio(vcpu); - return 1; - } - return 0; + return EMULATE_DONE; } -EXPORT_SYMBOL_GPL(kvm_emulate_pio); +EXPORT_SYMBOL_GPL(emulate_instruction); -int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in, - int size, unsigned long count, int down, - gva_t address, int rep, unsigned port) +int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) { - unsigned now, in_page; - int ret = 0; - - trace_kvm_pio(!in, port, size, count); - - vcpu->run->exit_reason = KVM_EXIT_IO; - vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; - vcpu->run->io.size = vcpu->arch.pio.size = size; - vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; - vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; - vcpu->run->io.port = vcpu->arch.pio.port = port; - vcpu->arch.pio.in = in; - vcpu->arch.pio.string = 1; - vcpu->arch.pio.down = down; - vcpu->arch.pio.rep = rep; - - if (!count) { - kvm_x86_ops->skip_emulated_instruction(vcpu); - return 1; - } - - if (!down) - in_page = PAGE_SIZE - offset_in_page(address); - else - in_page = offset_in_page(address) + size; - now = min(count, (unsigned long)in_page / size); - if (!now) - now = 1; - if (down) { - /* - * String I/O in reverse. Yuck. Kill the guest, fix later. - */ - pr_unimpl(vcpu, "guest string pio down\n"); - kvm_inject_gp(vcpu, 0); - return 1; - } - vcpu->run->io.count = now; - vcpu->arch.pio.cur_count = now; - - if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) - kvm_x86_ops->skip_emulated_instruction(vcpu); - - vcpu->arch.pio.guest_gva = address; - - if (!vcpu->arch.pio.in) { - /* string PIO write */ - ret = pio_copy_data(vcpu); - if (ret == X86EMUL_PROPAGATE_FAULT) - return 1; - if (ret == 0 && !pio_string_write(vcpu)) { - complete_pio(vcpu); - if (vcpu->arch.pio.count == 0) - ret = 1; - } - } - /* no string PIO read support yet */ - + unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); + int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); + /* do not return to emulator after return from userspace */ + vcpu->arch.pio.count = 0; return ret; } -EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); +EXPORT_SYMBOL_GPL(kvm_fast_pio_out); static void bounce_off(void *info) { @@ -3996,85 +4273,20 @@ int kvm_fix_hypercall(struct kvm_vcpu *vcpu) return emulator_write_emulated(rip, instruction, 3, vcpu); } -static u64 mk_cr_64(u64 curr_cr, u32 new_val) -{ - return (curr_cr & ~((1ULL << 32) - 1)) | new_val; -} - void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) { - struct descriptor_table dt = { limit, base }; + struct desc_ptr dt = { limit, base }; kvm_x86_ops->set_gdt(vcpu, &dt); } void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) { - struct descriptor_table dt = { limit, base }; + struct desc_ptr dt = { limit, base }; kvm_x86_ops->set_idt(vcpu, &dt); } -void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, - unsigned long *rflags) -{ - kvm_lmsw(vcpu, msw); - *rflags = kvm_get_rflags(vcpu); -} - -unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) -{ - unsigned long value; - - switch (cr) { - case 0: - value = kvm_read_cr0(vcpu); - break; - case 2: - value = vcpu->arch.cr2; - break; - case 3: - value = vcpu->arch.cr3; - break; - case 4: - value = kvm_read_cr4(vcpu); - break; - case 8: - value = kvm_get_cr8(vcpu); - break; - default: - vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); - return 0; - } - - return value; -} - -void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, - unsigned long *rflags) -{ - switch (cr) { - case 0: - kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); - *rflags = kvm_get_rflags(vcpu); - break; - case 2: - vcpu->arch.cr2 = val; - break; - case 3: - kvm_set_cr3(vcpu, val); - break; - case 4: - kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); - break; - case 8: - kvm_set_cr8(vcpu, val & 0xfUL); - break; - default: - vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); - } -} - static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) { struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; @@ -4138,9 +4350,13 @@ int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) { struct kvm_cpuid_entry2 *best; + best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); + if (!best || best->eax < 0x80000008) + goto not_found; best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); if (best) return best->eax & 0xff; +not_found: return 36; } @@ -4254,9 +4470,13 @@ static void inject_pending_event(struct kvm_vcpu *vcpu) { /* try to reinject previous events if any */ if (vcpu->arch.exception.pending) { + trace_kvm_inj_exception(vcpu->arch.exception.nr, + vcpu->arch.exception.has_error_code, + vcpu->arch.exception.error_code); kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, vcpu->arch.exception.has_error_code, - vcpu->arch.exception.error_code); + vcpu->arch.exception.error_code, + vcpu->arch.exception.reinject); return; } @@ -4486,7 +4706,6 @@ static int __vcpu_run(struct kvm_vcpu *vcpu) } srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); - post_kvm_run_save(vcpu); vapic_exit(vcpu); @@ -4514,26 +4733,17 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) if (!irqchip_in_kernel(vcpu->kvm)) kvm_set_cr8(vcpu, kvm_run->cr8); - if (vcpu->arch.pio.cur_count) { - vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); - r = complete_pio(vcpu); - srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); - if (r) - goto out; - } - if (vcpu->mmio_needed) { - memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); - vcpu->mmio_read_completed = 1; - vcpu->mmio_needed = 0; - + if (vcpu->arch.pio.count || vcpu->mmio_needed || + vcpu->arch.emulate_ctxt.restart) { + if (vcpu->mmio_needed) { + memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); + vcpu->mmio_read_completed = 1; + vcpu->mmio_needed = 0; + } vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); - r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0, - EMULTYPE_NO_DECODE); + r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE); srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); if (r == EMULATE_DO_MMIO) { - /* - * Read-modify-write. Back to userspace. - */ r = 0; goto out; } @@ -4545,6 +4755,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) r = __vcpu_run(vcpu); out: + post_kvm_run_save(vcpu); if (vcpu->sigset_active) sigprocmask(SIG_SETMASK, &sigsaved, NULL); @@ -4616,12 +4827,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) return 0; } -void kvm_get_segment(struct kvm_vcpu *vcpu, - struct kvm_segment *var, int seg) -{ - kvm_x86_ops->get_segment(vcpu, var, seg); -} - void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) { struct kvm_segment cs; @@ -4635,7 +4840,7 @@ EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) { - struct descriptor_table dt; + struct desc_ptr dt; vcpu_load(vcpu); @@ -4650,11 +4855,11 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); kvm_x86_ops->get_idt(vcpu, &dt); - sregs->idt.limit = dt.limit; - sregs->idt.base = dt.base; + sregs->idt.limit = dt.size; + sregs->idt.base = dt.address; kvm_x86_ops->get_gdt(vcpu, &dt); - sregs->gdt.limit = dt.limit; - sregs->gdt.base = dt.base; + sregs->gdt.limit = dt.size; + sregs->gdt.base = dt.address; sregs->cr0 = kvm_read_cr0(vcpu); sregs->cr2 = vcpu->arch.cr2; @@ -4693,563 +4898,33 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, return 0; } -static void kvm_set_segment(struct kvm_vcpu *vcpu, - struct kvm_segment *var, int seg) -{ - kvm_x86_ops->set_segment(vcpu, var, seg); -} - -static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, - struct kvm_segment *kvm_desct) -{ - kvm_desct->base = get_desc_base(seg_desc); - kvm_desct->limit = get_desc_limit(seg_desc); - if (seg_desc->g) { - kvm_desct->limit <<= 12; - kvm_desct->limit |= 0xfff; - } - kvm_desct->selector = selector; - kvm_desct->type = seg_desc->type; - kvm_desct->present = seg_desc->p; - kvm_desct->dpl = seg_desc->dpl; - kvm_desct->db = seg_desc->d; - kvm_desct->s = seg_desc->s; - kvm_desct->l = seg_desc->l; - kvm_desct->g = seg_desc->g; - kvm_desct->avl = seg_desc->avl; - if (!selector) - kvm_desct->unusable = 1; - else - kvm_desct->unusable = 0; - kvm_desct->padding = 0; -} - -static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, - u16 selector, - struct descriptor_table *dtable) -{ - if (selector & 1 << 2) { - struct kvm_segment kvm_seg; - - kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); - - if (kvm_seg.unusable) - dtable->limit = 0; - else - dtable->limit = kvm_seg.limit; - dtable->base = kvm_seg.base; - } - else - kvm_x86_ops->get_gdt(vcpu, dtable); -} - -/* allowed just for 8 bytes segments */ -static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, - struct desc_struct *seg_desc) -{ - struct descriptor_table dtable; - u16 index = selector >> 3; - int ret; - u32 err; - gva_t addr; - - get_segment_descriptor_dtable(vcpu, selector, &dtable); - - if (dtable.limit < index * 8 + 7) { - kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); - return X86EMUL_PROPAGATE_FAULT; - } - addr = dtable.base + index * 8; - ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc), - vcpu, &err); - if (ret == X86EMUL_PROPAGATE_FAULT) - kvm_inject_page_fault(vcpu, addr, err); - - return ret; -} - -/* allowed just for 8 bytes segments */ -static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, - struct desc_struct *seg_desc) -{ - struct descriptor_table dtable; - u16 index = selector >> 3; - - get_segment_descriptor_dtable(vcpu, selector, &dtable); - - if (dtable.limit < index * 8 + 7) - return 1; - return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL); -} - -static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu, - struct desc_struct *seg_desc) -{ - u32 base_addr = get_desc_base(seg_desc); - - return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL); -} - -static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu, - struct desc_struct *seg_desc) -{ - u32 base_addr = get_desc_base(seg_desc); - - return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL); -} - -static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) -{ - struct kvm_segment kvm_seg; - - kvm_get_segment(vcpu, &kvm_seg, seg); - return kvm_seg.selector; -} - -static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) -{ - struct kvm_segment segvar = { - .base = selector << 4, - .limit = 0xffff, - .selector = selector, - .type = 3, - .present = 1, - .dpl = 3, - .db = 0, - .s = 1, - .l = 0, - .g = 0, - .avl = 0, - .unusable = 0, - }; - kvm_x86_ops->set_segment(vcpu, &segvar, seg); - return X86EMUL_CONTINUE; -} - -static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg) +int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, + bool has_error_code, u32 error_code) { - return (seg != VCPU_SREG_LDTR) && - (seg != VCPU_SREG_TR) && - (kvm_get_rflags(vcpu) & X86_EFLAGS_VM); -} - -int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg) -{ - struct kvm_segment kvm_seg; - struct desc_struct seg_desc; - u8 dpl, rpl, cpl; - unsigned err_vec = GP_VECTOR; - u32 err_code = 0; - bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ - int ret; + int cs_db, cs_l, ret; + cache_all_regs(vcpu); - if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu)) - return kvm_load_realmode_segment(vcpu, selector, seg); + kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); - /* NULL selector is not valid for TR, CS and SS */ - if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) - && null_selector) - goto exception; + vcpu->arch.emulate_ctxt.vcpu = vcpu; + vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); + vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); + vcpu->arch.emulate_ctxt.mode = + (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : + (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) + ? X86EMUL_MODE_VM86 : cs_l + ? X86EMUL_MODE_PROT64 : cs_db + ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; - /* TR should be in GDT only */ - if (seg == VCPU_SREG_TR && (selector & (1 << 2))) - goto exception; + ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops, + tss_selector, reason, has_error_code, + error_code); - ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc); if (ret) - return ret; - - seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg); - - if (null_selector) { /* for NULL selector skip all following checks */ - kvm_seg.unusable = 1; - goto load; - } - - err_code = selector & 0xfffc; - err_vec = GP_VECTOR; - - /* can't load system descriptor into segment selecor */ - if (seg <= VCPU_SREG_GS && !kvm_seg.s) - goto exception; - - if (!kvm_seg.present) { - err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; - goto exception; - } - - rpl = selector & 3; - dpl = kvm_seg.dpl; - cpl = kvm_x86_ops->get_cpl(vcpu); - - switch (seg) { - case VCPU_SREG_SS: - /* - * segment is not a writable data segment or segment - * selector's RPL != CPL or segment selector's RPL != CPL - */ - if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl) - goto exception; - break; - case VCPU_SREG_CS: - if (!(kvm_seg.type & 8)) - goto exception; - - if (kvm_seg.type & 4) { - /* conforming */ - if (dpl > cpl) - goto exception; - } else { - /* nonconforming */ - if (rpl > cpl || dpl != cpl) - goto exception; - } - /* CS(RPL) <- CPL */ - selector = (selector & 0xfffc) | cpl; - break; - case VCPU_SREG_TR: - if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9)) - goto exception; - break; - case VCPU_SREG_LDTR: - if (kvm_seg.s || kvm_seg.type != 2) - goto exception; - break; - default: /* DS, ES, FS, or GS */ - /* - * segment is not a data or readable code segment or - * ((segment is a data or nonconforming code segment) - * and (both RPL and CPL > DPL)) - */ - if ((kvm_seg.type & 0xa) == 0x8 || - (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl))) - goto exception; - break; - } - - if (!kvm_seg.unusable && kvm_seg.s) { - /* mark segment as accessed */ - kvm_seg.type |= 1; - seg_desc.type |= 1; - save_guest_segment_descriptor(vcpu, selector, &seg_desc); - } -load: - kvm_set_segment(vcpu, &kvm_seg, seg); - return X86EMUL_CONTINUE; -exception: - kvm_queue_exception_e(vcpu, err_vec, err_code); - return X86EMUL_PROPAGATE_FAULT; -} - -static void save_state_to_tss32(struct kvm_vcpu *vcpu, - struct tss_segment_32 *tss) -{ - tss->cr3 = vcpu->arch.cr3; - tss->eip = kvm_rip_read(vcpu); - tss->eflags = kvm_get_rflags(vcpu); - tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); - tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); - tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); - tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); - tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); - tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); - tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); - tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); - tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); - tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); - tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); - tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); - tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); - tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); - tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); -} - -static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg) -{ - struct kvm_segment kvm_seg; - kvm_get_segment(vcpu, &kvm_seg, seg); - kvm_seg.selector = sel; - kvm_set_segment(vcpu, &kvm_seg, seg); -} - -static int load_state_from_tss32(struct kvm_vcpu *vcpu, - struct tss_segment_32 *tss) -{ - kvm_set_cr3(vcpu, tss->cr3); - - kvm_rip_write(vcpu, tss->eip); - kvm_set_rflags(vcpu, tss->eflags | 2); - - kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); - kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); - kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); - kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); - kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); - kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); - kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); - kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); - - /* - * SDM says that segment selectors are loaded before segment - * descriptors - */ - kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR); - kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES); - kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS); - kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS); - kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS); - kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS); - kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS); - - /* - * Now load segment descriptors. If fault happenes at this stage - * it is handled in a context of new task - */ - if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES)) - return 1; + return EMULATE_FAIL; - if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS)) - return 1; - return 0; -} - -static void save_state_to_tss16(struct kvm_vcpu *vcpu, - struct tss_segment_16 *tss) -{ - tss->ip = kvm_rip_read(vcpu); - tss->flag = kvm_get_rflags(vcpu); - tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); - tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); - tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); - tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); - tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); - tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); - tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); - tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); - - tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); - tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); - tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); - tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); - tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); -} - -static int load_state_from_tss16(struct kvm_vcpu *vcpu, - struct tss_segment_16 *tss) -{ - kvm_rip_write(vcpu, tss->ip); - kvm_set_rflags(vcpu, tss->flag | 2); - kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); - kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); - kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); - kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); - kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); - kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); - kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); - kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); - - /* - * SDM says that segment selectors are loaded before segment - * descriptors - */ - kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR); - kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES); - kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS); - kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS); - kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS); - - /* - * Now load segment descriptors. If fault happenes at this stage - * it is handled in a context of new task - */ - if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS)) - return 1; - - if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS)) - return 1; - return 0; -} - -static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, - u16 old_tss_sel, u32 old_tss_base, - struct desc_struct *nseg_desc) -{ - struct tss_segment_16 tss_segment_16; - int ret = 0; - - if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, - sizeof tss_segment_16)) - goto out; - - save_state_to_tss16(vcpu, &tss_segment_16); - - if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, - sizeof tss_segment_16)) - goto out; - - if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc), - &tss_segment_16, sizeof tss_segment_16)) - goto out; - - if (old_tss_sel != 0xffff) { - tss_segment_16.prev_task_link = old_tss_sel; - - if (kvm_write_guest(vcpu->kvm, - get_tss_base_addr_write(vcpu, nseg_desc), - &tss_segment_16.prev_task_link, - sizeof tss_segment_16.prev_task_link)) - goto out; - } - - if (load_state_from_tss16(vcpu, &tss_segment_16)) - goto out; - - ret = 1; -out: - return ret; -} - -static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, - u16 old_tss_sel, u32 old_tss_base, - struct desc_struct *nseg_desc) -{ - struct tss_segment_32 tss_segment_32; - int ret = 0; - - if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, - sizeof tss_segment_32)) - goto out; - - save_state_to_tss32(vcpu, &tss_segment_32); - - if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, - sizeof tss_segment_32)) - goto out; - - if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc), - &tss_segment_32, sizeof tss_segment_32)) - goto out; - - if (old_tss_sel != 0xffff) { - tss_segment_32.prev_task_link = old_tss_sel; - - if (kvm_write_guest(vcpu->kvm, - get_tss_base_addr_write(vcpu, nseg_desc), - &tss_segment_32.prev_task_link, - sizeof tss_segment_32.prev_task_link)) - goto out; - } - - if (load_state_from_tss32(vcpu, &tss_segment_32)) - goto out; - - ret = 1; -out: - return ret; -} - -int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) -{ - struct kvm_segment tr_seg; - struct desc_struct cseg_desc; - struct desc_struct nseg_desc; - int ret = 0; - u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); - u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); - u32 desc_limit; - - old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL); - - /* FIXME: Handle errors. Failure to read either TSS or their - * descriptors should generate a pagefault. - */ - if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) - goto out; - - if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) - goto out; - - if (reason != TASK_SWITCH_IRET) { - int cpl; - - cpl = kvm_x86_ops->get_cpl(vcpu); - if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { - kvm_queue_exception_e(vcpu, GP_VECTOR, 0); - return 1; - } - } - - desc_limit = get_desc_limit(&nseg_desc); - if (!nseg_desc.p || - ((desc_limit < 0x67 && (nseg_desc.type & 8)) || - desc_limit < 0x2b)) { - kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); - return 1; - } - - if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { - cseg_desc.type &= ~(1 << 1); //clear the B flag - save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); - } - - if (reason == TASK_SWITCH_IRET) { - u32 eflags = kvm_get_rflags(vcpu); - kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); - } - - /* set back link to prev task only if NT bit is set in eflags - note that old_tss_sel is not used afetr this point */ - if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) - old_tss_sel = 0xffff; - - if (nseg_desc.type & 8) - ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, - old_tss_base, &nseg_desc); - else - ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, - old_tss_base, &nseg_desc); - - if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { - u32 eflags = kvm_get_rflags(vcpu); - kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT); - } - - if (reason != TASK_SWITCH_IRET) { - nseg_desc.type |= (1 << 1); - save_guest_segment_descriptor(vcpu, tss_selector, - &nseg_desc); - } - - kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS); - seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); - tr_seg.type = 11; - kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); -out: - return ret; + kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); + return EMULATE_DONE; } EXPORT_SYMBOL_GPL(kvm_task_switch); @@ -5258,15 +4933,15 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, { int mmu_reset_needed = 0; int pending_vec, max_bits; - struct descriptor_table dt; + struct desc_ptr dt; vcpu_load(vcpu); - dt.limit = sregs->idt.limit; - dt.base = sregs->idt.base; + dt.size = sregs->idt.limit; + dt.address = sregs->idt.base; kvm_x86_ops->set_idt(vcpu, &dt); - dt.limit = sregs->gdt.limit; - dt.base = sregs->gdt.base; + dt.size = sregs->gdt.limit; + dt.address = sregs->gdt.base; kvm_x86_ops->set_gdt(vcpu, &dt); vcpu->arch.cr2 = sregs->cr2; @@ -5365,11 +5040,9 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); } - if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { - vcpu->arch.singlestep_cs = - get_segment_selector(vcpu, VCPU_SREG_CS); - vcpu->arch.singlestep_rip = kvm_rip_read(vcpu); - } + if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) + vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + + get_segment_base(vcpu, VCPU_SREG_CS); /* * Trigger an rflags update that will inject or remove the trace @@ -5860,13 +5533,22 @@ int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) return kvm_x86_ops->interrupt_allowed(vcpu); } +bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) +{ + unsigned long current_rip = kvm_rip_read(vcpu) + + get_segment_base(vcpu, VCPU_SREG_CS); + + return current_rip == linear_rip; +} +EXPORT_SYMBOL_GPL(kvm_is_linear_rip); + unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) { unsigned long rflags; rflags = kvm_x86_ops->get_rflags(vcpu); if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) - rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF); + rflags &= ~X86_EFLAGS_TF; return rflags; } EXPORT_SYMBOL_GPL(kvm_get_rflags); @@ -5874,10 +5556,8 @@ EXPORT_SYMBOL_GPL(kvm_get_rflags); void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) { if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && - vcpu->arch.singlestep_cs == - get_segment_selector(vcpu, VCPU_SREG_CS) && - vcpu->arch.singlestep_rip == kvm_rip_read(vcpu)) - rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF; + kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) + rflags |= X86_EFLAGS_TF; kvm_x86_ops->set_rflags(vcpu, rflags); } EXPORT_SYMBOL_GPL(kvm_set_rflags); @@ -5893,3 +5573,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); +EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index b7a404722d2b..f4b54458285b 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -65,6 +65,13 @@ static inline int is_paging(struct kvm_vcpu *vcpu) return kvm_read_cr0_bits(vcpu, X86_CR0_PG); } +static inline struct kvm_mem_aliases *kvm_aliases(struct kvm *kvm) +{ + return rcu_dereference_check(kvm->arch.aliases, + srcu_read_lock_held(&kvm->srcu) + || lockdep_is_held(&kvm->slots_lock)); +} + void kvm_before_handle_nmi(struct kvm_vcpu *vcpu); void kvm_after_handle_nmi(struct kvm_vcpu *vcpu); diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 2bdf628066bd..9257510b4836 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -1390,7 +1390,6 @@ __init void lguest_init(void) #endif #ifdef CONFIG_ACPI acpi_disabled = 1; - acpi_ht = 0; #endif /* diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index 550df481accd..787c52ca49c3 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -3,12 +3,6 @@ #include <linux/module.h> #include <linux/bootmem.h> -#ifdef CONFIG_DEBUG_PER_CPU_MAPS -# define DBG(x...) printk(KERN_DEBUG x) -#else -# define DBG(x...) -#endif - /* * Which logical CPUs are on which nodes */ diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index 8948f47fde05..a7bcc23ef96c 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -33,9 +33,6 @@ int numa_off __initdata; static unsigned long __initdata nodemap_addr; static unsigned long __initdata nodemap_size; -DEFINE_PER_CPU(int, node_number) = 0; -EXPORT_PER_CPU_SYMBOL(node_number); - /* * Map cpu index to node index */ @@ -809,7 +806,7 @@ void __cpuinit numa_set_node(int cpu, int node) per_cpu(x86_cpu_to_node_map, cpu) = node; if (node != NUMA_NO_NODE) - per_cpu(node_number, cpu) = node; + set_cpu_numa_node(cpu, node); } void __cpuinit numa_clear_node(int cpu) @@ -867,7 +864,7 @@ void __cpuinit numa_remove_cpu(int cpu) numa_set_cpumask(cpu, 0); } -int cpu_to_node(int cpu) +int __cpu_to_node(int cpu) { if (early_per_cpu_ptr(x86_cpu_to_node_map)) { printk(KERN_WARNING @@ -877,7 +874,7 @@ int cpu_to_node(int cpu) } return per_cpu(x86_cpu_to_node_map, cpu); } -EXPORT_SYMBOL(cpu_to_node); +EXPORT_SYMBOL(__cpu_to_node); /* * Same function as cpu_to_node() but used if called before the diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index bbe5502ee1cb..acc15b23b743 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -336,6 +336,7 @@ int free_memtype(u64 start, u64 end) { int err = -EINVAL; int is_range_ram; + struct memtype *entry; if (!pat_enabled) return 0; @@ -355,17 +356,20 @@ int free_memtype(u64 start, u64 end) } spin_lock(&memtype_lock); - err = rbt_memtype_erase(start, end); + entry = rbt_memtype_erase(start, end); spin_unlock(&memtype_lock); - if (err) { + if (!entry) { printk(KERN_INFO "%s:%d freeing invalid memtype %Lx-%Lx\n", current->comm, current->pid, start, end); + return -EINVAL; } + kfree(entry); + dprintk("free_memtype request 0x%Lx-0x%Lx\n", start, end); - return err; + return 0; } diff --git a/arch/x86/mm/pat_internal.h b/arch/x86/mm/pat_internal.h index 4f39eefa3e61..77e5ba153fac 100644 --- a/arch/x86/mm/pat_internal.h +++ b/arch/x86/mm/pat_internal.h @@ -28,15 +28,15 @@ static inline char *cattr_name(unsigned long flags) #ifdef CONFIG_X86_PAT extern int rbt_memtype_check_insert(struct memtype *new, unsigned long *new_type); -extern int rbt_memtype_erase(u64 start, u64 end); +extern struct memtype *rbt_memtype_erase(u64 start, u64 end); extern struct memtype *rbt_memtype_lookup(u64 addr); extern int rbt_memtype_copy_nth_element(struct memtype *out, loff_t pos); #else static inline int rbt_memtype_check_insert(struct memtype *new, unsigned long *new_type) { return 0; } -static inline int rbt_memtype_erase(u64 start, u64 end) -{ return 0; } +static inline struct memtype *rbt_memtype_erase(u64 start, u64 end) +{ return NULL; } static inline struct memtype *rbt_memtype_lookup(u64 addr) { return NULL; } static inline int rbt_memtype_copy_nth_element(struct memtype *out, loff_t pos) diff --git a/arch/x86/mm/pat_rbtree.c b/arch/x86/mm/pat_rbtree.c index 07de4cb8cc30..f537087bb740 100644 --- a/arch/x86/mm/pat_rbtree.c +++ b/arch/x86/mm/pat_rbtree.c @@ -231,16 +231,17 @@ int rbt_memtype_check_insert(struct memtype *new, unsigned long *ret_type) return err; } -int rbt_memtype_erase(u64 start, u64 end) +struct memtype *rbt_memtype_erase(u64 start, u64 end) { struct memtype *data; data = memtype_rb_exact_match(&memtype_rbroot, start, end); if (!data) - return -EINVAL; + goto out; rb_erase(&data->rb, &memtype_rbroot); - return 0; +out: + return data; } struct memtype *rbt_memtype_lookup(u64 addr) diff --git a/arch/x86/mm/pf_in.c b/arch/x86/mm/pf_in.c index df3d5c861cda..308e32570d84 100644 --- a/arch/x86/mm/pf_in.c +++ b/arch/x86/mm/pf_in.c @@ -34,7 +34,7 @@ /* IA32 Manual 3, 2-1 */ static unsigned char prefix_codes[] = { 0xF0, 0xF2, 0xF3, 0x2E, 0x36, 0x3E, 0x26, 0x64, - 0x65, 0x2E, 0x3E, 0x66, 0x67 + 0x65, 0x66, 0x67 }; /* IA32 Manual 3, 3-432*/ static unsigned int reg_rop[] = { diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c index 792854003ed3..cac718499256 100644 --- a/arch/x86/mm/pgtable_32.c +++ b/arch/x86/mm/pgtable_32.c @@ -9,7 +9,6 @@ #include <linux/pagemap.h> #include <linux/spinlock.h> #include <linux/module.h> -#include <linux/quicklist.h> #include <asm/system.h> #include <asm/pgtable.h> diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index b110d97fb925..a0207a7fdf39 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_X86_MRST) += mrst.o obj-y += common.o early.o obj-y += amd_bus.o bus_numa.o +obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o + ifeq ($(CONFIG_PCI_DEBUG),y) EXTRA_CFLAGS += -DDEBUG endif diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index 31930fd30ea9..2ec04c424a62 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -207,10 +207,9 @@ get_current_resources(struct acpi_device *device, int busnum, if (!info.res) goto res_alloc_fail; - info.name = kmalloc(16, GFP_KERNEL); + info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum); if (!info.name) goto name_alloc_fail; - sprintf(info.name, "PCI Bus %04x:%02x", domain, busnum); info.res_num = 0; acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource, @@ -224,8 +223,11 @@ res_alloc_fail: return; } -struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int domain, int busnum) +struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) { + struct acpi_device *device = root->device; + int domain = root->segment; + int busnum = root->secondary.start; struct pci_bus *bus; struct pci_sysdata *sd; int node; diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c new file mode 100644 index 000000000000..0846a5bbbfbd --- /dev/null +++ b/arch/x86/pci/broadcom_bus.c @@ -0,0 +1,101 @@ +/* + * Read address ranges from a Broadcom CNB20LE Host Bridge + * + * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/delay.h> +#include <linux/dmi.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <asm/pci_x86.h> + +#include "bus_numa.h" + +static void __devinit cnb20le_res(struct pci_dev *dev) +{ + struct pci_root_info *info; + struct resource res; + u16 word1, word2; + u8 fbus, lbus; + int i; + + /* + * The x86_pci_root_bus_res_quirks() function already refuses to use + * this information if ACPI _CRS was used. Therefore, we don't bother + * checking if ACPI is enabled, and just generate the information + * for both the ACPI _CRS and no ACPI cases. + */ + + info = &pci_root_info[pci_root_num]; + pci_root_num++; + + /* read the PCI bus numbers */ + pci_read_config_byte(dev, 0x44, &fbus); + pci_read_config_byte(dev, 0x45, &lbus); + info->bus_min = fbus; + info->bus_max = lbus; + + /* + * Add the legacy IDE ports on bus 0 + * + * These do not exist anywhere in the bridge registers, AFAICT. I do + * not have the datasheet, so this is the best I can do. + */ + if (fbus == 0) { + update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0); + update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0); + update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0); + update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0); + update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0); + } + + /* read the non-prefetchable memory window */ + pci_read_config_word(dev, 0xc0, &word1); + pci_read_config_word(dev, 0xc2, &word2); + if (word1 != word2) { + res.start = (word1 << 16) | 0x0000; + res.end = (word2 << 16) | 0xffff; + res.flags = IORESOURCE_MEM; + update_res(info, res.start, res.end, res.flags, 0); + } + + /* read the prefetchable memory window */ + pci_read_config_word(dev, 0xc4, &word1); + pci_read_config_word(dev, 0xc6, &word2); + if (word1 != word2) { + res.start = (word1 << 16) | 0x0000; + res.end = (word2 << 16) | 0xffff; + res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + update_res(info, res.start, res.end, res.flags, 0); + } + + /* read the IO port window */ + pci_read_config_word(dev, 0xd0, &word1); + pci_read_config_word(dev, 0xd2, &word2); + if (word1 != word2) { + res.start = word1; + res.end = word2; + res.flags = IORESOURCE_IO; + update_res(info, res.start, res.end, res.flags, 0); + } + + /* print information about this host bridge */ + res.start = fbus; + res.end = lbus; + res.flags = IORESOURCE_BUS; + dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n", + pci_domain_nr(dev->bus), &res); + + for (i = 0; i < info->res_num; i++) + dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]); +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, + cnb20le_res); + diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index cf2e93869c48..215a27ae050d 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -76,7 +76,7 @@ struct pci_ops pci_root_ops = { * This interrupt-safe spinlock protects all accesses to PCI * configuration space. */ -DEFINE_SPINLOCK(pci_config_lock); +DEFINE_RAW_SPINLOCK(pci_config_lock); static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d) { diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c index 347d882b3bb3..bd33620b0071 100644 --- a/arch/x86/pci/direct.c +++ b/arch/x86/pci/direct.c @@ -27,7 +27,7 @@ static int pci_conf1_read(unsigned int seg, unsigned int bus, return -EINVAL; } - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); @@ -43,7 +43,7 @@ static int pci_conf1_read(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } @@ -56,7 +56,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus, if ((bus > 255) || (devfn > 255) || (reg > 4095)) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); @@ -72,7 +72,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } @@ -108,7 +108,7 @@ static int pci_conf2_read(unsigned int seg, unsigned int bus, if (dev & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); outb((u8)(0xF0 | (fn << 1)), 0xCF8); outb((u8)bus, 0xCFA); @@ -127,7 +127,7 @@ static int pci_conf2_read(unsigned int seg, unsigned int bus, outb(0, 0xCF8); - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } @@ -147,7 +147,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus, if (dev & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); outb((u8)(0xF0 | (fn << 1)), 0xCF8); outb((u8)bus, 0xCFA); @@ -166,7 +166,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus, outb(0, 0xCF8); - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 97da2ba9344b..6fdb3ec30c31 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -96,6 +96,7 @@ EXPORT_SYMBOL(pcibios_align_resource); * the fact the PCI specs explicitly allow address decoders to be * shared between expansion ROMs and other resource regions, it's * at least dangerous) + * - bad resource sizes or overlaps with other regions * * Our solution: * (1) Allocate resources for all buses behind PCI-to-PCI bridges. @@ -136,6 +137,7 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) * child resource allocations in this * range. */ + r->start = r->end = 0; r->flags = 0; } } diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c index 5d362b5ba06f..9810a0f76c91 100644 --- a/arch/x86/pci/irq.c +++ b/arch/x86/pci/irq.c @@ -589,8 +589,6 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route case PCI_DEVICE_ID_INTEL_ICH10_1: case PCI_DEVICE_ID_INTEL_ICH10_2: case PCI_DEVICE_ID_INTEL_ICH10_3: - case PCI_DEVICE_ID_INTEL_CPT_LPC1: - case PCI_DEVICE_ID_INTEL_CPT_LPC2: r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; @@ -605,6 +603,13 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route return 1; } + if ((device >= PCI_DEVICE_ID_INTEL_CPT_LPC_MIN) && + (device <= PCI_DEVICE_ID_INTEL_CPT_LPC_MAX)) { + r->name = "PIIX/ICH"; + r->get = pirq_piix_get; + r->set = pirq_piix_set; + return 1; + } return 0; } diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c index 0db5eaf54560..8d460eaf524f 100644 --- a/arch/x86/pci/legacy.c +++ b/arch/x86/pci/legacy.c @@ -11,28 +11,14 @@ */ static void __devinit pcibios_fixup_peer_bridges(void) { - int n, devfn; - long node; + int n; if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff) return; DBG("PCI: Peer bridge fixup\n"); - for (n=0; n <= pcibios_last_bus; n++) { - u32 l; - if (pci_find_bus(0, n)) - continue; - node = get_mp_bus_to_node(n); - for (devfn = 0; devfn < 256; devfn += 8) { - if (!raw_pci_read(0, n, devfn, PCI_VENDOR_ID, 2, &l) && - l != 0x0000 && l != 0xffff) { - DBG("Found device at %02x:%02x [%04x]\n", n, devfn, l); - printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n); - pci_scan_bus_on_node(n, &pci_root_ops, node); - break; - } - } - } + for (n=0; n <= pcibios_last_bus; n++) + pcibios_scan_specific_bus(n); } int __init pci_legacy_init(void) @@ -50,6 +36,28 @@ int __init pci_legacy_init(void) return 0; } +void pcibios_scan_specific_bus(int busn) +{ + int devfn; + long node; + u32 l; + + if (pci_find_bus(0, busn)) + return; + + node = get_mp_bus_to_node(busn); + for (devfn = 0; devfn < 256; devfn += 8) { + if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) && + l != 0x0000 && l != 0xffff) { + DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l); + printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn); + pci_scan_bus_on_node(busn, &pci_root_ops, node); + return; + } + } +} +EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus); + int __init pci_subsys_init(void) { /* diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 39b9ebe8f886..a918553ebc75 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -483,16 +483,17 @@ static void __init pci_mmcfg_reject_broken(int early) list_for_each_entry(cfg, &pci_mmcfg_list, list) { int valid = 0; - if (!early && !acpi_disabled) + if (!early && !acpi_disabled) { valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0); - if (valid) - continue; - - if (!early) - printk(KERN_ERR FW_BUG PREFIX - "MMCONFIG at %pR not reserved in " - "ACPI motherboard resources\n", &cfg->res); + if (valid) + continue; + else + printk(KERN_ERR FW_BUG PREFIX + "MMCONFIG at %pR not reserved in " + "ACPI motherboard resources\n", + &cfg->res); + } /* Don't try to do this check unless configuration type 1 is available. how about type 2 ?*/ diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index 90d5fd476ed4..a3d9c54792ae 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -64,7 +64,7 @@ err: *value = -1; if (!base) goto err; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); pci_exp_set_dev_base(base, bus, devfn); @@ -79,7 +79,7 @@ err: *value = -1; *value = mmio_config_readl(mmcfg_virt_addr + reg); break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } @@ -97,7 +97,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, if (!base) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); pci_exp_set_dev_base(base, bus, devfn); @@ -112,7 +112,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, mmio_config_writel(mmcfg_virt_addr + reg, value); break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c index 8223738ad806..5c9e2458df4e 100644 --- a/arch/x86/pci/numaq_32.c +++ b/arch/x86/pci/numaq_32.c @@ -37,7 +37,7 @@ static int pci_conf1_mq_read(unsigned int seg, unsigned int bus, if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); write_cf8(bus, devfn, reg); @@ -62,7 +62,7 @@ static int pci_conf1_mq_read(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } @@ -76,7 +76,7 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus, if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); write_cf8(bus, devfn, reg); @@ -101,7 +101,7 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } diff --git a/arch/x86/pci/pcbios.c b/arch/x86/pci/pcbios.c index 59a225c17b84..2492d165096a 100644 --- a/arch/x86/pci/pcbios.c +++ b/arch/x86/pci/pcbios.c @@ -162,7 +162,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus, if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); switch (len) { case 1: @@ -213,7 +213,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return (int)((result & 0xff00) >> 8); } @@ -228,7 +228,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus, if ((bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; - spin_lock_irqsave(&pci_config_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); switch (len) { case 1: @@ -269,7 +269,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus, break; } - spin_unlock_irqrestore(&pci_config_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return (int)((result & 0xff00) >> 8); } diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 0a979f3e5b8a..1290ba54b350 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -105,6 +105,8 @@ static void __save_processor_state(struct saved_context *ctxt) ctxt->cr4 = read_cr4(); ctxt->cr8 = read_cr8(); #endif + ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, + &ctxt->misc_enable); } /* Needed by apm.c */ @@ -152,6 +154,8 @@ static void fix_processor_context(void) */ static void __restore_processor_state(struct saved_context *ctxt) { + if (ctxt->misc_enable_saved) + wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); /* * control registers */ diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c index 987267f79bf5..a9c661108034 100644 --- a/arch/x86/xen/suspend.c +++ b/arch/x86/xen/suspend.c @@ -60,6 +60,6 @@ static void xen_vcpu_notify_restore(void *data) void xen_arch_resume(void) { - smp_call_function(xen_vcpu_notify_restore, - (void *)CLOCK_EVT_NOTIFY_RESUME, 1); + on_each_cpu(xen_vcpu_notify_restore, + (void *)CLOCK_EVT_NOTIFY_RESUME, 1); } diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h index f04c9891142f..ed8cd3cbd499 100644 --- a/arch/xtensa/include/asm/cache.h +++ b/arch/xtensa/include/asm/cache.h @@ -29,5 +29,6 @@ # define CACHE_WAY_SIZE ICACHE_WAY_SIZE #endif +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES #endif /* _XTENSA_CACHE_H */ diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h index 87cb19d1b10c..26664cef8f11 100644 --- a/arch/xtensa/include/asm/hardirq.h +++ b/arch/xtensa/include/asm/hardirq.h @@ -11,18 +11,9 @@ #ifndef _XTENSA_HARDIRQ_H #define _XTENSA_HARDIRQ_H -#include <linux/cache.h> -#include <asm/irq.h> - -/* headers.S is sensitive to the offsets of these fields */ -typedef struct { - unsigned int __softirq_pending; - unsigned int __syscall_count; - struct task_struct * __ksoftirqd_task; /* waitqueue is too large */ - unsigned int __nmi_count; /* arch dependent */ -} ____cacheline_aligned irq_cpustat_t; - void ack_bad_irq(unsigned int irq); -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ +#define ack_bad_irq ack_bad_irq + +#include <asm-generic/hardirq.h> #endif /* _XTENSA_HARDIRQ_H */ diff --git a/arch/xtensa/include/asm/scatterlist.h b/arch/xtensa/include/asm/scatterlist.h index 810080bb0a2b..b1f9fdc1d5ba 100644 --- a/arch/xtensa/include/asm/scatterlist.h +++ b/arch/xtensa/include/asm/scatterlist.h @@ -11,28 +11,7 @@ #ifndef _XTENSA_SCATTERLIST_H #define _XTENSA_SCATTERLIST_H -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - +#include <asm-generic/scatterlist.h> #define ISA_DMA_THRESHOLD (~0UL) diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index 8cd38484e130..c64a5d387de5 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -27,15 +27,6 @@ static unsigned int cached_irq_mask; atomic_t irq_err_count; /* - * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves. - */ -void ack_bad_irq(unsigned int irq) -{ - printk("unexpected IRQ trap at vector %02x\n", irq); -} - -/* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific * handlers). diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S index 74a7518faf16..70066e3582d0 100644 --- a/arch/xtensa/kernel/vectors.S +++ b/arch/xtensa/kernel/vectors.S @@ -44,14 +44,12 @@ #include <linux/linkage.h> #include <asm/ptrace.h> -#include <asm/ptrace.h> #include <asm/current.h> #include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/processor.h> #include <asm/page.h> #include <asm/thread_info.h> -#include <asm/processor.h> #define WINDOW_VECTORS_SIZE 0x180 diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c index bc0733359a88..e367e3026436 100644 --- a/arch/xtensa/mm/fault.c +++ b/arch/xtensa/mm/fault.c @@ -105,7 +105,6 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ -survive: fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) @@ -146,15 +145,10 @@ bad_area: */ out_of_memory: up_read(&mm->mmap_sem); - if (is_global_init(current)) { - yield(); - down_read(&mm->mmap_sem); - goto survive; - } - printk("VM: killing process %s\n", current->comm); - if (user_mode(regs)) - do_group_exit(SIGKILL); - bad_page_fault(regs, address, SIGKILL); + if (!user_mode(regs)) + bad_page_fault(regs, address, SIGKILL); + else + pagefault_out_of_memory(); return; do_sigbus: |