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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-08-01 18:01:35 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-08-02 16:00:00 +0200 |
| commit | d7a65c4905bc9c304ecf3d8aa566802f6119480f (patch) | |
| tree | b5965570b7a22a8087af41674033c1fa355bc86b /arch | |
| parent | arm64: dts: marvell: mark the cp110 crypto engine as dma coherent (diff) | |
| download | linux-d7a65c4905bc9c304ecf3d8aa566802f6119480f.tar.xz linux-d7a65c4905bc9c304ecf3d8aa566802f6119480f.zip | |
ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Fixes: afda007feda5 ("ARM64: dts: marvell: Add pinctrl nodes for Armada
3700")
Cc: <stable@vger.kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index dbcc3d4e2ed5..51763d674050 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -219,7 +219,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |