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| author | Kan Liang <kan.liang@linux.intel.com> | 2020-01-16 21:02:09 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2020-01-17 11:33:28 +0100 |
| commit | fa694ae532836bd2f4cd659e9b4032abaf9fa9e5 (patch) | |
| tree | 0b45b14d20150183cc1e1f23d09a1b4a85de71a6 /arch | |
| parent | perf/x86/intel/uncore: Add PCI ID of IMC for Xeon E3 V5 Family (diff) | |
| download | linux-fa694ae532836bd2f4cd659e9b4032abaf9fa9e5.tar.xz linux-fa694ae532836bd2f4cd659e9b4032abaf9fa9e5.zip | |
perf/x86/intel/uncore: Fix missing marker for snr_uncore_imc_freerunning_events
An Oops during the boot is found on some SNR machines. It turns out
this is because the snr_uncore_imc_freerunning_events[] array was
missing an end-marker.
Fixes: ee49532b38dd ("perf/x86/intel/uncore: Add IMC uncore support for Snow Ridge")
Reported-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Like Xu <like.xu@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20200116200210.18937-1-kan.liang@linux.intel.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index b10a5ec79e48..011644802ce7 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -4536,6 +4536,7 @@ static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = { INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"), INTEL_UNCORE_EVENT_DESC(write.scale, "3.814697266e-6"), INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"), + { /* end: all zeroes */ }, }; static struct intel_uncore_ops snr_uncore_imc_freerunning_ops = { |