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author | Douglas Anderson <dianders@chromium.org> | 2016-06-14 22:21:11 +0200 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2016-06-27 01:07:40 +0200 |
commit | 5d26ad9cfb2ebe2aba75342813e7542d5a68d644 (patch) | |
tree | c9de48c4b887608671f4ec135606d0d30f3f5687 /arch | |
parent | arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 (diff) | |
download | linux-5d26ad9cfb2ebe2aba75342813e7542d5a68d644.tar.xz linux-5d26ad9cfb2ebe2aba75342813e7542d5a68d644.zip |
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 74fbcce6903d..80acb382efbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1045,6 +1045,16 @@ }; }; + sleep { + ap_pwroff: ap-pwroff { + rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { + rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + spdif { spdif_bus: spdif-bus { rockchip,pins = |