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authorviresh kumar <viresh.kumar@st.com>2011-02-16 07:40:41 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-02-21 20:29:24 +0100
commit167879ae8924540660b187d759956f316dd6e8fe (patch)
tree12a2d3a27338fea50e6becd9723eb316aff19694 /arch
parentARM: 6722/1: SPEAr: sp810: switch to slow mode before reset (diff)
downloadlinux-167879ae8924540660b187d759956f316dd6e8fe.tar.xz
linux-167879ae8924540660b187d759956f316dd6e8fe.zip
ARM: 6700/1: SPEAr: Correct SOC config base address for spear320
SPEAR320_SOC_CONFIG_BASE was wrong, causing the wrong registers to be accessed. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958cd..53677e464d4b 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -62,7 +62,7 @@
#define SPEAR320_SMII1_BASE 0xAB000000
#define SPEAR320_SMII1_SIZE 0x01000000
-#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04