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authorTero Kristo <t-kristo@ti.com>2015-02-27 14:59:26 +0100
committerPaul Walmsley <paul@pwsan.com>2015-03-02 00:58:25 +0100
commit50f59d07e9822274a2e6034777eb4e90cfb30cfc (patch)
tree24a230167abaa3115fff48e4527793132d2ecbcd /arch
parentARM: OMAP2+: hwmod: fix deassert hardreset clkdm usecounting (diff)
downloadlinux-50f59d07e9822274a2e6034777eb4e90cfb30cfc.tar.xz
linux-50f59d07e9822274a2e6034777eb4e90cfb30cfc.zip
ARM: OMAP4+: PRM: fix omap4 version of prm_save_and_clear_irqen
This was incorrectly reading the irq status registers during the save and clear, instead of the irq enable. This worked because there is only one user for the prcm interrupts currently, namely the io-chain. Whenever the function was called, an io-chain interrupt was both pending and enabled. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/prm44xx.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617a6c11..d6d6bc39e05c 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -252,10 +252,10 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
{
saved_mask[0] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
- OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+ OMAP4_PRM_IRQENABLE_MPU_OFFSET);
saved_mask[1] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
- OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+ OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_OFFSET);