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authorChristophe Leroy <christophe.leroy@c-s.fr>2017-08-23 16:54:34 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2017-09-01 08:42:45 +0200
commitc0622167e3d4195d50b925bfabd8966589635e75 (patch)
treedb3f43e2dda4fe3bb0d15166fc81833c03d3a930 /arch
parentpowerpc/32: add memset16() (diff)
downloadlinux-c0622167e3d4195d50b925bfabd8966589635e75.tar.xz
linux-c0622167e3d4195d50b925bfabd8966589635e75.zip
powerpc: fix location of two EXPORT_SYMBOL
Commit 9445aa1a3062a ("ppc: move exports to definitions") added EXPORT_SYMBOL() for memset() and flush_hash_pages() in the middle of the functions. This patch moves them at the end of the two functions. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/lib/copy_32.S2
-rw-r--r--arch/powerpc/mm/hash_low_32.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index a14d4df2ebc9..a3ffeac69eca 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -104,7 +104,6 @@ _GLOBAL(memset)
subf r6,r0,r6
cmplwi 0,r4,0
bne 2f /* Use normal procedure if r4 is not zero */
-EXPORT_SYMBOL(memset)
_GLOBAL(memset_nocache_branch)
b 2f /* Skip optimised bloc until cache is enabled */
@@ -140,6 +139,7 @@ _GLOBAL(memset_nocache_branch)
8: stbu r4,1(r6)
bdnz 8b
blr
+EXPORT_SYMBOL(memset)
/*
* This version uses dcbz on the complete cache lines in the
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 6f962e5cb5e1..ffbd7c0bda96 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -575,7 +575,6 @@ _GLOBAL(flush_hash_pages)
rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
stwcx. r8,0,r5 /* update the pte */
bne- 33b
-EXPORT_SYMBOL(flush_hash_pages)
/* Get the address of the primary PTE group in the hash table (r3) */
_GLOBAL(flush_hash_patch_A)
@@ -634,6 +633,7 @@ _GLOBAL(flush_hash_patch_B)
SYNC_601
isync
blr
+EXPORT_SYMBOL(flush_hash_pages)
/*
* Flush an entry from the TLB