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authorGraf Yang <graf.yang@analog.com>2008-10-09 08:17:47 +0200
committerBryan Wu <cooloney@kernel.org>2008-10-09 08:17:47 +0200
commitdd4354fa51f6379fb3ac98ba9377ca5895f50497 (patch)
treefc4094e9b90adcfd33e33f84911893f3eae2b067 /arch
parentBlackfin arch: Make L2 SRAM cacheable (diff)
downloadlinux-dd4354fa51f6379fb3ac98ba9377ca5895f50497.tar.xz
linux-dd4354fa51f6379fb3ac98ba9377ca5895f50497.zip
Blackfin arch: fix define error in BF561 memory map macros
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 9d6674ad1e5e..f1d4c0637bd2 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -35,14 +35,14 @@
/* Memory Map for ADSP-BF561 processors */
#ifdef CONFIG_BF561
-#define COREA_L1_CODE_START 0xFFA00000
+#define COREA_L1_CODE_START 0xFFA00000
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF500000
-#define COREB_L1_DATA_B_START 0xFF400000
+#define COREB_L1_CODE_START 0xFF600000
+#define COREB_L1_DATA_A_START 0xFF400000
+#define COREB_L1_DATA_B_START 0xFF500000
-#define L1_CODE_START COREA_L1_CODE_START
+#define L1_CODE_START COREA_L1_CODE_START
#define L1_DATA_A_START COREA_L1_DATA_A_START
#define L1_DATA_B_START COREA_L1_DATA_B_START