diff options
| author | Paul Mackerras <paulus@samba.org> | 2013-06-22 09:15:24 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-06-30 03:33:22 +0200 |
| commit | 681562cd56f5336cbdf6dab0c4b2f6ef16ea89ed (patch) | |
| tree | c18bfe66e7f4f84b513580a728fee764c1ed2337 /arch | |
| parent | KVM: PPC: Book3S PR: Allow guest to use 1TB segments (diff) | |
| download | linux-681562cd56f5336cbdf6dab0c4b2f6ef16ea89ed.tar.xz linux-681562cd56f5336cbdf6dab0c4b2f6ef16ea89ed.zip | |
KVM: PPC: Book3S PR: Invalidate SLB entries properly
At present, if the guest creates a valid SLB (segment lookaside buffer)
entry with the slbmte instruction, then invalidates it with the slbie
instruction, then reads the entry with the slbmfee/slbmfev instructions,
the result of the slbmfee will have the valid bit set, even though the
entry is not actually considered valid by the host. This is confusing,
if not worse. This fixes it by zeroing out the orige and origv fields
of the SLB entry structure when the entry is invalidated.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kvm/book3s_64_mmu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index ee435ba6b92a..739bfbadb85e 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -397,6 +397,8 @@ static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea) dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid); slbe->valid = false; + slbe->orige = 0; + slbe->origv = 0; seg_size = 1ull << kvmppc_slb_sid_shift(slbe); kvmppc_mmu_flush_segment(vcpu, ea & ~(seg_size - 1), seg_size); @@ -408,8 +410,11 @@ static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu) dprintk("KVM MMU: slbia()\n"); - for (i = 1; i < vcpu->arch.slb_nr; i++) + for (i = 1; i < vcpu->arch.slb_nr; i++) { vcpu->arch.slb[i].valid = false; + vcpu->arch.slb[i].orige = 0; + vcpu->arch.slb[i].origv = 0; + } if (vcpu->arch.shared->msr & MSR_IR) { kvmppc_mmu_flush_segments(vcpu); |