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authorGrygorii Strashko <grygorii.strashko@ti.com>2019-11-18 13:20:16 +0100
committerTony Lindgren <tony@atomide.com>2019-11-20 18:42:33 +0100
commit6af0a549c25e0d02366aa95507bfe3cad2f7b68b (patch)
tree6d6f56161a8d6bc9cd08cbbbbc8e0328d2864ab1 /arch
parentARM: dts: am57xx-beagle-x15: Update pinmux name to ddr_3_3v (diff)
downloadlinux-6af0a549c25e0d02366aa95507bfe3cad2f7b68b.tar.xz
linux-6af0a549c25e0d02366aa95507bfe3cad2f7b68b.zip
ARM: dts: dra7: fix cpsw mdio fck clock
The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) is specified incorrectly, which is caused incorrect MDIO bus clock configuration MDCLK. The correct CPSW MDIO functional clock is gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. Fixes: 1faa415c9c6e ("ARM: dts: Add fck for cpsw mdio for omap variants") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index ea0e7c19eb4e..be5c505eaea9 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -3065,7 +3065,7 @@
davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
+ clocks = <&gmac_main_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;