diff options
| author | Enze Li <lienze@kylinos.cn> | 2023-04-19 06:07:27 +0200 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-04-19 06:07:27 +0200 |
| commit | 213ef669d1e536e57cdff8ddc2d3b9347b98e35f (patch) | |
| tree | 262b00103a9b5d538852c2c6825416dd54f8d4cf /arch | |
| parent | LoongArch: Clean up plat_swiotlb_setup() related code (diff) | |
| download | linux-213ef669d1e536e57cdff8ddc2d3b9347b98e35f.tar.xz linux-213ef669d1e536e57cdff8ddc2d3b9347b98e35f.zip | |
LoongArch: Replace hard-coded values in comments with VALEN
According to LoongArch documentation [1], CSR.PGDL and CSR.PGDH are
concerned with the VA's MSB which is VALEN-1 instead of always being 47.
Fix comments to avoid misleading others.
[1] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#page-global-directory-base-address-for-lower-half-address-space
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Enze Li <lienze@kylinos.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/loongarch/include/asm/loongarch.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 8c2969965c3c..83da5d29e2d1 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -423,9 +423,9 @@ static __always_inline void iocsr_write64(u64 val, u32 reg) #define CSR_ASID_ASID_WIDTH 10 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT) -#define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[47] = 0 */ +#define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */ -#define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[47] = 1 */ +#define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */ #define LOONGARCH_CSR_PGD 0x1b /* Page table base */ |