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authorFabrizio Castro <fabrizio.castro@bp.renesas.com>2017-10-16 12:12:49 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-10-18 07:21:36 +0200
commitb6d3b649441936621c87b79bff8dd436e2397e3c (patch)
tree319b76080b8e4eca4e046bb81b5e603465a7e24c /arch
parentARM: dts: r7s72100: Add clock for CA9 CPU core (diff)
downloadlinux-b6d3b649441936621c87b79bff8dd436e2397e3c.tar.xz
linux-b6d3b649441936621c87b79bff8dd436e2397e3c.zip
ARM: dts: r8a7743: Add xhci support to SoC dtsi
Add node for xhci. Boards DT files will enable it if needed. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/r8a7743.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 4db4f61be25a..7bbba4a36f31 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -932,6 +932,26 @@
status = "disabled";
};
+ /*
+ * pci1 and xhci share the same phy, therefore only one of them
+ * can be active at any one time. If both of them are enabled,
+ * a race condition will determine who'll control the phy.
+ * A firmware file is needed by the xhci driver in order for
+ * USB 3.0 to work properly.
+ */
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7743",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7743";
reg = <0 0xee100000 0 0x328>;