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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-12-30 08:40:17 +0100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-01-15 03:20:07 +0100
commite443ed35606cf921cbf9d6949010a5b36bbe747d (patch)
tree91839698bc14c32da9f191c41810067f0e5a1143 /arch
parentpowerpc/8xx: Always pin kernel instruction TLB (diff)
downloadlinux-e443ed35606cf921cbf9d6949010a5b36bbe747d.tar.xz
linux-e443ed35606cf921cbf9d6949010a5b36bbe747d.zip
powerpc/swsusp_32: Fix TLB invalidation
It seems there is a thinko in the TLB invalidation code that makes the tlbie in the loop executed just once. The intended check was probably 'gt', not 'lt'. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/swsusp_32.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index b47d8ceffb52..b0754e237438 100644
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -303,7 +303,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
lis r4,0x1000
1: addic. r4,r4,-0x1000
tlbie r4
- blt 1b
+ bgt 1b
sync
/* restore the MSR and turn on the MMU */