diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-09-04 11:48:58 +0200 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 04:06:47 +0200 |
| commit | aec247d4ac578693ee75ac2bf10eac1c29299c45 (patch) | |
| tree | 43ea4eacbe55e7f25ad6b5d8bce54f691e92f5a7 /arch | |
| parent | ARM: clk-imx6sl: correct the pxp and epdc axi clock selections (diff) | |
| download | linux-aec247d4ac578693ee75ac2bf10eac1c29299c45.tar.xz linux-aec247d4ac578693ee75ac2bf10eac1c29299c45.zip | |
ARM: clk-imx6q: refine clock tree for ASRC
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share
the same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2edcebf67cee..d5bf1e2940bf 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -107,6 +107,7 @@ static struct clk_div_table video_div_table[] = { }; static unsigned int share_count_esai; +static unsigned int share_count_asrc; static void __init imx6q_clocks_init(struct device_node *ccm_node) { @@ -317,7 +318,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* name parent_name reg shift */ clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); - clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); + clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); + clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); + clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); |