diff options
| author | Joe Perches <joe@perches.com> | 2007-12-19 02:02:21 +0100 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-12-19 02:02:21 +0100 |
| commit | 313d8e57b074d5f03dfed2755f21ae41a6f0fd5a (patch) | |
| tree | d2eac737118e16b8bb05f18ca3f5a79856188906 /arch | |
| parent | [IA64] Avoid unnecessary TLB flushes when allocating memory (diff) | |
| download | linux-313d8e57b074d5f03dfed2755f21ae41a6f0fd5a.tar.xz linux-313d8e57b074d5f03dfed2755f21ae41a6f0fd5a.zip | |
[IA64] Two trivial spelling fixes
s/addres/address/
s/performanc/performance/
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ia64/sn/pci/tioce_provider.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c index cee9379d44e0..e1a3e19d3d9c 100644 --- a/arch/ia64/sn/pci/tioce_provider.c +++ b/arch/ia64/sn/pci/tioce_provider.c @@ -41,7 +41,7 @@ * } else * do desired mmr access * - * According to hw, we can use reads instead of writes to the above addres + * According to hw, we can use reads instead of writes to the above address * * Note this WAR can only to be used for accessing internal MMR's in the * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the |