diff options
| author | Kan Liang <kan.liang@intel.com> | 2017-11-14 15:06:40 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-11-14 17:07:49 +0100 |
| commit | bb9fbe1b57503f790dbbf9f06e72cb0fb9e60740 (patch) | |
| tree | cbe021075474b56bcce6d7f5d045c206fc9c6daa /arch | |
| parent | perf/x86/intel: Hide TSX events when RTM is not supported (diff) | |
| download | linux-bb9fbe1b57503f790dbbf9f06e72cb0fb9e60740.tar.xz linux-bb9fbe1b57503f790dbbf9f06e72cb0fb9e60740.zip | |
perf/x86/intel/uncore: Add event constraint for BDX PCU
Event select bit 7 'Use Occupancy' in PCU Box is not available for
counter 0 on BDX
Add a constraint to fix it.
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: ak@linux.intel.com
Link: https://lkml.kernel.org/r/1510668400-301000-1-git-send-email-kan.liang@intel.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 95cb19f4e06f..f4e4168455a8 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3035,11 +3035,19 @@ static struct intel_uncore_type *bdx_msr_uncores[] = { NULL, }; +/* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */ +static struct event_constraint bdx_uncore_pcu_constraints[] = { + EVENT_CONSTRAINT(0x80, 0xe, 0x80), + EVENT_CONSTRAINT_END +}; + void bdx_uncore_cpu_init(void) { if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; uncore_msr_uncores = bdx_msr_uncores; + + hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints; } static struct intel_uncore_type bdx_uncore_ha = { |