diff options
| author | Douglas Anderson <dianders@chromium.org> | 2020-02-03 19:31:36 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-02-25 06:02:28 +0100 |
| commit | 0997882f96c784927bcd368dd7e800d3623fc27d (patch) | |
| tree | 3640667ac21e7fe45cb0031cab690050b180f599 /arch | |
| parent | arm64: dts: qcom: qcs404: Fix sdhci compat string (diff) | |
| download | linux-0997882f96c784927bcd368dd7e800d3623fc27d.tar.xz linux-0997882f96c784927bcd368dd7e800d3623fc27d.zip | |
arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc
We're transitioning over to requiring the Qualcomm Display Clock
Controller to specify all the input clocks. Let's add them for
sdm845.
NOTES:
- Until the Linux driver for sdm845's dispcc is updated, these clocks
will not actually be used in Linux. It will continue to use global
clock names to match things up.
- Although the clocks from the DP PHY are required, the DP PHY isn't
represented in the dts yet. Apparently the magic for this is just
to use <0>.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index dbbf2b1b204e..7a7835bdf630 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3145,6 +3145,24 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; |