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| author | Andi Kleen <ak@linux.intel.com> | 2021-12-15 21:40:29 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-01-18 12:09:49 +0100 |
| commit | 8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc (patch) | |
| tree | fda5f034b2e7c8d18ee79a72d1c09a239ab88aaf /arch | |
| parent | perf/x86/intel/uncore: Add IMC uncore support for ADL (diff) | |
| download | linux-8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc.tar.xz linux-8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc.zip | |
x86/perf: Avoid warning for Arch LBR without XSAVE
Some hypervisors support Arch LBR, but without the LBR XSAVE support.
The current Arch LBR init code prints a warning when the xsave size (0) is
unexpected. Avoid printing the warning for the "no LBR XSAVE" case.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20211215204029.150686-1-ak@linux.intel.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/intel/lbr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index f8fd25528935..669c2be14784 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1751,6 +1751,9 @@ static bool is_arch_lbr_xsave_available(void) * Check the LBR state with the corresponding software structure. * Disable LBR XSAVES support if the size doesn't match. */ + if (xfeature_size(XFEATURE_LBR) == 0) + return false; + if (WARN_ON(xfeature_size(XFEATURE_LBR) != get_lbr_state_size())) return false; |