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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2019-02-21 20:08:52 +0100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2019-02-23 11:04:32 +0100 |
| commit | 8f54a6f7406ee3b7b528c3ff569f6a51295b2608 (patch) | |
| tree | a1d056a8298d442a492a2830d8f612c342732665 /arch | |
| parent | powerpc/8xx: don't disable large TLBs with CONFIG_STRICT_KERNEL_RWX (diff) | |
| download | linux-8f54a6f7406ee3b7b528c3ff569f6a51295b2608.tar.xz linux-8f54a6f7406ee3b7b528c3ff569f6a51295b2608.zip | |
powerpc/kconfig: make _etext and data areas alignment configurable on 8xx
On 8xx, large pages (512kb or 8M) are used to map kernel linear
memory. Aligning to 8M reduces TLB misses as only 8M pages are used
in that case. We make 8M the default for data.
This patchs allows the user to do it via Kconfig.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/Kconfig | 18 | ||||
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 4 |
2 files changed, 17 insertions, 5 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 43fa82e409bf..ad8e22827de0 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -722,7 +722,8 @@ config THREAD_SHIFT want. Only change this if you know what you are doing. config ETEXT_SHIFT_BOOL - bool "Set custom etext alignment" if STRICT_KERNEL_RWX && PPC_BOOK3S_32 + bool "Set custom etext alignment" if STRICT_KERNEL_RWX && \ + (PPC_BOOK3S_32 || PPC_8xx) depends on ADVANCED_OPTIONS help This option allows you to set the kernel end of text alignment. When @@ -734,6 +735,7 @@ config ETEXT_SHIFT_BOOL config ETEXT_SHIFT int "_etext shift" if ETEXT_SHIFT_BOOL range 17 28 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 + range 19 23 if STRICT_KERNEL_RWX && PPC_8xx default 17 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 default 19 if STRICT_KERNEL_RWX && PPC_8xx default PPC_PAGE_SHIFT @@ -741,8 +743,13 @@ config ETEXT_SHIFT On Book3S 32 (603+), IBATs are used to map kernel text. Smaller is the alignment, greater is the number of necessary IBATs. + On 8xx, large pages (512kb or 8M) are used to map kernel linear + memory. Aligning to 8M reduces TLB misses as only 8M pages are used + in that case. + config DATA_SHIFT_BOOL - bool "Set custom data alignment" if STRICT_KERNEL_RWX && PPC_BOOK3S_32 + bool "Set custom data alignment" if STRICT_KERNEL_RWX && \ + (PPC_BOOK3S_32 || PPC_8xx) depends on ADVANCED_OPTIONS help This option allows you to set the kernel data alignment. When @@ -755,13 +762,18 @@ config DATA_SHIFT int "Data shift" if DATA_SHIFT_BOOL default 24 if STRICT_KERNEL_RWX && PPC64 range 17 28 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 + range 19 23 if STRICT_KERNEL_RWX && PPC_8xx default 22 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 - default 19 if STRICT_KERNEL_RWX && PPC_8xx + default 23 if STRICT_KERNEL_RWX && PPC_8xx default PPC_PAGE_SHIFT help On Book3S 32 (603+), DBATs are used to map kernel text and rodata RO. Smaller is the alignment, greater is the number of necessary DBATs. + On 8xx, large pages (512kb or 8M) are used to map kernel linear + memory. Aligning to 8M reduces TLB misses as only 8M pages are used + in that case. + config FORCE_MAX_ZONEORDER int "Maximum zone order" range 8 9 if PPC64 && PPC_64K_PAGES diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3f2d1afba2d1..50303d25cbc1 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -416,7 +416,7 @@ InstructionTLBMiss: #ifndef CONFIG_PIN_TLB_TEXT ITLBMissLinear: mtcr r11 -#ifdef CONFIG_STRICT_KERNEL_RWX +#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23 patch_site 0f, patch__itlbmiss_linmem_top8 mfspr r10, SPRN_SRR0 @@ -537,7 +537,7 @@ DTLBMissIMMR: DTLBMissLinear: mtcr r11 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */ -#ifdef CONFIG_STRICT_KERNEL_RWX +#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23 patch_site 0f, patch__dtlbmiss_romem_top8 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha |