diff options
author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-04-05 14:59:02 +0200 |
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committer | Kevin Hilman <khilman@linaro.org> | 2013-04-09 19:53:06 +0200 |
commit | baf4b7d3436be7e8c8ff5bd58acc51a9b07e1871 (patch) | |
tree | a73aa055caeb007cc53ebe03883c9d3aa21379d1 /arch | |
parent | ARM: OMAP4+: PM: Consolidate MPU subsystem PM code for re-use (diff) | |
download | linux-baf4b7d3436be7e8c8ff5bd58acc51a9b07e1871.tar.xz linux-baf4b7d3436be7e8c8ff5bd58acc51a9b07e1871.zip |
ARM: OMAP4+: Make secondary_startup function name more consistent
Current code has rather inconsistent function names for 'secondary_startup'
routines. Update it to make it more consistent.
Suggested by Kevin Hilman as part of OMAP5 PM patch review.
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/common.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 8 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap-mpuss-lowpower.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap-smp.c | 6 |
4 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 40f4a03d728f..1a568482a107 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -230,8 +230,8 @@ extern void omap_do_wfi(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern void omap_secondary_startup_4460(void); +extern void omap4_secondary_startup(void); +extern void omap4460_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 0ea09faf327b..4ea308114165 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -49,7 +49,7 @@ END(omap5_secondary_startup) * The primary core will update this flag using a hardware * register AuxCoreBoot0. */ -ENTRY(omap_secondary_startup) +ENTRY(omap4_secondary_startup) hold: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -64,9 +64,9 @@ hold: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup) +ENDPROC(omap4_secondary_startup) -ENTRY(omap_secondary_startup_4460) +ENTRY(omap4460_secondary_startup) hold_2: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup_4460) +ENDPROC(omap4460_secondary_startup) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 8e7029269d8a..d4322aa3192e 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -324,7 +324,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) /* * CPU never retuns back if targeted power state is OFF mode. * CPU ONLINE follows normal CPU ONLINE ptah via - * omap_secondary_startup(). + * omap4_secondary_startup(). */ omap_pm_ops.finish_suspend(cpu_state); @@ -370,9 +370,9 @@ int __init omap4_mpuss_init(void) pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; if (cpu_is_omap446x()) - pm_info->secondary_startup = omap_secondary_startup_4460; + pm_info->secondary_startup = omap4460_secondary_startup; else - pm_info->secondary_startup = omap_secondary_startup; + pm_info->secondary_startup = omap4_secondary_startup; pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); if (!pm_info->pwrdm) { diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 0cbb677c4df4..5b201653ca32 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -93,7 +93,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * /* * Update the AuxCoreBoot0 with boot state for secondary core. - * omap_secondary_startup() routine will hold the secondary core till + * omap4_secondary_startup() routine will hold the secondary core till * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ @@ -199,7 +199,7 @@ static void __init omap4_smp_init_cpus(void) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { - void *startup_addr = omap_secondary_startup; + void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); /* @@ -210,7 +210,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); if (cpu_is_omap446x()) { - startup_addr = omap_secondary_startup_4460; + startup_addr = omap4460_secondary_startup; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; } |