diff options
author | Arnd Bergmann <arnd@arndb.de> | 2023-02-06 20:48:40 +0100 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2023-02-06 20:48:41 +0100 |
commit | cfd5bdf3e98e3d21d7f57ad0b76001aa1ab78d66 (patch) | |
tree | b476354e59dc6e3886e7fa34aa27c8878448d31c /arch | |
parent | Merge tag 'ti-k3-dt-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/... (diff) | |
parent | arm64: dts: socfpga: change address-cells to support 64-bit addressing (diff) | |
download | linux-cfd5bdf3e98e3d21d7f57ad0b76001aa1ab78d66.tar.xz linux-cfd5bdf3e98e3d21d7f57ad0b76001aa1ab78d66.zip |
Merge tag 'socfpga_dts_updates_for_v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v6.3
- Align UART node with bindings
- Add pinctrl properties for Stratix10/Agilex
- Change address-cells to 2 to support 64-bit address for fpga region
* tag 'socfpga_dts_updates_for_v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: change address-cells to support 64-bit addressing
arm64: dts: stratix10: add i2c pins for pinctrl
arm64: dts: add pinctrl-single property for Stratix10/Agilex
ARM: dts: socfpga: align UART node name with bindings
Link: https://lore.kernel.org/r/20230206162425.311593-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/socfpga_vt.dts | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 21 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 23 | ||||
-rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 19 |
6 files changed, 64 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 3fee80bbae21..4c1d140f40f8 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -905,7 +905,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; interrupts = <0 162 4>; @@ -918,7 +918,7 @@ resets = <&rst UART0_RESET>; }; - uart1: serial1@ffc03000 { + uart1: serial@ffc03000 { compatible = "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; interrupts = <0 163 4>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3b2a2c9c6547..72c55e5187ca 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -845,7 +845,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x100>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -856,7 +856,7 @@ status = "disabled"; }; - uart1: serial1@ffc02100 { + uart1: serial@ffc02100 { compatible = "snps,dw-apb-uart"; reg = <0xffc02100 0x100>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 3d0d806888b7..845ab2cc5ce6 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -57,11 +57,11 @@ clock-frequency = <7000000>; }; - serial0@ffc02000 { + serial@ffc02000 { clock-frequency = <7372800>; }; - serial1@ffc03000 { + serial@ffc03000 { clock-frequency = <7372800>; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 55c5e1fdddc7..41c9eb51d0ee 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -134,9 +134,8 @@ ranges = <0 0 0 0xffffffff>; base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - + #address-cells = <0x2>; + #size-cells = <0x2>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; }; @@ -353,6 +352,22 @@ reset-names = "dma", "dma-ocp"; }; + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + reg = <0xffd13000 0xA0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinctrl@ffd13100 { + compatible = "pinctrl-single"; + reg = <0xffd13100 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,stratix10-rst-mgr"; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 17752ca743e5..38ae674f2f02 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -65,6 +65,22 @@ }; }; +&pinctrl0 { + i2c1_pmx_func: i2c1-pmx-func { + pinctrl-single,pins = < + 0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; + + i2c1_pmx_func_gpio: i2c1-pmx-func-gpio { + pinctrl-single,pins = < + 0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; +}; + &gpio1 { status = "okay"; }; @@ -131,6 +147,13 @@ i2c-sda-falling-time-ns = <890>; /* hcnt */ i2c-sdl-falling-time-ns = <890>; /* lcnt */ + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pmx_func>; + pinctrl-1 = <&i2c1_pmx_func_gpio>; + + scl-gpios = <&portb 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&portb 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + adc@14 { compatible = "lltc,ltc2497"; reg = <0x14>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 849b46dd8098..f9674cc46764 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -139,8 +139,8 @@ ranges = <0 0 0 0xffffffff>; base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; }; @@ -357,6 +357,21 @@ clock-names = "apb_pclk"; }; + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13000 0xa0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinconf@ffd13100 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13100 0x20>; + pinctrl-single,register-width = <32>; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,stratix10-rst-mgr"; |