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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-04-04 19:21:35 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-04-05 19:41:12 +0200 |
| commit | de6e05097f7db066afb0ad4c88b730949f7b7749 (patch) | |
| tree | 6f73b5d36b92c2df8dfbf44438360f1480f0be90 /block/blk-merge.c | |
| parent | nvmem: stm32-romem: mark OF related data as maybe unused (diff) | |
| download | linux-de6e05097f7db066afb0ad4c88b730949f7b7749.tar.xz linux-de6e05097f7db066afb0ad4c88b730949f7b7749.zip | |
nvmem: mtk-efuse: Support postprocessing for GPU speed binning data
On some MediaTek SoCs GPU speed binning data is available for read
in the SoC's eFuse array but it has a format that is incompatible
with what the OPP API expects, as we read a number from 0 to 7 but
opp-supported-hw is expecting a bitmask to enable an OPP entry:
being what we read limited to 0-7, it's straightforward to simply
convert the value to BIT(value) as a post-processing action.
So, introduce post-processing support and enable it by evaluating
the newly introduced platform data's `uses_post_processing` member,
currently enabled only for MT8186.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20230404172148.82422-28-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'block/blk-merge.c')
0 files changed, 0 insertions, 0 deletions