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| author | Alexey Firago <alexey_firago@mentor.com> | 2017-04-07 11:12:23 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-19 18:08:48 +0200 |
| commit | a330b6f5d1aee83fb2554d00ad33877b91a74c0c (patch) | |
| tree | 9d5288e5e49b7cd9a346cd12f01a2422ae3437af /block | |
| parent | clk: vc5: Add structure to describe particular chip features (diff) | |
| download | linux-a330b6f5d1aee83fb2554d00ad33877b91a74c0c.tar.xz linux-a330b6f5d1aee83fb2554d00ad33877b91a74c0c.zip | |
clk: vc5: Add bindings for IDT VersaClock 5P49V5935
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either integrated crystal or from
external reference clock.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'block')
0 files changed, 0 insertions, 0 deletions