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authorKishon Vijay Abraham I <kishon@ti.com>2014-07-14 12:42:18 +0200
committerTony Lindgren <tony@atomide.com>2014-07-15 09:16:11 +0200
commitba5137b27281f9016a5b2f6177f02595252305bd (patch)
tree24b65779ae592f073edb3008d037b8de4429fa84 /block
parentARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pc... (diff)
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ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Added missing 32KHz clock used by PCIe PHY. Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows 32KHz is used by PCIe PHY. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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