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| author | Daniel Thompson <daniel.thompson@linaro.org> | 2016-08-19 18:13:09 +0200 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-09-12 20:46:19 +0200 |
| commit | 91ef84428a86b75a52e15c6fe4f56b446ba75f93 (patch) | |
| tree | 46066d44e3ddccef1b4d0056955eb59ffc67cf54 /block | |
| parent | irqchip/gic: Make locking a BL_SWITCHER only feature (diff) | |
| download | linux-91ef84428a86b75a52e15c6fe4f56b446ba75f93.tar.xz linux-91ef84428a86b75a52e15c6fe4f56b446ba75f93.zip | |
irqchip/gic-v3: Reset BPR during initialization
Currently, when running on FVP, CPU 0 boots up with its BPR changed from
the reset value. This renders it impossible to (preemptively) prioritize
interrupts on CPU 0.
This is harmless on normal systems since Linux typically does not
support preemptive interrupts. It does however cause problems in
systems with additional changes (such as patches for NMI simulation).
Many thanks to Andrew Thoelke for suggesting the BPR as having the
potential to harm preemption.
Suggested-by: Andrew Thoelke <andrew.thoelke@arm.com>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'block')
0 files changed, 0 insertions, 0 deletions