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| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-12-09 10:49:16 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-16 21:23:13 +0100 |
| commit | 732374a0b440d9a79c8412f318a25cd37ba6f4e2 (patch) | |
| tree | 8ad203562671d443b0087ec9cb92f2d57ea32072 /certs | |
| parent | clk: sifive: Fix the wrong bit field shift (diff) | |
| download | linux-732374a0b440d9a79c8412f318a25cd37ba6f4e2.tar.xz linux-732374a0b440d9a79c8412f318a25cd37ba6f4e2.zip | |
clk: sifive: Add clock enable and disable ops
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Zong Li <zong.li@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-6-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'certs')
0 files changed, 0 insertions, 0 deletions