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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 02:42:53 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 02:42:53 +0200 |
| commit | 83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 (patch) | |
| tree | bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce /crypto/async_tx/async_pq.c | |
| parent | dmaengine: cleanup unused transaction types (diff) | |
| download | linux-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.tar.xz linux-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.zip | |
dmaengine, async_tx: support alignment checks
Some engines have transfer size and address alignment restrictions. Add
a per-operation alignment property to struct dma_device that the async
routines and dmatest can use to check alignment capabilities.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'crypto/async_tx/async_pq.c')
| -rw-r--r-- | crypto/async_tx/async_pq.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/crypto/async_tx/async_pq.c b/crypto/async_tx/async_pq.c index a25e290c39fb..b88db6d1dc65 100644 --- a/crypto/async_tx/async_pq.c +++ b/crypto/async_tx/async_pq.c @@ -211,7 +211,8 @@ async_gen_syndrome(struct page **blocks, unsigned int offset, int disks, if (dma_src && device && (src_cnt <= dma_maxpq(device, 0) || - dma_maxpq(device, DMA_PREP_CONTINUE) > 0)) { + dma_maxpq(device, DMA_PREP_CONTINUE) > 0) && + is_dma_pq_aligned(device, offset, 0, len)) { /* run the p+q asynchronously */ pr_debug("%s: (async) disks: %d len: %zu\n", __func__, disks, len); @@ -274,7 +275,8 @@ async_syndrome_val(struct page **blocks, unsigned int offset, int disks, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) blocks; - if (dma_src && device && disks <= dma_maxpq(device, 0)) { + if (dma_src && device && disks <= dma_maxpq(device, 0) && + is_dma_pq_aligned(device, offset, 0, len)) { struct device *dev = device->dev; dma_addr_t *pq = &dma_src[disks-2]; int i; |