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| author | Stefan Agner <stefan@agner.ch> | 2017-06-09 00:34:47 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-20 04:02:41 +0200 |
| commit | 22039d150f716e4e56215d70ad23fb92caa4476e (patch) | |
| tree | 1821f452251a54adf1e15b0827811fc2b4fe230f /crypto/blowfish_common.c | |
| parent | clk: hi3660: Set PPLL2 to 2880M (diff) | |
| download | linux-22039d150f716e4e56215d70ad23fb92caa4476e.tar.xz linux-22039d150f716e4e56215d70ad23fb92caa4476e.zip | |
clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.
Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'crypto/blowfish_common.c')
0 files changed, 0 insertions, 0 deletions