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authorJoel Stanley <joel@jms.id.au>2016-08-30 09:54:27 +0200
committerLinus Walleij <linus.walleij@linaro.org>2016-09-07 16:56:47 +0200
commit361b79119a4b7f53f728913b5ed2c8d2d10c16f5 (patch)
treebb31d4df905d64d1973d3ab9a97bd3ee73d6abc7 /crypto/tcrypt.c
parentgpio: dt-bindings: Add documentation for Aspeed GPIO controllers (diff)
downloadlinux-361b79119a4b7f53f728913b5ed2c8d2d10c16f5.tar.xz
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gpio: Add Aspeed driver
The Aspeed SoCs contain GPIOs banked by letter, where each bank contains 8 pins. The GPIO banks are then grouped in sets of four in the register layout. The implementation exposes multiple banks through the one driver and requests and releases pins via the pinctrl subsystem. The hardware supports generation of interrupts from all GPIO-capable pins. A number of hardware features are not yet supported: Configuration of interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance for output ports. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'crypto/tcrypt.c')
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