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| author | Fatemeh Darbehani <fatemeh.darbehani@amd.com> | 2019-06-21 23:44:50 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 21:18:10 +0200 |
| commit | 7e6472966e8341bf72f558babfdafac8aeff3257 (patch) | |
| tree | 87979c12fff0c6bebfa82e31fedf31f6c6ab3dd1 /crypto | |
| parent | drm/amd/display: Remove second initialization of pp_smu (diff) | |
| download | linux-7e6472966e8341bf72f558babfdafac8aeff3257.tar.xz linux-7e6472966e8341bf72f558babfdafac8aeff3257.zip | |
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why]
Some display's hsync width is lower than the minimum dcn20 is set
to support right now. This will cause optc1_validate_timing to fail which
eventually will result in wrong set mode. This was set to 8 as per
HW team's request for no valid reason.
[How]
Changing min_h_sync_width to 4 will let us validate timing for
preffered mode and light up the headset. This change was made
to Vega 10 before for a similar issue.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions