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authorJisheng Zhang <jszhang@marvell.com>2014-12-26 09:58:00 +0100
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2015-01-07 15:25:37 +0100
commit2356d2f3d1b742dacdeb1b0a038ec17f7cc2947f (patch)
tree5f585ee3d51a35832bd440e1a2520a2174ec00fc /crypto
parentARM: dts: berlin: add pmu node for BG2Q and BG2CD (diff)
downloadlinux-2356d2f3d1b742dacdeb1b0a038ec17f7cc2947f.tar.xz
linux-2356d2f3d1b742dacdeb1b0a038ec17f7cc2947f.zip
ARM: dts: berlin: add PPI cpu mask to twd timer interrupts
According to the gic binding document, "bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of the 8 possible cpus attached to the GIC. A bit set to '1' indicated the interrupt is wired to that CPU." This patch wants to add the PPI cpu mask for completeness. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'crypto')
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