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authorBrian Norris <computersforpeace@gmail.com>2011-08-31 03:45:37 +0200
committerArtem Bityutskiy <artem.bityutskiy@intel.com>2011-09-11 14:02:18 +0200
commit9ce244b3fb416ce6600e05612ac46b9692dcc638 (patch)
tree34b9b77f38ce65f8efe9f9f40e71efd22bc43507 /crypto
parentmtd: add the common code for GPMI-NAND controller driver (diff)
downloadlinux-9ce244b3fb416ce6600e05612ac46b9692dcc638.tar.xz
linux-9ce244b3fb416ce6600e05612ac46b9692dcc638.zip
mtd: support writing OOB without ECC
This fixes issues with `nandwrite -n -o' and the MEMWRITEOOB[64] ioctls on hardware that writes ECC when writing OOB. The problem arises as follows: `nandwrite -n' can write page data to flash without applying ECC, but when used with the `-o' option, ECC is applied (incorrectly), contrary to the `--noecc' option. I found that this is the case because my hardware computes and writes ECC data to flash upon either OOB write or page write. Thus, to support a proper "no ECC" write, my driver must know when we're performing a raw OOB write vs. a normal ECC OOB write. However, MTD does not pass any raw mode information to the write_oob functions. This patch addresses the problems by: 1) Passing MTD_OOB_RAW down to lower layers, instead of just defaulting to MTD_OOB_PLACE 2) Handling MTD_OOB_RAW within the NAND layer's `nand_do_write_oob' 3) Adding a new (replaceable) function pointer in struct ecc_ctrl; this function should support writing OOB without ECC data. Current hardware often can use the same OOB write function when writing either with or without ECC This was tested with nandsim as well as on actual SLC NAND. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
Diffstat (limited to 'crypto')
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