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| author | davidwang <davidwang@zhaoxin.com> | 2018-01-22 11:14:17 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-01-24 13:38:10 +0100 |
| commit | fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d (patch) | |
| tree | 7a8ad4a75e7aa384ae1011ed6abd7d6bd8d502b0 /drivers/acpi | |
| parent | x86/tsc: Introduce early tsc clocksource (diff) | |
| download | linux-fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d.tar.xz linux-fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d.zip | |
x86/centaur: Mark TSC invariant
Centaur CPU has a constant frequency TSC and that TSC does not stop in
C-States. But because the corresponding TSC feature flags are not set for
that CPU, the TSC is treated as not constant frequency and assumed to stop
in C-States, which makes it an unreliable and unusable clock source.
Setting those flags tells the kernel that the TSC is usable, so it will
select it over HPET. The effect of this is that reading time stamps (from
kernel or user space) will be faster and more efficent.
Signed-off-by: davidwang <davidwang@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: qiyuanwang@zhaoxin.com
Cc: linux-pm@vger.kernel.org
Cc: brucechang@via-alliance.com
Cc: cooperyan@zhaoxin.com
Cc: benjaminpan@viatech.com
Link: https://lkml.kernel.org/r/1516616057-5158-1-git-send-email-davidwang@zhaoxin.com
Diffstat (limited to 'drivers/acpi')
| -rw-r--r-- | drivers/acpi/processor_idle.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index d50a7b6ccddd..5f0071c7e2e1 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -207,6 +207,7 @@ static void tsc_check_state(int state) switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: case X86_VENDOR_INTEL: + case X86_VENDOR_CENTAUR: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set. |