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author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-01-10 18:00:31 +0100 |
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committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-01-10 18:00:31 +0100 |
commit | 78e6e4dfd8f0cbb477a6f9571123edcbd5873c28 (patch) | |
tree | 1bfc1f2215481b45ccc83279533be83f4d66940c /drivers/acpi | |
parent | Merge branches 'pm-cpuidle', 'pm-core' and 'pm-sleep' (diff) | |
parent | Merge branch 'opp/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/gi... (diff) | |
parent | Merge tag 'devfreq-next-for-5.17' of git://git.kernel.org/pub/scm/linux/kerne... (diff) | |
parent | Merge back earlier power capping changes for v5.17 (diff) | |
download | linux-78e6e4dfd8f0cbb477a6f9571123edcbd5873c28.tar.xz linux-78e6e4dfd8f0cbb477a6f9571123edcbd5873c28.zip |
Merge branches 'pm-opp', 'pm-devfreq' and 'powercap'
Merge an operating performance points (OPP) update, devfreq updates
and power capping updates for 5.17-rc1:
- Update outdated OPP documentation (Tang Yizhou).
- Reduce log severity for informative message regarding frequency
transition failures in devfreq (Tzung-Bi Shih).
- Add DRAM frequency controller devfreq driver for Allwinner sunXi
SoCs (Samuel Holland).
- Add missing COMMON_CLK dependency to the sun8i devfreq driver (Arnd
Bergmann).
- Add support for new layout of Psys PowerLimit Register on SPR to
the Intel RAPL power capping driver (Zhang Rui).
- Fix typo in a comment in idle_inject.c (Jason Wang).
- Remove unused function definition from the DTPM (Dynamit Thermal
Power Management) power capping framework (Daniel Lezcano).
- Reduce DTPM trace verbosity (Daniel Lezcano).
* pm-opp:
Documentation: power: Update outdated contents in opp.rst
* pm-devfreq:
PM / devfreq: Reduce log severity for informative message
PM / devfreq: sun8i: addd COMMON_CLK dependency
PM / devfreq: Add a driver for the sun8i/sun50i MBUS
* powercap:
powercap/drivers/dtpm: Reduce trace verbosity
powercap/drivers/dtpm: Remove unused function definition
powercap: fix typo in a comment in idle_inject.c
powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR