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authorArvind Yadav <arvind.yadav.cs@gmail.com>2017-11-25 12:17:35 +0100
committerTejun Heo <tj@kernel.org>2017-11-27 20:46:26 +0100
commit20f9ceed72f127e4cc44c0358160e6e0118f823d (patch)
treeeee2eab65b4397845a8c67792eb0b254a4d6c2d7 /drivers/ata/pata_pdc2027x.c
parentpata_pdc2027x: Remove unnecessary error check (diff)
downloadlinux-20f9ceed72f127e4cc44c0358160e6e0118f823d.tar.xz
linux-20f9ceed72f127e4cc44c0358160e6e0118f823d.zip
pata_pdc2027x : make pdc2027x_*_timing structures const
Make these pdc2027x_*_timing structures const as it is never modified. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata/pata_pdc2027x.c')
-rw-r--r--drivers/ata/pata_pdc2027x.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index 4a9d532bdbb8..6db2e34bd52f 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -82,7 +82,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
* is issued to the device. However, if the controller clock is 133MHz,
* the following tables must be used.
*/
-static struct pdc2027x_pio_timing {
+static const struct pdc2027x_pio_timing {
u8 value0, value1, value2;
} pdc2027x_pio_timing_tbl[] = {
{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
@@ -92,7 +92,7 @@ static struct pdc2027x_pio_timing {
{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
};
-static struct pdc2027x_mdma_timing {
+static const struct pdc2027x_mdma_timing {
u8 value0, value1;
} pdc2027x_mdma_timing_tbl[] = {
{ 0xdf, 0x5f }, /* MDMA mode 0 */
@@ -100,7 +100,7 @@ static struct pdc2027x_mdma_timing {
{ 0x69, 0x25 }, /* MDMA mode 2 */
};
-static struct pdc2027x_udma_timing {
+static const struct pdc2027x_udma_timing {
u8 value0, value1, value2;
} pdc2027x_udma_timing_tbl[] = {
{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */