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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-10-09 15:12:39 +0200 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-10-24 17:07:23 +0200 |
| commit | 4ff7e3b65c8e1d8062365296b738fd262cfc2e9c (patch) | |
| tree | 68b7dbcd0779ef82842675754ea16fa7929a08fd /drivers/ata/sata_dwc_460ex.c | |
| parent | ARM: OMAP3: use CLK_SET_RATE_PARENT for dss clocks (diff) | |
| download | linux-4ff7e3b65c8e1d8062365296b738fd262cfc2e9c.tar.xz linux-4ff7e3b65c8e1d8062365296b738fd262cfc2e9c.zip | |
ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them, I didn't touch them.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'drivers/ata/sata_dwc_460ex.c')
0 files changed, 0 insertions, 0 deletions