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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-02-03 22:26:40 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-02-21 17:24:10 +0100 |
| commit | 9bd405c48b0ac4de087c0c4440fd79597201b8a7 (patch) | |
| tree | d54faaeb05d7cdaf7923a67cf0a3315120dc4546 /drivers/cache | |
| parent | Linux 6.8-rc1 (diff) | |
| download | linux-9bd405c48b0ac4de087c0c4440fd79597201b8a7.tar.xz linux-9bd405c48b0ac4de087c0c4440fd79597201b8a7.zip | |
cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback()
Align the end size to cache boundary size in ax45mp_dma_cache_wback()
callback likewise done in ax45mp_dma_cache_inv() callback.
Additionally return early in case of start == end.
Fixes: d34599bcd2e4 ("cache: Add L2 cache management for Andes AX45MP RISC-V core")
Reported-by: Pavel Machek <pavel@denx.de>
Link: https://lore.kernel.org/cip-dev/ZYsdKDiw7G+kxQ3m@duo.ucw.cz/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/cache')
| -rw-r--r-- | drivers/cache/ax45mp_cache.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c index 57186c58dc84..1d7dd3d2c101 100644 --- a/drivers/cache/ax45mp_cache.c +++ b/drivers/cache/ax45mp_cache.c @@ -129,8 +129,12 @@ static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size) unsigned long line_size; unsigned long flags; + if (unlikely(start == end)) + return; + line_size = ax45mp_priv.ax45mp_cache_line_size; start = start & (~(line_size - 1)); + end = ((end + line_size - 1) & (~(line_size - 1))); local_irq_save(flags); ax45mp_cpu_dcache_wb_range(start, end); local_irq_restore(flags); |