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authorJesse Barnes <jbarnes@virtuousgeek.org>2012-06-15 20:55:22 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-06-20 22:49:46 +0200
commite597dad846bafe6c9802c9ae2a94d755c5567de9 (patch)
tree8c2661d03b7bd250ed0701ca35a9f46b957bf181 /drivers/char/agp/intel-gtt.c
parentagp/intel: allow cacheable and GDFT PTEs on ValleyView (diff)
downloadlinux-e597dad846bafe6c9802c9ae2a94d755c5567de9.tar.xz
linux-e597dad846bafe6c9802c9ae2a94d755c5567de9.zip
agp/intel: use correct GTT offset on VLV
VLV is a gen7 device, but we don't currently handle that in the switch. So add it and write the PTEs correctly. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 692610e597db..9ed92ef5829b 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1253,6 +1253,7 @@ static int i9xx_setup(void)
switch (INTEL_GTT_GEN) {
case 5:
case 6:
+ case 7:
gtt_offset = MB(2);
break;
case 4: